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memtest for ffm-lfe5 (untested)

master
emard 3 months ago
parent
commit
3949891ef7
5 changed files with 1348 additions and 0 deletions
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      constraints/FFM-LFE5U-V0r0_mit_FFC-CA7-V2r0.lpf
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      examples/sdram/memtest_mister/hdl/top/top_ffm_memtest.v
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      examples/sdram/memtest_mister/proj/ffmlfe5_memtest/makefile
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      examples/sdram/memtest_mister/proj/ffmlfe5_memtest/makefile-720x480.diamond
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      examples/sdram/memtest_mister/proj/ffmlfe5_memtest/makefile-720x480.trellis

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constraints/FFM-LFE5U-V0r0_mit_FFC-CA7-V2r0.lpf View File

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# Generated by makeLPF.ulp developed by Sven Raiser, Tuebingen, Germany
#
# Board: Y:/___/FFM-LFE5U/FFM-LFE5U-V0r0.brd
# Part Name: FPGA
# Part pkg: CABGA-554
# Created: 14.05.2018 06:30:59
LOCATE COMP "clk_100mhz_p" SITE "K4";
LOCATE COMP "clk_100mhz_n" SITE "L4";
FREQUENCY PORT "clk_100mhz_p" 100 MHZ;
IOBUF PORT "clk_100mhz_p" IO_TYPE=LVDS DRIVE=4;
IOBUF PORT "clk_100mhz_n" IO_TYPE=LVDS DRIVE=4;
# JTAG and SPI FLASH voltage 3.3V and options to boot from SPI flash
SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=ENABLE SLAVE_PARALLEL_PORT=DISABLE;
# LEDs
LOCATE COMP "led[1]" SITE "F1";
IOBUF PORT "led[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
# LED2 disconnected on new schematics?
LOCATE COMP "led[2]" SITE "H1";
IOBUF PORT "led[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "led[3]" SITE "K1";
IOBUF PORT "led[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
# Serial ports FT4232
LOCATE COMP "uart1_txd" SITE "B10";
IOBUF PORT "uart1_txd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "uart1_rxd" SITE "C10";
IOBUF PORT "uart1_rxd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "uart1_cts" SITE "C9";
IOBUF PORT "uart1_cts" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "uart1_rts" SITE "D8";
IOBUF PORT "uart1_rts" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "uart2_txd" SITE "D13";
IOBUF PORT "uart2_txd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "uart2_rxd" SITE "E13";
IOBUF PORT "uart2_rxd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "uart2_rts" SITE "D11";
IOBUF PORT "uart2_rts" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "uart3_rxd" SITE "N21";
IOBUF PORT "uart3_rxd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "uart3_txd" SITE "N22";
IOBUF PORT "uart3_txd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
# SDRAM 32-bit wide (IS42s32160F-6bli)
LOCATE COMP "dr_cs_n" SITE "AE26";
IOBUF PORT "dr_cs_n" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_cke" SITE "U23";
IOBUF PORT "dr_cke" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_clk" SITE "H25";
IOBUF PORT "dr_clk" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_ras_n" SITE "R26";
IOBUF PORT "dr_ras_n" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_cas_n" SITE "U25";
IOBUF PORT "dr_cas_n" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_we_n" SITE "T24";
IOBUF PORT "dr_we_n" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_a[0]" SITE "M26";
IOBUF PORT "dr_a[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_a[1]" SITE "N26";
IOBUF PORT "dr_a[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_a[2]" SITE "K24";
IOBUF PORT "dr_a[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_a[3]" SITE "M24";
IOBUF PORT "dr_a[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_a[4]" SITE "P21";
IOBUF PORT "dr_a[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_a[5]" SITE "R24";
IOBUF PORT "dr_a[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_a[6]" SITE "P26";
IOBUF PORT "dr_a[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_a[7]" SITE "T22";
IOBUF PORT "dr_a[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_a[8]" SITE "R21";
IOBUF PORT "dr_a[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_a[9]" SITE "AA26";
IOBUF PORT "dr_a[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_a[10]" SITE "N24";
IOBUF PORT "dr_a[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_a[11]" SITE "AB26";
IOBUF PORT "dr_a[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_a[12]" SITE "W26";
IOBUF PORT "dr_a[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_ba[0]" SITE "T25";
IOBUF PORT "dr_ba[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_ba[1]" SITE "AC26";
IOBUF PORT "dr_ba[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_d[0]" SITE "AD25";
IOBUF PORT "dr_d[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_d[1]" SITE "W23";
IOBUF PORT "dr_d[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_d[2]" SITE "AE25";
IOBUF PORT "dr_d[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_d[3]" SITE "AA24";
IOBUF PORT "dr_d[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_d[4]" SITE "AB24";
IOBUF PORT "dr_d[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_d[5]" SITE "W25";
IOBUF PORT "dr_d[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_d[6]" SITE "W24";
IOBUF PORT "dr_d[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_d[7]" SITE "V23";
IOBUF PORT "dr_d[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_d[8]" SITE "V24";
IOBUF PORT "dr_d[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_d[9]" SITE "W21";
IOBUF PORT "dr_d[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_d[10]" SITE "U22";
IOBUF PORT "dr_d[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_d[11]" SITE "W22";
IOBUF PORT "dr_d[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_d[12]" SITE "AA25";
IOBUF PORT "dr_d[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_d[13]" SITE "AA22";
IOBUF PORT "dr_d[13]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_d[14]" SITE "AB25";
IOBUF PORT "dr_d[14]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_d[15]" SITE "AA23";
IOBUF PORT "dr_d[15]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_d[16]" SITE "T26";
IOBUF PORT "dr_d[16]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_d[17]" SITE "R23";
IOBUF PORT "dr_d[17]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_d[18]" SITE "P25";
IOBUF PORT "dr_d[18]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_d[19]" SITE "L24";
IOBUF PORT "dr_d[19]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_d[20]" SITE "P24";
IOBUF PORT "dr_d[20]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_d[21]" SITE "L25";
IOBUF PORT "dr_d[21]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_d[22]" SITE "P23";
IOBUF PORT "dr_d[22]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_d[23]" SITE "J24";
IOBUF PORT "dr_d[23]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_d[24]" SITE "H26";
IOBUF PORT "dr_d[24]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_d[25]" SITE "J26";
IOBUF PORT "dr_d[25]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_d[26]" SITE "H24";
IOBUF PORT "dr_d[26]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_d[27]" SITE "K25";
IOBUF PORT "dr_d[27]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_d[28]" SITE "K26";
IOBUF PORT "dr_d[28]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_d[29]" SITE "P22";
IOBUF PORT "dr_d[29]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_d[30]" SITE "L26";
IOBUF PORT "dr_d[30]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_d[31]" SITE "N23";
IOBUF PORT "dr_d[31]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_dqm[0]" SITE "U26";
IOBUF PORT "dr_dqm[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_dqm[1]" SITE "V26";
IOBUF PORT "dr_dqm[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_dqm[2]" SITE "T23";
IOBUF PORT "dr_dqm[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dr_dqm[3]" SITE "N25";
IOBUF PORT "dr_dqm[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
# Micro SD card
LOCATE COMP "sd_m_clk" SITE "L22";
IOBUF PORT "sd_m_clk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "sd_m_cmd" SITE "K21";
IOBUF PORT "sd_m_cmd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "sd_m_d[0]" SITE "K22";
IOBUF PORT "sd_m_d[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "sd_m_d[1]" SITE "J21";
IOBUF PORT "sd_m_d[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "sd_m_d[2]" SITE "H21";
IOBUF PORT "sd_m_d[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "sd_m_d[3]" SITE "J23";
IOBUF PORT "sd_m_d[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "sd_m_cdet" SITE "M21";
IOBUF PORT "sd_m_cdet" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
# Low-cost digital video TMS141
LOCATE COMP "vid_d_n[0]" SITE "T5"; # blue -
IOBUF PORT "vid_d_n[0]" IO_TYPE=LVCMOS33D DRIVE=4;
LOCATE COMP "vid_d_p[0]" SITE "R4"; # blue +
IOBUF PORT "vid_d_p[0]" IO_TYPE=LVCMOS33D DRIVE=4;
LOCATE COMP "vid_d_n[1]" SITE "U2"; # green -
IOBUF PORT "vid_d_n[1]" IO_TYPE=LVCMOS33D DRIVE=4;
LOCATE COMP "vid_d_p[1]" SITE "V1"; # green +
IOBUF PORT "vid_d_p[1]" IO_TYPE=LVCMOS33D DRIVE=4;
LOCATE COMP "vid_d_n[2]" SITE "U3"; # red -
IOBUF PORT "vid_d_n[2]" IO_TYPE=LVCMOS33D DRIVE=4;
LOCATE COMP "vid_d_p[2]" SITE "T3"; # red +
IOBUF PORT "vid_d_p[2]" IO_TYPE=LVCMOS33D DRIVE=4;
LOCATE COMP "vid_d_n[3]" SITE "J3"; # clock -
IOBUF PORT "vid_d_n[3]" IO_TYPE=LVCMOS33D DRIVE=4;
LOCATE COMP "vid_d_p[3]" SITE "H3"; # clock +
IOBUF PORT "vid_d_p[3]" IO_TYPE=LVCMOS33D DRIVE=4;
LOCATE COMP "vid_rscl" SITE "W4";
IOBUF PORT "vid_rscl" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "vid_rsda" SITE "W5";
IOBUF PORT "vid_rsda" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "vid_src" SITE "W6";
IOBUF PORT "vid_src" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
# Digital video ADV7513
LOCATE COMP "dv_clk" SITE "D2";
IOBUF PORT "dv_clk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dv_sda" SITE "F2";
IOBUF PORT "dv_sda" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dv_scl" SITE "H4";
IOBUF PORT "dv_scl" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dv_int" SITE "J4";
IOBUF PORT "dv_int" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dv_de" SITE "K6";
IOBUF PORT "dv_de" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dv_hsync" SITE "L5";
IOBUF PORT "dv_hsync" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dv_vsync" SITE "M4";
IOBUF PORT "dv_vsync" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dv_spdif" SITE "F5";
IOBUF PORT "dv_spdif" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dv_mclk" SITE "C4";
IOBUF PORT "dv_mclk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dv_i2s[0]" SITE "E4";
IOBUF PORT "dv_i2s[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dv_i2s[1]" SITE "C3";
IOBUF PORT "dv_i2s[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dv_i2s[2]" SITE "F4";
IOBUF PORT "dv_i2s[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dv_i2s[3]" SITE "F3";
IOBUF PORT "dv_i2s[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dv_sclk" SITE "H5";
IOBUF PORT "dv_sclk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dv_lrclk" SITE "K5";
IOBUF PORT "dv_lrclk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dv_d[23]" SITE "A15";
IOBUF PORT "dv_d[23]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dv_d[22]" SITE "A12";
IOBUF PORT "dv_d[22]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dv_d[21]" SITE "A13";
IOBUF PORT "dv_d[21]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dv_d[20]" SITE "A10";
IOBUF PORT "dv_d[20]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dv_d[19]" SITE "A11";
IOBUF PORT "dv_d[19]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dv_d[18]" SITE "B17";
IOBUF PORT "dv_d[18]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dv_d[17]" SITE "C17";
IOBUF PORT "dv_d[17]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dv_d[16]" SITE "B16";
IOBUF PORT "dv_d[16]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dv_d[15]" SITE "C16";
IOBUF PORT "dv_d[15]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dv_d[14]" SITE "C13";
IOBUF PORT "dv_d[14]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dv_d[13]" SITE "C14";
IOBUF PORT "dv_d[13]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dv_d[12]" SITE "C11";
IOBUF PORT "dv_d[12]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dv_d[11]" SITE "B11";
IOBUF PORT "dv_d[11]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dv_d[10]" SITE "A8";
IOBUF PORT "dv_d[10]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dv_d[9]" SITE "A9";
IOBUF PORT "dv_d[9]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dv_d[8]" SITE "B8";
IOBUF PORT "dv_d[8]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dv_d[7]" SITE "C8";
IOBUF PORT "dv_d[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dv_d[6]" SITE "D6";
IOBUF PORT "dv_d[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dv_d[5]" SITE "C6";
IOBUF PORT "dv_d[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dv_d[4]" SITE "A6";
IOBUF PORT "dv_d[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dv_d[3]" SITE "B6";
IOBUF PORT "dv_d[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dv_d[2]" SITE "A5";
IOBUF PORT "dv_d[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dv_d[1]" SITE "A4";
IOBUF PORT "dv_d[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dv_d[0]" SITE "A3";
IOBUF PORT "dv_d[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
# Display Port
LOCATE COMP "dp_aux_n[0]" SITE "P1";
IOBUF PORT "dp_aux_n[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dp_aux_n[1]" SITE "N2";
IOBUF PORT "dp_aux_n[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dp_aux_p[0]" SITE "P2";
IOBUF PORT "dp_aux_p[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dp_aux_p[1]" SITE "N1";
IOBUF PORT "dp_aux_p[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "dp_hpd" SITE "W3";
IOBUF PORT "dp_hpd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
# USB USB3340
LOCATE COMP "usb_oc" SITE "D23";
IOBUF PORT "usb_oc" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "usb_clk" SITE "L23";
FREQUENCY PORT "usb_clk" 60 MHZ;
IOBUF PORT "usb_clk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "usb_dir" SITE "C23";
IOBUF PORT "usb_dir" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "usb_nxt" SITE "C24";
IOBUF PORT "usb_nxt" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "usb_stp" SITE "B24";
IOBUF PORT "usb_stp" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "usb_d[0]" SITE "B26";
IOBUF PORT "usb_d[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "usb_d[1]" SITE "C25";
IOBUF PORT "usb_d[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "usb_d[2]" SITE "C26";
IOBUF PORT "usb_d[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "usb_d[3]" SITE "D25";
IOBUF PORT "usb_d[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "usb_d[4]" SITE "D26";
IOBUF PORT "usb_d[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "usb_d[5]" SITE "E26";
IOBUF PORT "usb_d[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "usb_d[6]" SITE "F24";
IOBUF PORT "usb_d[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "usb_d[7]" SITE "F26";
IOBUF PORT "usb_d[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
# Ethernet DP83848
LOCATE COMP "eth_clk" SITE "K23";
FREQUENCY PORT "eth_clk" 50 MHZ;
IOBUF PORT "eth_clk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "eth_crs_dev" SITE "F22";
IOBUF PORT "eth_crs_dev" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "eth_mdc" SITE "E24";
IOBUF PORT "eth_mdc" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "eth_mdio" SITE "E23";
IOBUF PORT "eth_mdio" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "eth_rxd[0]" SITE "H22";
IOBUF PORT "eth_rxd[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "eth_rxd[1]" SITE "F23";
IOBUF PORT "eth_rxd[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "eth_txd[0]" SITE "M23";
IOBUF PORT "eth_txd[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "eth_txd[1]" SITE "D24";
IOBUF PORT "eth_txd[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "eth_tx_en" SITE "H23";
IOBUF PORT "eth_tx_en" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
# FIO ports (GPIO)
LOCATE COMP "fioa[0]" SITE "E17";
IOBUF PORT "fioa[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "fioa[1]" SITE "D17";
IOBUF PORT "fioa[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "fioa[2]" SITE "D16";
IOBUF PORT "fioa[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "fioa[3]" SITE "E16";
IOBUF PORT "fioa[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "fioa[4]" SITE "E14";
IOBUF PORT "fioa[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "fioa[5]" SITE "B14";
IOBUF PORT "fioa[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "fioa[6]" SITE "D14";
IOBUF PORT "fioa[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "fioa[7]" SITE "B13";
IOBUF PORT "fioa[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "fiob[20]" SITE "E8";
IOBUF PORT "fiob[20]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "fiob[21]" SITE "J6";
IOBUF PORT "fiob[21]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "fiob[22]" SITE "H6";
IOBUF PORT "fiob[22]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "fiob[23]" SITE "E6";
IOBUF PORT "fiob[23]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "fiob[24]" SITE "D5";
IOBUF PORT "fiob[24]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "fiob[25]" SITE "C5";
IOBUF PORT "fiob[25]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "fiob[26]" SITE "D4";
IOBUF PORT "fiob[26]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "fiob[27]" SITE "B4";
IOBUF PORT "fiob[27]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "fiob[28]" SITE "D3";
IOBUF PORT "fiob[28]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "fiob[29]" SITE "B3";
IOBUF PORT "fiob[29]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "fiob[30]" SITE "E3";
IOBUF PORT "fiob[30]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "fiob[31]" SITE "C2";
IOBUF PORT "fiob[31]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "fioc[47]" SITE "A24";
IOBUF PORT "fioc[47]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "fioc[48]" SITE "A25";
IOBUF PORT "fioc[48]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "fioc[49]" SITE "A23";
IOBUF PORT "fioc[49]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "fioc[50]" SITE "B23";
IOBUF PORT "fioc[50]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "fioc[51]" SITE "C22";
IOBUF PORT "fioc[51]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "fioc[52]" SITE "D22";
IOBUF PORT "fioc[52]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "fioc[53]" SITE "B21";
IOBUF PORT "fioc[53]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "fioc[54]" SITE "C21";
IOBUF PORT "fioc[54]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "fioc[55]" SITE "A21";
IOBUF PORT "fioc[55]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "fioc[56]" SITE "A22";
IOBUF PORT "fioc[56]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "fioc[57]" SITE "D21";
IOBUF PORT "fioc[57]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "fioc[58]" SITE "E21";
IOBUF PORT "fioc[58]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "fioc[59]" SITE "E19";
IOBUF PORT "fioc[59]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "fioc[60]" SITE "D19";
IOBUF PORT "fioc[60]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "fioc[61]" SITE "C19";
IOBUF PORT "fioc[61]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "fioc[62]" SITE "B19";
IOBUF PORT "fioc[62]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "fioc[63]" SITE "C18";
IOBUF PORT "fioc[63]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "fioc[64]" SITE "D18";
IOBUF PORT "fioc[64]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "fioc[65]" SITE "A18";
IOBUF PORT "fioc[65]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "fioc[66]" SITE "A19";
IOBUF PORT "fioc[66]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "fioc[67]" SITE "A16";
IOBUF PORT "fioc[67]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "fioc[68]" SITE "A17";
IOBUF PORT "fioc[68]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "fioc[69]" SITE "A14";
IOBUF PORT "fioc[69]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
# FPGA config signal lines and unsorted stuff
#LOCATE COMP "fc_done" SITE "AC4";
#IOBUF PORT "fc_done" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
#LOCATE COMP "fc_init_nconfig" SITE "AF3";
#IOBUF PORT "fc_init_nconfig" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
#LOCATE COMP "fc_prog_nstatus" SITE "AB4";
#IOBUF PORT "fc_prog_nstatus" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
#LOCATE COMP "SS0" SITE "E11";
#IOBUF PORT "SS0" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
#LOCATE COMP "SS2/FPGA" SITE "E10";
#IOBUF PORT "SS2/FPGA" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
#LOCATE COMP "SS3/OSD" SITE "D10";
#IOBUF PORT "SS3/OSD" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
#LOCATE COMP "SS4/SD_DIRECT" SITE "D9";
#IOBUF PORT "SS4/SD_DIRECT" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
#LOCATE COMP "FPGA_CCLK_INTERNAL" SITE "AE3";
#IOBUF PORT "FPGA_CCLK_INTERNAL" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
#LOCATE COMP "FPGA_CFG_0" SITE "AF4";
#IOBUF PORT "FPGA_CFG_0" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
#LOCATE COMP "FPGA_CFG_1" SITE "AE4";
#IOBUF PORT "FPGA_CFG_1" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
#LOCATE COMP "FPGA_CFG_2" SITE "AD4";
#IOBUF PORT "FPGA_CFG_2" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
#LOCATE COMP "FPGA_CSO" SITE "AA2";
#IOBUF PORT "FPGA_CSO" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
#LOCATE COMP "FPGA_D02" SITE "AF2";
#IOBUF PORT "FPGA_D02" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
#LOCATE COMP "FPGA_D03" SITE "AE1";
#IOBUF PORT "FPGA_D03" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
#LOCATE COMP "FPGA_MISO_INTERNAL" SITE "AD2";
#IOBUF PORT "FPGA_MISO_INTERNAL" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
#LOCATE COMP "FPGA_MOSI" SITE "AE2";
#IOBUF PORT "FPGA_MOSI" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
#LOCATE COMP "FPGA_TCK" SITE "AD5";
#IOBUF PORT "FPGA_TCK" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
#LOCATE COMP "FPGA_TDI" SITE "AC5";
#IOBUF PORT "FPGA_TDI" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
#LOCATE COMP "FPGA_TDO" SITE "AB5";
#IOBUF PORT "FPGA_TDO" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
#LOCATE COMP "FPGA_TMS" SITE "AE5";
#IOBUF PORT "FPGA_TMS" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
#LOCATE COMP "PS_SRST_N" SITE "F25";
#IOBUF PORT "PS_SRST_N" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
#LOCATE COMP "PCIE_PERST_N" SITE "W1";
#IOBUF PORT "PCIE_PERST_N" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
#LOCATE COMP "PCIE_WAKE_N" SITE "W2";
#IOBUF PORT "PCIE_WAKE_N" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
#LOCATE COMP "PON_RESET_N" SITE "V6";
#IOBUF PORT "PON_RESET_N" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
# TODO
# [ ] fix schematics for dv_clk D2 not clock pin

+ 431
- 0
examples/sdram/memtest_mister/hdl/top/top_ffm_memtest.v View File

@@ -0,0 +1,431 @@
module top_ffm_memtest
(
input clk_100mhz_p, // core should use only positive when in differential mode
// input clk_100mhz_n,//- negative differential omitted
// input [6:0] btn,
output [3:1] led,
output [3:0] vid_d_p, // core should use only positive when in differential mode
// output [3:0] vid_d_n, // negative differential omitted connect only positive
// SDRAM interface (For use with 16Mx16bit or 32Mx16bit SDR DRAM, depending on version)
output dr_cs_n, // chip select
output dr_clk, // clock to SDRAM
output dr_cke, // clock enable to SDRAM
output dr_ras_n, // SDRAM RAS
output dr_cas_n, // SDRAM CAS
output dr_we_n, // SDRAM write-enable
output [12:0] dr_a, // SDRAM address bus
output [1:0] dr_ba, // SDRAM bank-address
output [3:0] dr_dqm, // byte select
inout [31:0] dr_d // data bus to/from SDRAM
);
parameter C_ddr = 1'b1; // 0:SDR 1:DDR
parameter C_clk_gui_Hz = 32'd27500000; // Hz
parameter C_clk_dr_Hz = 32'd112500000; // Hz
parameter nreset_btn = 1'b1;

localparam [31:0] C_sec_max = C_clk_gui_Hz - 1;
localparam [31:0] C_min_max = C_clk_gui_Hz*60 - 1;

localparam [15:0] C_clk_dr_1MHz = C_clk_dr_Hz / 1000000;
localparam [15:0] C_clk_dr_10MHz = C_clk_dr_1MHz / 10;
localparam [15:0] C_clk_dr_100MHz = C_clk_dr_10MHz / 10;
localparam [11:0] C_clk_dr_bcd = (C_clk_dr_100MHz % 10) * 'h100
+ (C_clk_dr_10MHz % 10) * 'h10
+ (C_clk_dr_1MHz % 10);

// wifi_gpio0=1 keeps board from rebooting
// hold btn0 to let ESP32 take control over the board
//assign wifi_gpio0 = nreset_btn;

// clock generator
wire clk_shift, clk_pixel, clk_sys;
wire clk_gui, clk_sdram;
wire locked;
clk_25_shift_pixel
clock_video_instance
(
.clkin(clk_100mhz_p),
.clk_shift(clk_shift),
.clk_pixel(clk_pixel),
.clk_sys(clk_sys),
.locked(locked)
/*
.CLKI(clk_25mhz),
.CLKOP(clk_shift),
.CLKOS(clk_pixel),
.CLKOS2(clk_sys),
.LOCK(locked)
*/
);
wire locked_sdram;
clk_25_sdram
clock_ram_instance
(
.clkin(clk_100mhz_p),
.clk_sdram(clk_sdram), // to controller soft-core
.clk_sdram_shift(dr_clk), // to SDRAM chip
.locked(locked_sdram)
/*
.CLKI(clk_25mhz),
.CLKOP(clk_sdram), // to controller soft-core
.CLKOS(dr_clk), // to SDRAM chip
.LOCK(locked_sdram)
*/
);
assign clk_gui = clk_pixel;

// LED blinky
localparam counter_width = 28;
wire [7:0] countblink;
blink
#(
.bits(counter_width)
)
blink_instance
(
.clk(clk_gui),
.led(countblink)
);
// assign led[0] = btn[1];
// assign led[7:1] = countblink[7:1];

///////////////////////////////////////////////////////////////////

///// mister board specific keyboard control
/*
reg recfg = 0;
reg pll_reset = 0;

reg [10:0] ps2_key;
wire mgmt_waitrequest;
reg mgmt_write;
reg [5:0] mgmt_address;
reg [31:0] mgmt_writedata;
wire [63:0] reconfig_to_pll;
wire [63:0] reconfig_from_pll;

wire [31:0] cfg_param[44];

reg [3:0] pos = 0;
reg auto = 0;
reg ph_shift = 0;
reg [31:0] pre_phase;

reg [7:0] state = 0;
reg old_wait;
reg [31:0] phase;
reg old_stb = 0;
reg shift = 0;

always @(posedge clk_gui)
begin

mgmt_write <= 0;

if(((locked && !mgmt_waitrequest) || pll_reset) && recfg) begin
state <= state + 1'd1;
if(!state[2:0]) begin
case(state[7:3])
// Start
0: begin
mgmt_address <= 0;
mgmt_writedata <= 0;
mgmt_write <= 1;
if(!ph_shift) pre_phase <= cfg_param[{pos, 2'd3}];
end

// M
1: begin
mgmt_address <= 4;
mgmt_writedata <= cfg_param[{pos, 2'd0}];
mgmt_write <= 1;
end

// K
2: begin
mgmt_address <= 7;
mgmt_writedata <= cfg_param[{pos, 2'd1}];
mgmt_write <= 1;
end

// N
3: begin
mgmt_address <= 3;
mgmt_writedata <= 'h10000;
mgmt_write <= 1;
end

// C0
4: begin
mgmt_address <= 5;
mgmt_writedata <= cfg_param[{pos, 2'd2}];
mgmt_write <= 1;
end

// C1
5: begin
mgmt_address <= 5;
mgmt_writedata <= cfg_param[{pos, 2'd2}] | 'h40000;
mgmt_write <= 1;
end

// Charge pump
6: begin
mgmt_address <= 9;
mgmt_writedata <= 1;
mgmt_write <= 1;
end

// Bandwidth
7: begin
mgmt_address <= 8;
mgmt_writedata <= 7;
mgmt_write <= 1;
end

// Apply
8: begin
mgmt_address <= 2;
mgmt_writedata <= 0;
mgmt_write <= 1;
end

9: pll_reset <= 1;
10: pll_reset <= 0;

// Start
11: begin
mgmt_address <= 0;
mgmt_writedata <= 0;
mgmt_write <= 1;
if(pre_phase > cfg_param[3]) phase <= pre_phase - cfg_param[3];
else
if(pre_phase < cfg_param[3]) phase <= (cfg_param[3] - pre_phase) | 'h200000;
else
begin
// no change. finish.
mgmt_write <= 0;
recfg <= 0;
end
end

// Phase
12: begin
mgmt_address <= 6;
mgmt_writedata <= phase | 'h10000;
mgmt_write <= 1;
end

// Apply
13: begin
mgmt_address <= 2;
mgmt_writedata <= 0;
mgmt_write <= 1;
end

14: recfg <= 0;
endcase
end
end

old_stb <= ps2_key[10];
if(old_stb != ps2_key[10]) begin
state <= 0;
if(ps2_key[9]) begin
if(ps2_key[7:0] == 'h75 && pos > 0) begin
recfg <= 1;
pos <= pos - 1'd1;
auto <= 0;
ph_shift <= 0;
end
if(ps2_key[7:0] == 'h72 && pos < 10) begin
recfg <= 1;
pos <= pos + 1'd1;
auto <= 0;
ph_shift <= 0;
end
if(ps2_key[7:0] == 'h5a) begin
recfg <= 1;
auto <= 0;
ph_shift <= shift;
end
if(ps2_key[7:0] == 'h1c) begin
recfg <= 1;
pos <= 0;
auto <= 1;
ph_shift <= 0;
end
if(ps2_key[7:0] == 'h74 && shift && pre_phase < 100) begin
recfg <= 1;
pre_phase <= pre_phase + 1'd1;
auto <= 0;
ph_shift <= 1;
end
if(ps2_key[7:0] == 'h6B && shift && pre_phase > 0) begin
recfg <= 1;
pre_phase <= pre_phase - 1'd1;
auto <= 0;
ph_shift <= 1;
end
end

if(ps2_key[7:0] == 'h12) shift <= ps2_key[9];
end

if(auto && failcount && !recfg && pos < 10) begin
recfg <= 1;
pos <= pos + 1'd1;
ph_shift <= 0;
end
end
*/
///////////////////////////////////////////////////////////////////

reg timer_reset;
always @(posedge clk_gui)
timer_reset <= ~(nreset_btn & locked);

reg [15:0] mins;
reg [31:0] min;
always @(posedge clk_gui)
begin
if(timer_reset) begin
min <= 0;
mins <= 0;
end else begin
if(min == C_min_max) begin
min <= 0;
if(mins[3:0]<9) mins[3:0] <= mins[3:0] + 1'd1;
else begin
mins[3:0] <= 0;
if(mins[7:4]<9) mins[7:4] <= mins[7:4] + 1'd1;
else begin
mins[7:4] <= 0;
if(mins[11:8]<9) mins[11:8] <= mins[11:8] + 1'd1;
else begin
mins[11:8] <= 0;
if(mins[15:12]<9) mins[15:12] <= mins[15:12] + 1'd1;
else mins[15:12] <= 0;
end
end
end
end
else
min <= min + 1;
end
end

reg [15:0] secs;
reg [31:0] sec;
always @(posedge clk_gui)
begin
if(timer_reset) begin
sec <= 0;
secs <= 0;
end else begin
if(sec == C_sec_max) begin
sec <= 0;
secs <= secs + 1;
end
else
sec <= sec + 1;
end
end

///////////////////////////////////////////////////////////////////

wire [31:0] passcount, failcount;

reg resetn;
always @(posedge clk_sdram)
resetn <= nreset_btn & locked_sdram;

defparam my_memtst.DRAM_COL_SIZE = 10; // 9:32MB 10:64MB
defparam my_memtst.DRAM_ROW_SIZE = 13; // don't touch
mem_tester my_memtst
(
.clk(clk_sdram),
.rst_n(resetn),
.passcount(passcount),
.failcount(failcount),
.DRAM_DQ(dr_d[15:0]),
.DRAM_ADDR(dr_a),
.DRAM_LDQM(dr_dqm[0]),
.DRAM_UDQM(dr_dqm[1]),
.DRAM_WE_N(dr_we_n),
.DRAM_CS_N(dr_cs_n),
.DRAM_RAS_N(dr_ras_n),
.DRAM_CAS_N(dr_cas_n),
.DRAM_BA_0(dr_ba[0]),
.DRAM_BA_1(dr_ba[1])
);
assign dr_cke = 1'b1;
assign dr_dqm[3:2] = 2'b11; // disable driving of upper 16-bit
// assign dr_d[31:16] = 16'hzzzz;

// most important info is failcount - lower 8 bits shown on LEDs
assign led = failcount[2:0];

// VGA signal generator
wire VGA_DE;
wire [1:0] vga_r, vga_g, vga_b;
vgaout showrez
(
.clk(clk_pixel),
.rez1(passcount),
.rez2(failcount),
// disabled to shorten compile time
// .mark(8'h80 >> secs[2:0]),
// .elapsed(mins),
// .freq(C_clk_dr_bcd),
.hs(vga_hsync),
.vs(vga_vsync),
.de(VGA_DE),
.r(vga_r),
.g(vga_g),
.b(vga_b)
);
assign vga_blank = ~VGA_DE;

// VGA to digital video converter
wire [1:0] tmds[3:0];
vga2dvid
#(
.C_depth(2),
.C_ddr(C_ddr)
)
vga2dvid_instance
(
.clk_pixel(clk_pixel),
.clk_shift(clk_shift),
.in_red(vga_r),
.in_green(vga_g),
.in_blue(vga_b),
.in_hsync(~vga_hsync),
.in_vsync(~vga_vsync),
.in_blank(vga_blank),
.out_clock(tmds[3]),
.out_red(tmds[2]),
.out_green(tmds[1]),
.out_blue(tmds[0])
);
// output TMDS SDR/DDR data to fake differential lanes
fake_differential
#(
.C_ddr(C_ddr)
)
fake_differential_instance
(
.clk_shift(clk_shift),
.in_clock(tmds[3]),
.in_red(tmds[2]),
.in_green(tmds[1]),
.in_blue(tmds[0]),
.out_p(vid_d_p),
.out_n() // .out_n(gpdi_dn)
);

endmodule

+ 1
- 0
examples/sdram/memtest_mister/proj/ffmlfe5_memtest/makefile View File

@@ -0,0 +1 @@
makefile-720x480.trellis

+ 114
- 0
examples/sdram/memtest_mister/proj/ffmlfe5_memtest/makefile-720x480.diamond View File

@@ -0,0 +1,114 @@

# SDRAM test clock
FREQ = 112.5
PHASE = 120
# ******* project, board and chip name *******
PROJECT = memtest_32MB_$(FREQ)MHz_$(PHASE)deg
BOARD = ulx3s
# 12 25 45 85
FPGA_SIZE = 85
FPGA_PACKAGE = 6bg554c
# config flash: 1:SPI (standard), 4:QSPI (quad)
FLASH_SPI = 4
# chip: is25lp032d is25lp128f s25fl164k
FLASH_CHIP = is25lp128f

# ******* if programming with OpenOCD *******
# using local latest openocd until in linux distribution
OPENOCD=openocd_ft232r
# default onboard usb-jtag
OPENOCD_INTERFACE=$(SCRIPTS)/ft231x.ocd
# ulx3s-jtag-passthru
#OPENOCD_INTERFACE=$(SCRIPTS)/ft231x2.ocd
# ulx2s
#OPENOCD_INTERFACE=$(SCRIPTS)/ft232r.ocd
# external jtag
#OPENOCD_INTERFACE=$(SCRIPTS)/ft2232.ocd

# ******* design files *******
CONSTRAINTS = ../../../../../constraints/FFM-LFE5U-V0r0_mit_FFC-CA7-V2r0.lpf
TOP_MODULE = top_ffm_memtest
TOP_MODULE_FILE = ../../hdl/top/$(TOP_MODULE).v

CLK0_NAME = clk_25_shift_pixel
CLK0_FILE_NAME = clocks/$(CLK0_NAME).v
CLK0_OPTIONS = \
--module=$(CLK0_NAME) \
--clkin_name=clkin \
--clkin=100 \
--clkout0_name=clk_shift \
--clkout0=137.5 \
--clkout1_name=clk_pixel \
--clkout1=27.5 \
--clkout2_name=clk_sys \
--clkout2=50 \

# --feedback_clkout=0 \
# --internal_feedback \

CLK1_NAME = clk_25_sdram
CLK1_FILE_NAME = clocks/$(CLK1_NAME).v
CLK1_OPTIONS = \
--module=$(CLK1_NAME) \
--clkin_name=clkin \
--clkin=100 \
--clkout0_name=clk_sdram \
--clkout0=$(FREQ) \
--clkout1_name=clk_sdram_shift \
--clkout1=$(FREQ) --phase1=$(PHASE) \

# --feedback_clkout=0 \
# --internal_feedback \

# blue v3.0.7 minimig loads "silkworms", shows demo screen but can't start game
# 85F+64MB 112.5 MHz 0-225 deg PASS (center 112.5); 234-342 deg FAIL, 234 very low error rate
# 85F+64MB 150 MHz 0-146.25, 292.5-360 deg PASS (center 40 deg); 168.75-281.25 deg FAIL
# 85F+64MB 160 MHz 45 deg PASS
# 85F+64MB 170 MHz 45 deg PASS
# 85F+64MB 180 MHz 0-45, 285-360 deg PASS (center 345 deg); 60-270 deg FAIL. 60 and 270 deg very low error rate
# 85F+64MB 190 MHz 345 deg PASS; 45 deg FAIL
# 85F+64MB 200 MHz 270-330 deg PASS (center 300 deg); 0-240, 345-360 deg FAIL

# blue v3.0.7 minimig shows red screen "menue firmware incompatible"
# 85F+64MB 112.5 MHz 0-225 deg PASS (center 112.5 deg); 234-342 deg FAIL
# 85F+64MB 180 MHz 0-15, 270-360 deg PASS (center 322 deg); 30-255 deg FAIL
# 85F+64MB 190 MHz 315 deg PASS
# 85F+64MB 200 MHz 300 deg FAIL

# green v2.1.2 minimig works
# 12F+64MB 112.5 MHz 45-243 deg PASS (center 144 deg); 0-27, 270-360 deg FAIL
# 12F+64MB 180 MHz 0 deg PASS; 135,300 deg FAIL
# 12F+64MB 190 MHz 15-60 deg PASS (center 37.5 deg); 0, 75-360 deg FAIL, 0 deg few error bits
# 12F+64MB 200 MHz 0-30, 345 deg FAIL-few error bits; 330 deg FAIL

# green v2.1.2
# 85F+32MB 190 MHz 300 deg PASS
# 85F+32MB 200 MHz 270-300 deg PASS
# 85F+32MB 220 MHz 270-300 deg PASS (center 285 deg), 0-265, 315-360 deg FAIL

VERILOG_FILES = \
$(TOP_MODULE_FILE) \
$(CLK0_FILE_NAME) \
$(CLK1_FILE_NAME) \
../../hdl/rnd_vec_gen.v \
../../hdl/sdram_control.v \
../../hdl/mem_tester.v \
../../hdl/vgaout.v \
../../../../dvi/hdl/fake_differential.v

# $(CLK0_FILE_NAME) \
# $(CLK1_FILE_NAME) \
# clkgen2/clk_25_shift_pixel/clk_25_shift_pixel.v \
# clkgen/clk_25_sdram/clk_25_sdram.v \
# clkgen/clk_25_sdram/clk_25_sdram.v \

VHDL_FILES = \
../../../../dvi/hdl/blink.vhd \
../../../../dvi/hdl/vga.vhd \
../../../../dvi/hdl/vga2dvid.vhd \
../../../../dvi/hdl/tmds_encoder.vhd

SCRIPTS = ../../../../../scripts
include $(SCRIPTS)/trellis_path.mk
include $(SCRIPTS)/diamond_path.mk
include $(SCRIPTS)/diamond_main.mk

+ 97
- 0
examples/sdram/memtest_mister/proj/ffmlfe5_memtest/makefile-720x480.trellis View File

@@ -0,0 +1,97 @@
# SDRAM test clock
FREQ = 112.5
PHASE = 120
# ******* project, board and chip name *******
PROJECT = memtest_32MB_$(FREQ)MHz_$(PHASE)deg
BOARD = ulx3s
# 12 25 45 85
FPGA_SIZE = 85
FPGA_PACKAGE = CABGA554

# ******* if programming with OpenOCD *******
# using local latest openocd until in linux distribution
OPENOCD=openocd_ft232r
# default onboard usb-jtag
OPENOCD_INTERFACE=$(SCRIPTS)/ft231x.ocd
# ulx3s-jtag-passthru
#OPENOCD_INTERFACE=$(SCRIPTS)/ft231x2.ocd
# ulx2s
#OPENOCD_INTERFACE=$(SCRIPTS)/ft232r.ocd
# external jtag
#OPENOCD_INTERFACE=$(SCRIPTS)/ft2232.ocd


# ******* design files *******
CONSTRAINTS = ../../../../../constraints/FFM-LFE5U-V0r0_mit_FFC-CA7-V2r0.lpf
TOP_MODULE = top_ffm_memtest
TOP_MODULE_FILE = ../../hdl/top/$(TOP_MODULE).v

CLK0_NAME = clk_25_shift_pixel
CLK0_FILE_NAME = clocks/$(CLK0_NAME).v
CLK0_OPTIONS = \
--module=$(CLK0_NAME) \
--clkin_name=clkin \
--clkin=100 \
--clkout0_name=clk_shift \
--clkout0=137.5 \
--clkout1_name=clk_pixel \
--clkout1=27.5 \
--clkout2_name=clk_sys \
--clkout2=50 \

# --feedback_clkout=0 \
# --internal_feedback \

CLK1_NAME = clk_25_sdram
CLK1_FILE_NAME = clocks/$(CLK1_NAME).v
CLK1_OPTIONS = \
--module=$(CLK1_NAME) \
--clkin_name=clkin \
--clkin=100 \
--clkout0_name=clk_sdram \
--clkout0=$(FREQ) \
--clkout1_name=clk_sdram_shift \
--clkout1=$(FREQ) --phase1=$(PHASE) \

# --feedback_clkout=0 \
# --internal_feedback \

VERILOG_FILES = \
$(TOP_MODULE_FILE) \
$(CLK0_FILE_NAME) \
$(CLK1_FILE_NAME) \
../../hdl/rnd_vec_gen.v \
../../hdl/sdram_control.v \
../../hdl/mem_tester.v \
../../hdl/vgaout.v \
../../../../dvi/hdl/fake_differential.v \

# *.vhd those files will be converted to *.v files with vhdl2vl (warning overwriting/deleting)
VHDL_FILES = \
../../../../dvi/hdl/blink.vhd \
../../../../dvi/hdl/vga.vhd \
../../../../dvi/hdl/vga2dvid.vhd \
../../../../dvi/hdl/tmds_encoder.vhd

# blue v3.0.7 minimig loads "silkworms", shows demo screen but can't start game
# 85F+64MB 112.5 MHz 120 deg PASS
# 85F+64MB 150 MHz 0-100,330-360 deg PASS (center 40 deg); 120-300 deg FAIL
# 85F+64MB 160 MHz 0-30,330-360 deg PASS (center 0 deg); 45-300 deg FAIL; 45 deg very low error rate
# 85F+64MB 170 MHz 0,330-360 deg PASS (center 345 deg); 30-300 deg FAIL
# 85F+64MB 180 MHz 315 deg PASS; 0-300,330-360 deg FAIL; 330 deg low error rate

# blue v3.0.7 minimig shows red screen "menue firmware incompatible"
# 85F+64MB 112.5 MHz 120 deg PASS
# 85F+64MB 170 MHz 315-345 deg PASS (center ? deg); 0-300 deg FAIL

# green v2.1.2
# 12F+64MB 170 MHz 0-120 deg PASS (center 60 deg); 135-345 deg FAIL

# synthesis options
NEXTPNR_OPTIONS = --timing-allow-fail
#NEXTPNR_OPTIONS = --timing-allow-fail --ignore-loops

SCRIPTS = ../../../../../scripts
include $(SCRIPTS)/diamond_path.mk
include $(SCRIPTS)/trellis_path.mk
include $(SCRIPTS)/trellis_main.mk

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