From a17eab2b96b329e068b88209f5d60426559decfe Mon Sep 17 00:00:00 2001
From: forksand <moe@forksand.com>
Date: Sun, 19 Dec 2021 17:40:04 -0700
Subject: [PATCH] --load works

---
 scripts/forksand-trellis-all | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/scripts/forksand-trellis-all b/scripts/forksand-trellis-all
index 50646a2..15879fe 100755
--- a/scripts/forksand-trellis-all
+++ b/scripts/forksand-trellis-all
@@ -510,17 +510,16 @@ cp -p ../pythondata-cpu-vexriscv-smp/pythondata_cpu_vexriscv_smp/verilog/ext/Vex
 #
 #
 # Load image on FPGA
-# XXX busted:
 ./make.py --board=trellisboard --load &&				\
 ######################
 # Load image on FPGA #
 ######################
 # Use this to flash since make.py broken:
-cd $FPGADIR
-openocd									\
-	-f ./prjtrellis/misc/openocd/trellisboard.cfg			\
-	-c  "init; svf litex/linux-on-litex-vexriscv/build/trellisboard/gateware/trellisboard.svf ; exit"
-cd ..
+#cd $FPGADIR
+#openocd									\
+#	-f ./prjtrellis/misc/openocd/trellisboard.cfg			\
+#	-c  "init; svf litex/linux-on-litex-vexriscv/build/trellisboard/gateware/trellisboard.svf ; exit"
+#cd ..
 ###################
 # Connect to FPGA #
 ###################