From b6aa9885bedd5df2ca16d70de72b4495febf0e30 Mon Sep 17 00:00:00 2001
From: forksand <moe@forksand.com>
Date: Sun, 19 Dec 2021 13:10:16 -0700
Subject: [PATCH] verilog no longer there

---
 scripts/forksand-trellis-all | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/scripts/forksand-trellis-all b/scripts/forksand-trellis-all
index 86a029c..6cb151a 100755
--- a/scripts/forksand-trellis-all
+++ b/scripts/forksand-trellis-all
@@ -339,9 +339,9 @@ git submodule update &&							\
 #sed -i -e 's/main_ram_size = min(main_ram_size, 0x20000000) # FIXME: limit to 512MB for now/main_ram_size = min(main_ram_size, 0x30000000) # FIXME: limit to 768MB for now/g' $FPGADIR/litex/litex/litex/soc/integration/soc_sdram.py && \
 #sed -i -e 's///g' $FPGADIR/litex/litex/litex/soc/integration/soc_core.py
 # BUILD VexRiscv.v HERE XXX
-cd litex/soc/cores/cpu/vexriscv/verilog && 				\
+#cd litex/soc/cores/cpu/vexriscv/verilog && 				\
 # Remove older builds
-rm -f *.v &&								\
+#rm -f *.v &&								\
 # BUILD VEXRISCV
 # 1m8s:
 make &&									\