no more Vexriscv-verilog. add pythondata-cpu-vexriscv

scripts/forksand-trellis-all

@@ -344,8 +344,8 @@ git submodule update &&							\
 #rm -f *.v &&								\
 # BUILD VEXRISCV
 # 1m8s:
-make &&									\
-cd ../../../../../.. &&							\
+#make &&									\
+#cd ../../../../../.. &&							\
 # Build LiteX
 # 7 seconds:
 python3 ./setup.py clean && python3 ./setup.py build && python3 ./setup.py install --user || exit
@@ -362,25 +362,39 @@ cd .. && \
 # $FPGADIR/litex/litex/litex/soc/cores/cpu/vexriscv/verilog
 #
 # Update Vexrisc-verilog
-echo "===================================== Update vexrisc-verilog"
+#echo "===================================== Update vexrisc-verilog"
 # XXX BUILD
-cd Vexriscv-verilog &&							\
-git branch -a && 							\
-git checkout master &&							\
-git reset --hard HEAD &&						\
-git status &&	 							\
-git log | head -1 | cut -f 2 -d " "
-git pull &&								\
-git submodule update &&							\
+#cd Vexriscv-verilog &&							\
+#git branch -a && 							\
+#git checkout master &&							\
+#git reset --hard HEAD &&						\
+#git status &&	 							\
+#git log | head -1 | cut -f 2 -d " "
+#git pull &&								\
+#git submodule update &&							\
 # XXX clean thusly?
 # 5 seconds:
-sbt clean reload &&							\
+#sbt clean reload &&							\
 # XXX Just checkout VexRiscv_LinuxNoDspFmax ?
 # sbt "runMain vexriscv.GenCoreDefault"
 # 10 seconds:
-sbt "runMain vexriscv.GenCoreDefault --externalInterruptArray=true --csrPluginConfig=linux-minimal" && \
+#sbt "runMain vexriscv.GenCoreDefault --externalInterruptArray=true --csrPluginConfig=linux-minimal" && \
 # XXX OUTPUT FILES:
 # VexRiscv.v VexRiscv.yaml
+#cd ..
+
+# Update pythondata-cpu-vexriscv
+echo "===================================== Update pythondata-cpu-vexriscv"
+# XXX BUILD
+cd pythondata-cpu-vexriscv &&							\
+git branch -a && 							\
+git checkout master &&							\
+git reset --hard HEAD &&						\
+git status &&	 							\
+git log | head -1 | cut -f 2 -d " "
+git pull &&								\
+git submodule update &&							\
+python3 ./setup.py clean && python3 ./setup.py build && python3 ./setup.py install --user || exit
 cd ..
 
 ########################
@@ -419,12 +433,12 @@ rm -rf $FPGADIR/litex/linux-on-litex-vexriscv/prog/trellisboard.cfg && 	\
 # root=nbd:<server>:<port>[:<fstype>][:<mountopts>]
 # XXX
 # sed -i -e 's/root=\/dev\/ram0 init=/root=nbd:192.168.1.100:8992 debug init=/g' json2dts.py
-cp -p $FPGADIR/PATCH/json2dts.py $FPGADIR/litex/linux-on-litex-vexriscv
+#cp -p $FPGADIR/PATCH/json2dts.py $FPGADIR/litex/linux-on-litex-vexriscv
 
 # TrellisBoard Patch to make.py
-patch -p0 < $FPGADIR/PATCH/0001-linuxonlitex-make.diff &&		\
+#patch -p0 < $FPGADIR/PATCH/0001-linuxonlitex-make.diff &&		\
 # TrellisBoard config
-cp -p $FPGADIR/PATCH/0000-trellisboard.cfg prog/trellisboard.cfg &&	\
+#cp -p $FPGADIR/PATCH/0000-trellisboard.cfg prog/trellisboard.cfg &&	\
 # motd :)
 cp -p $FPGADIR/PATCH/linux-on-litex-motd \
       buildroot/board/litex_vexriscv/rootfs_overlay/etc/motd && 	\
@@ -497,8 +511,8 @@ cd ..
 # lxterm /dev/ttyUSB1 --speed=1e6
 echo "Connect to FPGA thusly:" && 					\
 echo "lxterm /dev/ttyUSB1 --speed=1e6" &&				\
-lxterm /dev/ttyUSB1 --speed=1e6
-lxterm /dev/ttyUSB2 --speed=1e6
+#lxterm /dev/ttyUSB1 --speed=1e6
+#lxterm /dev/ttyUSB2 --speed=1e6
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 # MISC #
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