#!/bin/bash
#
# This updates every repo, rebuilds everything.
# Creates:
# RISC-V 32-bit core running Linux with root filesystem for ECP5 FPGA.

# Directory where everything is stored
FPGADIR=/home/jebba/devel/FPGA
# Directory of scripts
FPGASCRIPTS=$FPGADIR/muh
# Timestamp
FPGANOW=`date +%Y%m%d-%H%M%S`

# Log script
exec > >(tee $FPGADIR/log/trellis-$FPGANOW) 2>>$FPGADIR/log/trellis-$FPGANOW

set -x

cd $FPGASCRIPTS || exit

# Write log of current git commits
./forksand-fpga-git-commits-log

###################################
# Update and build icestorm tools #
###################################
cd $FPGADIR || exit

# Update Icestorm
echo "===================================== Update icestorm"
cd icestorm &&								\
git branch -a && 							\
git checkout master &&							\
git reset --hard HEAD &&						\
git status &&	 							\
git log | head -1 | cut -f 2 -d " " &&					\
git pull &&								\
git submodule update &&							\
make clean &&								\
# 18 seconds:
make -j$(nproc) &&							\
sudo make install || exit
cd ..

# Update Pjtrellis
echo "===================================== Update pjtrellis"
cd prjtrellis &&							\
git branch -a && 							\
git checkout master &&							\
git reset --hard HEAD &&						\
git status &&	 							\
git log | head -1 | cut -f 2 -d " "
git pull &&								\
git submodule update &&							\
cd libtrellis &&							\
make clean &&								\
cmake -DCMAKE_INSTALL_PREFIX=/usr/local . &&				\
# 1 second:
make -j$(nproc) &&							\
sudo make install || exit
cd ../..

# Update Nextpnr
echo "===================================== Update nextpnr"
cd nextpnr &&								\
git branch -a && 							\
git checkout master &&							\
git reset --hard HEAD &&						\
git status &&	 							\
git log | head -1 | cut -f 2 -d " "
git pull &&								\
git submodule update &&							\
make clean &&								\
cmake -DARCH=ecp5 -DCMAKE_INSTALL_PREFIX=/usr/local . &&		\
# 4m40s:
make -j$(nproc) &&							\
sudo make install || exit
cd ..

# Update Yosys
echo "===================================== Update yosys"
cd yosys &&								\
git branch -a && 							\
git checkout master &&							\
git reset --hard HEAD &&						\
git status &&	 							\
git log | head -1 | cut -f 2 -d " "
git pull &&								\
git submodule update &&							\
make clean &&								\
YOABCREV=`grep ^ABCREV Makefile |cut -f 2 -d "=" | sed -e 's/ //g'` &&	\
cd abc &&								\
git branch -a && 							\
git checkout master &&							\
git reset --hard HEAD &&						\
git pull &&								\
git submodule update &&							\
git checkout $YOABCREV &&						\
# 4 seconds:
# XXX which file XXX
#make -j$(nproc) &&							\
cd ..
make -j$(nproc) &&							\
sudo make install || exit
cd ..

# Update OpenOCD
echo "===================================== Update openocd"
cd openocd &&								\
git branch -a && 							\
git checkout master &&							\
git reset --hard HEAD &&						\
git status &&	 							\
git log | head -1 | cut -f 2 -d " "
git pull &&								\
git submodule update &&							\
make clean &&								\
# 13 seconds:
make &&									\
sudo make install || exit
cd ..

###############
# Build LiteX #
###############
cd $FPGADIR/litex

# Update Buildroot
echo "===================================== Update buildroot"
cd buildroot &&								\
git branch -a && 							\
git checkout master &&							\
git reset --hard HEAD &&						\
git status &&	 							\
git log | head -1 | cut -f 2 -d " "
git pull &&								\
git submodule update &&							\
make clean &&								\
# XXX Use custom linux.config
cp -p $FPGADIR/PATCH/linux-fstrellis.config				\
 $FPGADIR/litex/linux-on-litex-vexriscv/buildroot/board/litex_vexriscv/linux-fstrellis.config
# XXX Set up rootfs overlay files defined here:
rm -rf $FPGADIR/litex/linux-on-litex-vexriscv/buildroot/board/litex_vexriscv/rootfs_overlay
cp -a $FPGADIR/PATCH/rootfs_overlay					\
  $FPGADIR/litex/linux-on-litex-vexriscv/buildroot/board/litex_vexriscv/rootfs_overlay
# XXX Use custom defconfig
#cp -p $FPGADIR/PATCH/litex_vexriscv_fstrellis_defconfig			\
# $FPGADIR/litex/linux-on-litex-vexriscv/buildroot/configs/litex_vexriscv_fstrellis_defconfig
#make BR2_EXTERNAL=../linux-on-litex-vexriscv/buildroot/ litex_vexriscv_fstrellis_defconfig
cp -p $FPGADIR/PATCH/litex_vexriscv_fstrellis_config			\
 $FPGADIR/litex/linux-on-litex-vexriscv/buildroot/.config
# XXX update patches
mkdir -p $FPGADIR/litex/linux-on-litex-vexriscv/buildroot/board/litex_vexriscv/patches
make BR2_EXTERNAL=../linux-on-litex-vexriscv/buildroot/
# 5m16s:
make &&									\
# XXX COPY OUTPUT
# XXX *output/images/*
# Since tftp server is remote, mount it locally for convenience:
#sshfs -o reconnect sparkle:/srv/tftp/ /srv/tftp/
cp -p output/images/Image /srv/tftp/Image  &&				\
cp -p output/images/rootfs.cpio /srv/tftp/rootfs.cpio &&		\
cp -p output/images/rootfs.tar /srv/tftp/rootfs.tar &&			\
# Where dtb dts ? ./linux-on-litex-vexriscv/buildroot/rv32.dtb

cd ..

# Update migen
echo "===================================== Update migen"
cd migen &&								\
git branch -a && 							\
git checkout master &&							\
git reset --hard HEAD &&						\
git status &&	 							\
git log | head -1 | cut -f 2 -d " "
git pull &&								\
git submodule update &&							\
# 1 second:
python3 ./setup.py clean && python3 ./setup.py build && python3 ./setup.py install --user || exit
cd ..

# Update litedram
echo "===================================== Update litedram"
cd litedram &&								\
git branch -a && 							\
git checkout master &&							\
git reset --hard HEAD &&						\
git status &&	 							\
git log | head -1 | cut -f 2 -d " "
git pull &&								\
git submodule update &&							\
# 1 second:
python3 ./setup.py clean && python3 ./setup.py build && python3 ./setup.py install --user || exit
cd ..

# Update liteeth
echo "===================================== Update liteeth"
cd liteeth &&								\
git branch -a && 							\
git checkout master &&							\
git reset --hard HEAD &&						\
git status &&	 							\
git log | head -1 | cut -f 2 -d " "
git pull &&								\
git submodule update &&							\
# 1 second:
python3 ./setup.py clean && python3 ./setup.py build && python3 ./setup.py install --user || exit
cd ..

# Update litepcie
echo "===================================== Update litepcie"
cd litepcie &&								\
git branch -a && 							\
git checkout master &&							\
git reset --hard HEAD &&						\
git status &&	 							\
git log | head -1 | cut -f 2 -d " "
git pull &&								\
git submodule update &&							\
# 1 second:
python3 ./setup.py clean && python3 ./setup.py build && python3 ./setup.py install --user || exit
cd ..

# Update litesdcard
echo "===================================== Update litesdcard"
cd litesdcard &&							\
git branch -a && 							\
git checkout master &&							\
git reset --hard HEAD &&						\
git status &&	 							\
git log | head -1 | cut -f 2 -d " "
git pull &&								\
git submodule update &&							\
# 1 second:
python3 ./setup.py clean && python3 ./setup.py build && python3 ./setup.py install --user || exit
cd ..

# Update litespi
echo "===================================== Update litespi"
cd litespi &&							\
git branch -a && 							\
git checkout master &&							\
git reset --hard HEAD &&						\
git status &&	 							\
git log | head -1 | cut -f 2 -d " "
git pull &&								\
git submodule update &&							\
# 1 second:
python3 ./setup.py clean && python3 ./setup.py build && python3 ./setup.py install --user || exit
cd ..

# Update litevideo
echo "===================================== Update litevideo"
cd litevideo &&								\
git branch -a && 							\
git checkout master &&							\
git reset --hard HEAD &&						\
git status &&	 							\
git log | head -1 | cut -f 2 -d " "
git pull &&								\
git submodule update &&							\
# 1 second:
python3 ./setup.py clean && python3 ./setup.py build && python3 ./setup.py install --user || exit
cd ..

# Update liteiclink
echo "===================================== Update liteiclink"
# XXX needed?
cd liteiclink &&							\
git branch -a && 							\
git checkout master &&							\
git reset --hard HEAD &&						\
git status &&	 							\
git log | head -1 | cut -f 2 -d " "
git pull &&								\
git submodule update &&							\
# 1 second:
python3 ./setup.py clean && python3 ./setup.py build && python3 ./setup.py install --user || exit
cd ..

# Update litejesd204b
echo "===================================== Update litejesd204b"
# XXX needed?
cd litejesd204b &&							\
git branch -a && 							\
git checkout master &&							\
git reset --hard HEAD &&						\
git status &&	 							\
git log | head -1 | cut -f 2 -d " "
git pull &&								\
git submodule update &&							\
# 1 second:
python3 ./setup.py clean && python3 ./setup.py build && python3 ./setup.py install --user || exit
cd ..

# Update litesata
echo "===================================== Update litesata"
# XXX needed?
cd litesata &&								\
git branch -a && 							\
git checkout master &&							\
git reset --hard HEAD &&						\
git status &&	 							\
git log | head -1 | cut -f 2 -d " "
git pull &&								\
git submodule update &&							\
# 1 second:
python3 ./setup.py clean && python3 ./setup.py build && python3 ./setup.py install --user || exit
cd ..

# Update litex-boards
echo "===================================== Update litex-boards"
# XXX BUILD
cd litex-boards &&							\
git branch -a && 							\
git checkout master &&							\
git reset --hard HEAD &&						\
git status &&	 							\
git log | head -1 | cut -f 2 -d " "
git pull &&								\
git submodule update &&							\
# 1 second:
python3 ./setup.py clean && python3 ./setup.py build && python3 ./setup.py install --user || exit
cd ..

# Update litex
echo "===================================== Update litex"
# XXX BUILD
cd litex &&								\
git branch -a && 							\
git checkout master &&							\
git reset --hard HEAD &&						\
git status &&	 							\
git log | head -1 | cut -f 2 -d " "
git pull &&								\
git submodule update &&							\
# XXX need to patch:
# XXX MEMORY PATCH AND MORE HERE
#cp -p $FPGADIR/PATCH/litex-soc_core.py					\
#      ./litex/soc/integration/soc_core.py &&	\
# XXX
# Set memory in crufty way: XXX
#sed -i -e 's/main_ram_size = min(main_ram_size, 0x20000000) # FIXME: limit to 512MB for now/main_ram_size = min(main_ram_size, 0x40000000) # FIXME: limit to 1G for now/g' $FPGADIR/litex/litex/litex/soc/integration/soc_sdram.py && \
#sed -i -e 's/main_ram_size = min(main_ram_size, 0x20000000) # FIXME: limit to 512MB for now/main_ram_size = min(main_ram_size, 0x30000000) # FIXME: limit to 768MB for now/g' $FPGADIR/litex/litex/litex/soc/integration/soc_sdram.py && \
#sed -i -e 's///g' $FPGADIR/litex/litex/litex/soc/integration/soc_core.py
# BUILD VexRiscv.v HERE XXX
#cd litex/soc/cores/cpu/vexriscv/verilog && 				\
# Remove older builds
#rm -f *.v &&								\
# BUILD VEXRISCV
# 1m8s:
#make &&									\
#cd ../../../../../.. &&							\
# Build LiteX
# 7 seconds:
python3 ./setup.py clean && python3 ./setup.py build && python3 ./setup.py install --user || exit
# REVERT memory in crufty way: XXX
#sed -i -e 's/main_ram_size = min(main_ram_size, 0x40000000) # FIXME: limit to 1G for now/main_ram_size = min(main_ram_size, 0x20000000) # FIXME: limit to 512MB for now/g' $FPGADIR/litex/litex/litex/soc/integration/soc_sdram.py && \
#sed -i -e 's/main_ram_size = min(main_ram_size, 0x30000000) # FIXME: limit to 768MB for now/main_ram_size = min(main_ram_size, 0x20000000) # FIXME: limit to 512MB for now/g' $FPGADIR/litex/litex/litex/soc/integration/soc_sdram.py && \
cd .. && \
#####################
# Build RISC-V Core #
#####################
# XXX This build is done in above LiteX subdir
# XXX So this is unused duplicate
# XXX Should this really be built here earlier???
# $FPGADIR/litex/litex/litex/soc/cores/cpu/vexriscv/verilog
#
# Update Vexrisc-verilog
#echo "===================================== Update vexrisc-verilog"
# XXX BUILD
#cd Vexriscv-verilog &&							\
#git branch -a && 							\
#git checkout master &&							\
#git reset --hard HEAD &&						\
#git status &&	 							\
#git log | head -1 | cut -f 2 -d " "
#git pull &&								\
#git submodule update &&							\
# XXX clean thusly?
# 5 seconds:
#sbt clean reload &&							\
# XXX Just checkout VexRiscv_LinuxNoDspFmax ?
# sbt "runMain vexriscv.GenCoreDefault"
# 10 seconds:
#sbt "runMain vexriscv.GenCoreDefault --externalInterruptArray=true --csrPluginConfig=linux-minimal" && \
# XXX OUTPUT FILES:
# VexRiscv.v VexRiscv.yaml
#cd ..

# Update pythondata-cpu-vexriscv
echo "===================================== Update pythondata-cpu-vexriscv"
# XXX BUILD
cd pythondata-cpu-vexriscv &&							\
git branch -a && 							\
git checkout master &&							\
git reset --hard HEAD &&						\
git status &&	 							\
git log | head -1 | cut -f 2 -d " "
git pull &&								\
git submodule update &&							\
python3 ./setup.py clean && python3 ./setup.py build && python3 ./setup.py install --user || exit
cd ..

########################
# Build Linux on LiteX #
########################

# Update Linux on LiteX Vexriscv
echo "===================================== Update linux-on-litex-vexriscv"
# XXX BUILD
cd linux-on-litex-vexriscv &&						\
git branch -a && 							\
git checkout master &&							\
git reset --hard HEAD &&						\
git status &&	 							\
git log | head -1 | cut -f 2 -d " "
git pull &&								\
git submodule update &&							\
# Clean
rm -rf $FPGADIR/litex/linux-on-litex-vexriscv/__pycache__/ &&		\
rm -rf $FPGADIR/litex/linux-on-litex-vexriscv/build &&			\
rm -rf $FPGADIR/litex/linux-on-litex-vexriscv/buildroot/rv32.dtb && 	\
rm -rf $FPGADIR/litex/linux-on-litex-vexriscv/buildroot/board/litex_vexriscv/linux-fstrellis.config && \
rm -rf $FPGADIR/litex/linux-on-litex-vexriscv/buildroot/configs/litex_vexriscv_fstrellis_defconfig && \
rm -rf $FPGADIR/litex/linux-on-litex-vexriscv/emulator/*.d &&		\
rm -rf $FPGADIR/litex/linux-on-litex-vexriscv/emulator/*.o &&		\
rm -rf $FPGADIR/litex/linux-on-litex-vexriscv/emulator/emulator.bin &&	\
rm -rf $FPGADIR/litex/linux-on-litex-vexriscv/emulator/emulator.elf &&	\
rm -rf $FPGADIR/litex/linux-on-litex-vexriscv/prog/trellisboard.cfg && 	\
# Checkout custom branch
#git checkout fs-trellis &&						\
#git status &&	 							\
#git log | head -1 | cut -f 2 -d " "
# XXX PATCH
# XXX set ramdisk_size=131072
#sed -i -e 's/root=\/dev\/ram0 init=/root=\/dev\/ram0 ramdisk_size=65536 debug init=/g' json2dts.py
# root=nbd:<server>:<port>[:<fstype>][:<mountopts>]
# XXX
# sed -i -e 's/root=\/dev\/ram0 init=/root=nbd:192.168.1.100:8992 debug init=/g' json2dts.py
#cp -p $FPGADIR/PATCH/json2dts.py $FPGADIR/litex/linux-on-litex-vexriscv

# TrellisBoard Patch to make.py
#patch -p0 < $FPGADIR/PATCH/0001-linuxonlitex-make.diff &&		\
# TrellisBoard config
#cp -p $FPGADIR/PATCH/0000-trellisboard.cfg prog/trellisboard.cfg &&	\
# motd :)
cp -p $FPGADIR/PATCH/linux-on-litex-motd \
      buildroot/board/litex_vexriscv/rootfs_overlay/etc/motd && 	\
# motd date
echo "motd date `date`" >> buildroot/board/litex_vexriscv/rootfs_overlay/etc/motd
# XXX BUILD
# XXX Add output of Vexrisc.v and buildroot etc from above
#
#
# Really need to fix:
# 2m1s:
# XXX It actually builds, then fails at the end on something else (?)
# This is now broken: XXX NOW OK
./make.py --board=trellisboard --build
#
# Temporary work around:
#cd $FPGADIR/litex/litex-boards/litex_boards/partner/targets
#rm -rf soc_ethernetsoc_trellisboard
#./trellisboard.py                                                       \
#        --with-ethernet                                                 \
#        --sys-clk-freq=75e6                                             \
#        --gateware-toolchain=trellis                                    \
#        --gateware-toolchain-path=/usr/local                            \
#        --cpu-type=vexriscv                                             \
#        --cpu-variant=linux+no-dsp                                      \
#        --csr-csv=./csr_trellisboard.csv
#
#
#
#
#
# XXX extra cruft
#cd ~/FPGADIR/litex/linux-on-litex-vexriscv &&						\
## Now comment out the line that fails in make.py and rerun to get rest of build...
#sed -i -e 's/builder.build()/#builder.build()/g' make.py &&		\
#./make.py --board=trellisboard --build &&				\
#
#
#
#
# XXX Copy to tftp server 1 file needed ?
cp -p buildroot/rv32.dtb /srv/tftp/rv32.dtb &&				\
# XXX copy to tftp server emulator.bin
cp -p emulator/emulator.bin /srv/tftp/emulator.bin &&			\
#
#
#
#
# Load image on FPGA
# XXX busted:
./make.py --board=trellisboard --load &&				\
######################
# Load image on FPGA #
######################
# Use this to flash since make.py broken:
cd $FPGADIR
openocd									\
	-f ./prjtrellis/misc/openocd/trellisboard.cfg			\
	-c  "init; svf litex/linux-on-litex-vexriscv/build/trellisboard/gateware/trellisboard.svf ; exit"
cd ..
###################
# Connect to FPGA #
###################
# lxterm
# lxterm /dev/ttyUSB1
# lxterm /dev/ttyUSB1 --speed=2e6
# lxterm /dev/ttyUSB1 --speed=1e6
echo "Connect to FPGA thusly:" && 					\
echo "lxterm /dev/ttyUSB1 --speed=1e6" &&				\
#lxterm /dev/ttyUSB1 --speed=1e6
#lxterm /dev/ttyUSB2 --speed=1e6
########
# MISC #
########
# Update GCC toolchain
#######
# END #
#######
exit 0