--- make.py.orig	2019-09-21 11:48:48.213955331 -0600
+++ make.py	2019-09-21 11:50:35.465382876 -0600
@@ -149,6 +149,16 @@
     def load(self):
         os.system("ujprog build/ulx3s/gateware/top.svf")
 
+# TrellisBoard support ------------------------------------------------------------------------------------
+
+class Trellis(Board):
+    def __init__(self):
+        from litex_boards.targets import trellisboard
+        Board.__init__(self, trellisboard.EthernetSoC, {"serial", "ethernet"})
+
+    def load(self):
+        os.system("openocd -f prog/trellisboard.cfg -c \"transport select jtag; init; svf build/trellisboard/gateware/top.svf; exit\"")
+
 # De0Nano support ------------------------------------------------------------------------------------
 
 class De0Nano(Board):
@@ -175,6 +185,7 @@
     # Lattice
     "versa_ecp5":   VersaECP5,
     "ulx3s":        ULX3S,
+    "trellisboard": Trellis,
     # Altera/Intel
     "de0nano":      De0Nano,
 }
@@ -202,7 +213,7 @@
     for board_name in board_names:
         board = supported_boards[board_name]()
         soc_kwargs = {}
-        if board_name in ["versa_ecp5", "ulx3s"]:
+        if board_name in ["versa_ecp5", "ulx3s", "trellisboard"]:
             soc_kwargs["toolchain"] = "trellis"
             soc_kwargs["cpu_variant"] = "linux+no-dsp"
         soc = SoCLinux(board.soc_cls, **soc_kwargs)