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fpga-cruft/scripts/forksand-trellis-buildroot

77 lines
2.4 KiB

#!/bin/bash
#
# Just update buildroot
# config kernel
# cd /home/jebba/devel/FPGA/litex/buildroot/output/build/linux-5.0.13
# make ARCH=riscv CROSS_COMPILE="/home/jebba/devel/FPGA/litex/buildroot/output/host/bin/riscv32-buildroot-linux-gnu-" menuconfig
# Directory where everything is stored
FPGADIR=/home/jebba/devel/FPGA
# Directory of scripts
FPGASCRIPTS=$FPGADIR/muh
# Timestamp
FPGANOW=`date +%Y%m%d-%H%M%S`
# Log script
exec > >(tee $FPGADIR/log/trellis-buildroot-$FPGANOW) 2>>$FPGADIR/log/trellis-buildroot-$FPGANOW
set -x
###############
# Build LiteX #
###############
cd $FPGADIR/litex
# Update Buildroot
echo "===================================== Build buildroot"
cd buildroot && \
# XXX Use custom linux.config
cp -p $FPGADIR/PATCH/linux-fstrellis.config \
$FPGADIR/litex/linux-on-litex-vexriscv/buildroot/board/litex_vexriscv/linux-fstrellis.config
# XXX Set up rootfs overlay files defined here:
rm -rf $FPGADIR/litex/linux-on-litex-vexriscv/buildroot/board/litex_vexriscv/rootfs_overlay
cp -a $FPGADIR/PATCH/rootfs_overlay \
$FPGADIR/litex/linux-on-litex-vexriscv/buildroot/board/litex_vexriscv/rootfs_overlay
# XXX Use custom defconfig
cp -p $FPGADIR/PATCH/litex_vexriscv_fstrellis_defconfig \
$FPGADIR/litex/linux-on-litex-vexriscv/buildroot/configs/litex_vexriscv_fstrellis_defconfig
make BR2_EXTERNAL=../linux-on-litex-vexriscv/buildroot/ litex_vexriscv_fstrellis_defconfig \
# 5m16s:
make && \
# XXX COPY OUTPUT
# XXX *output/images/*
# Since tftp server is remote, mount it locally for convenience:
sshfs -o reconnect sparkle:/srv/tftp/ /srv/tftp/
cp -p output/images/Image /srv/tftp/Image && \
cp -p output/images/rootfs.cpio /srv/tftp/rootfs.cpio && \
cp -p output/images/rootfs.tar /srv/tftp/rootfs.tar && \
# Where dtb dts ? ./linux-on-litex-vexriscv/buildroot/rv32.dtb
##################
# Linux on LiteX #
##################
cd $FPGADIR/litex/linux-on-litex-vexriscv
# Load image on FPGA
cp -p $FPGADIR/PATCH/json2dts.py $FPGADIR/litex/linux-on-litex-vexriscv
# XXX
./make.py --board=trellisboard --load
###################
# Connect to FPGA #
###################
# lxterm
# lxterm /dev/ttyUSB1
# lxterm /dev/ttyUSB1 --speed=2e6
# lxterm /dev/ttyUSB1 --speed=1e6
echo "Connect to FPGA thusly:" && \
echo "lxterm /dev/ttyUSB1 --speed=1e6" && \
echo "lxterm /dev/ttyUSB2 --speed=1e6" && \
#lxterm /dev/ttyUSB1 --speed=1e6
#lxterm /dev/ttyUSB2 --speed=1e6
exit 0