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37 lines
1.3 KiB
37 lines
1.3 KiB
--- make.py.orig 2019-10-02 19:59:51.962297746 -0600
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+++ make.py 2019-10-02 20:02:50.549344701 -0600
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@@ -149,6 +149,16 @@
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def load(self):
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os.system("ujprog build/ulx3s/gateware/top.svf")
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+# TrellisBoard support ------------------------------------------------------------------------------------
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+
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+class Trellis(Board):
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+ def __init__(self):
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+ from litex_boards.targets import trellisboard
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+ Board.__init__(self, trellisboard.EthernetSoC, "serial+ethernet")
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+
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+ def load(self):
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+ os.system("openocd -f prog/trellisboard.cfg -c \"transport select jtag; init; svf build/trellisboard/gateware/top.svf; exit\"")
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+
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# De0Nano support ------------------------------------------------------------------------------------
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class De0Nano(Board):
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@@ -175,6 +185,7 @@
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# Lattice
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"versa_ecp5": VersaECP5,
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"ulx3s": ULX3S,
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+ "trellisboard": Trellis,
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# Altera/Intel
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"de0nano": De0Nano,
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}
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@@ -202,7 +213,7 @@
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for board_name in board_names:
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board = supported_boards[board_name]()
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soc_kwargs = {}
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- if board_name in ["versa_ecp5", "ulx3s"]:
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+ if board_name in ["versa_ecp5", "ulx3s", "trellisboard"]:
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soc_kwargs["toolchain"] = "trellis"
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soc_kwargs["cpu_variant"] = "linux+no-dsp"
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if board_name in ["de0nano"]:
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