EESchema Schematic File Version 4
LIBS:ecp5_mainboard-cache
EELAYER 26 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 1 9
Title "TrellisBoard"
Date "2018-11-20"
Rev "1.0"
Comp "David Shah"
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Sheet
S 1000 900  2400 1000
U 5B5D9B41
F0 "Power" 50
F1 "power.sch" 50
$EndSheet
$Sheet
S 5300 900  1650 1000
U 5B5F5F9A
F0 "FPGA Core Power" 50
F1 "fpga_pwr.sch" 50
$EndSheet
$Sheet
S 1000 2300 2400 800 
U 62793184
F0 "Debug Interface" 50
F1 "debug.sch" 50
$EndSheet
$Sheet
S 1000 3450 2400 800 
U 5C060E84
F0 "PCIe + SATA" 50
F1 "serdes.sch" 50
$EndSheet
$Sheet
S 1000 4600 2400 800 
U 5CA09014
F0 "HDMI, GbE, USB" 50
F1 "ports.sch" 50
$EndSheet
$Sheet
S 1000 5750 2400 900 
U 610481D8
F0 "Misc IO" 50
F1 "miscio.sch" 50
$EndSheet
$Sheet
S 5300 2300 1650 750 
U 6162FA9E
F0 "DDR3" 50
F1 "ddr3.sch" 50
$EndSheet
$Sheet
S 4500 3500 2400 1700
U 61FAF948
F0 "FPGA IO" 50
F1 "fpga_io.sch" 50
$EndSheet
$EndSCHEMATC
