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EESchema Schematic File Version 4
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LIBS:ecp5_mainboard-cache
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EELAYER 29 0
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EELAYER END
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$Descr A4 11693 8268
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encoding utf-8
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Sheet 1 9
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Title "TrellisBoard"
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Date "2018-11-20"
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Rev "1.0"
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Comp "David Shah"
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Comment1 ""
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Comment2 ""
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Comment3 ""
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Comment4 ""
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$EndDescr
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$Sheet
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S 1000 900 2400 1000
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U 5B5D9B41
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F0 "Power" 50
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F1 "power.sch" 50
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$EndSheet
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$Sheet
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S 5300 900 1650 1000
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U 5B5F5F9A
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F0 "FPGA Core Power" 50
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F1 "fpga_pwr.sch" 50
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$EndSheet
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$Sheet
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S 1000 2300 2400 800
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U 62793184
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F0 "Debug Interface" 50
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F1 "debug.sch" 50
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$EndSheet
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$Sheet
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S 1000 3450 2400 800
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U 5C060E84
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F0 "PCIe + SATA" 50
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F1 "serdes.sch" 50
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$EndSheet
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$Sheet
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S 1000 4600 2400 800
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U 5CA09014
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F0 "HDMI, GbE, USB" 50
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F1 "ports.sch" 50
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$EndSheet
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$Sheet
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S 1000 5750 2400 900
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U 610481D8
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F0 "Misc IO" 50
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F1 "miscio.sch" 50
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$EndSheet
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$Sheet
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S 5300 2300 1650 750
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U 6162FA9E
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F0 "DDR3" 50
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F1 "ddr3.sch" 50
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$EndSheet
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$Sheet
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S 4500 3500 2400 1700
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U 61FAF948
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F0 "FPGA IO" 50
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F1 "fpga_io.sch" 50
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$EndSheet
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$Comp
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L Connector:Conn_01x01_Female J16
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U 1 1 5CDA154A
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P 9450 3100
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F 0 "J16" H 9478 3171 50 0000 L CNN
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F 1 "MOUNT" H 9478 3080 50 0000 L CNN
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F 2 "MountingHole:MountingHole_3.2mm_M3_Pad" H 9478 2989 50 0000 L CNN
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F 3 "~" H 9450 3100 50 0001 C CNN
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1 9450 3100
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1 0 0 -1
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$EndComp
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$Comp
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L Connector:Conn_01x01_Female J17
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U 1 1 5CDA17E7
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P 9450 3250
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F 0 "J17" H 9478 3321 50 0000 L CNN
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F 1 "MOUNT" H 9478 3230 50 0000 L CNN
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F 2 "MountingHole:MountingHole_3.2mm_M3_Pad" H 9478 3139 50 0000 L CNN
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F 3 "~" H 9450 3250 50 0001 C CNN
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1 9450 3250
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1 0 0 -1
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$EndComp
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NoConn ~ 9250 3250
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NoConn ~ 9250 3100
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$EndSCHEMATC
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