From d3a4f9b40254f7655ab0f246cac1a7ccf5bf9b0d Mon Sep 17 00:00:00 2001 From: David Shah Date: Thu, 4 Jul 2019 11:26:40 +0100 Subject: [PATCH] gateware/simple: Demo tweaks Signed-off-by: David Shah --- gateware/simple/demo.v | 27 ++++++++++++++++++++------- gateware/simple/led_ctrl.v | 8 +++++++- 2 files changed, 27 insertions(+), 8 deletions(-) diff --git a/gateware/simple/demo.v b/gateware/simple/demo.v index aee0229..d3e789f 100644 --- a/gateware/simple/demo.v +++ b/gateware/simple/demo.v @@ -7,10 +7,11 @@ module demo_top( output [11:0] led ); - reg [11:0] ctr_scroll = 1'b1; + reg [35:0] ctr_scroll; + reg [35:0] ctr_scroll_swapped; reg clk_div = 0; - localparam DIV = 21; + localparam DIV = 20; reg [DIV-1:0] div_ctr = 0; always @(posedge clk_12) begin @@ -18,17 +19,29 @@ module demo_top( if (clk_div) begin if (!(|ctr_scroll)) - ctr_scroll <= 1'b1; + ctr_scroll <= {1'b1, {10{1'b0}}, 1'b1, {13{1'b0}}, 1'b1}; else - ctr_scroll <= {ctr_scroll[10:0], ctr_scroll[11]}; + ctr_scroll <= {ctr_scroll[34:24], ctr_scroll[35], + ctr_scroll[22:12], ctr_scroll[23], + ctr_scroll[10:0], ctr_scroll[11]}; end end + integer i, j; + always @(posedge clk_12) begin + for (i = 0; i < 36; i = i + 6) + for (j = 0; j < 6; j = j + 1) + if ((i % 12) == 0) + ctr_scroll_swapped[i+j] <= ctr_scroll[i+j]; + else + ctr_scroll_swapped[i+j] <= ctr_scroll[i+5-j]; + end + led_ctrl led_ctrl_i ( .clk(clk_12), - .led_in_yr({ctr_scroll[5:0], dip_sw[1:0], btn}), - .led_in_bg({dip_sw[7:2], ctr_scroll[11:6]}), + .led_in_yr({ctr_scroll_swapped[23:12] | ctr_scroll_swapped[35:24]}), + .led_in_bg({ctr_scroll_swapped[11:0] | ctr_scroll_swapped[35:24]}), .led_pin(led) ); -endmodule \ No newline at end of file +endmodule diff --git a/gateware/simple/led_ctrl.v b/gateware/simple/led_ctrl.v index 143fa17..97b40da 100644 --- a/gateware/simple/led_ctrl.v +++ b/gateware/simple/led_ctrl.v @@ -16,6 +16,10 @@ module led_ctrl ( always @(posedge clk) ctr <= ctr + 1'b1; + wire pwm_1_4 = ctr[DIV_FACTOR - 1 : DIV_FACTOR - 2] > 2'b10; + wire pwm_7_8 = ctr[DIV_FACTOR - 1 : DIV_FACTOR - 3] > 2'b000; + + genvar i; wire [11:0] led_o, led_en; generate @@ -23,14 +27,16 @@ module led_ctrl ( /* Only YR asserted : LED at constant 1'b0 Both YR & BG asserted : blend colour by connecting LED to divider MSB + NB: bias towards yellow (i<6) or green (i>=6) for better white/orange Only BG asserted : LED at constant 1'b1 Neither asserted : LED off (1'bz) */ assign led_o[i] = led_in_yr[i] ? - (led_in_bg[i] ? ctr[DIV_FACTOR - 1] : 1'b0) : + (led_in_bg[i] ? (i < 6 ? pwm_1_4 : pwm_7_8) : 1'b0) : 1'b1; assign led_en[i] = led_in_yr[i] || led_in_bg[i]; assign led_pin[i] = led_en[i] ? led_o[i] : 1'bz; + //BB bb_i (.I(led_o[i]), .T(~led_en[i]), .B(led_pin[i])); end endgenerate