From dbb9064930c39b17bcef2049c81831d9a77e37f0 Mon Sep 17 00:00:00 2001 From: David Shah Date: Sat, 24 Nov 2018 16:34:09 +0000 Subject: [PATCH] hardware/mainboard: Set up layers and design rules Signed-off-by: David Shah --- .../ecp5_mainboard/ecp5_mainboard.kicad_pcb | 39 ++++++++++++++----- 1 file changed, 29 insertions(+), 10 deletions(-) diff --git a/hardware/ecp5_mainboard/ecp5_mainboard.kicad_pcb b/hardware/ecp5_mainboard/ecp5_mainboard.kicad_pcb index 65a2240..fe25f9d 100644 --- a/hardware/ecp5_mainboard/ecp5_mainboard.kicad_pcb +++ b/hardware/ecp5_mainboard/ecp5_mainboard.kicad_pcb @@ -12,6 +12,12 @@ (page A4) (layers (0 F.Cu signal) + (1 In1.Cu signal) + (2 In2.Cu signal) + (3 In3.Cu signal) + (4 In4.Cu signal) + (5 In5.Cu signal) + (6 In6.Cu signal) (31 B.Cu signal) (32 B.Adhes user) (33 F.Adhes user) @@ -34,17 +40,30 @@ ) (setup - (last_trace_width 0.25) - (trace_clearance 0.2) + (last_trace_width 0.0889) + (user_trace_width 0.1) + (user_trace_width 0.15) + (user_trace_width 0.2) + (user_trace_width 0.25) + (user_trace_width 0.35) + (user_trace_width 0.5) + (user_trace_width 0.8) + (user_trace_width 1) + (trace_clearance 0.0889) (zone_clearance 0.508) (zone_45_only no) - (trace_min 0.2) + (trace_min 0.0889) (segment_width 0.2) (edge_width 0.15) - (via_size 0.8) - (via_drill 0.4) + (via_size 0.4) + (via_drill 0.2) (via_min_size 0.4) - (via_min_drill 0.3) + (via_min_drill 0.2) + (user_via 0.6 0.3) + (user_via 0.8 0.5) + (user_via 1 0.6) + (user_via 1.5 1) + (user_via 2 1.5) (uvia_size 0.3) (uvia_drill 0.1) (uvias_allowed no) @@ -811,10 +830,10 @@ (net 718 "Net-(J2-Pad4)") (net_class Default "This is the default net class." - (clearance 0.2) - (trace_width 0.25) - (via_dia 0.8) - (via_drill 0.4) + (clearance 0.0889) + (trace_width 0.0889) + (via_dia 0.4) + (via_drill 0.2) (uvia_dia 0.3) (uvia_drill 0.1) (add_net +12V)