Function Test RAM #28

Function Test RAM

System boots into Linux with 256M at present.

Add TrellisBoard, 1GB hack

linux-on-litex-vexriscv daveshah1:

4bb8cd9a06

Add TrellisBoard, 1GB hack

LiteX daveshah1:

cade9717bb

litedram daveshah1:

https://github.com/daveshah1/litedram/commits/ecp5_75MHz

https://github.com/daveshah1/versa_ecp5_dram/commits/trellis2

LiteX is getting set up with 512M:

--============ SoC info ================--
CPU:       VexRiscv @ 75MHz
ROM:       32KB
SRAM:      4KB
L2:        8KB
MAIN-RAM:  524288KB

But Linux only gets 256M:

root@buildroot:~# free -m
              total        used        free      shared  buff/cache   available
Mem:            241           2         233           0           5         230
Swap:             0           0           0

This can likely be increased just by changing the Linux boot line (from dmesg):

[    0.000000] Kernel command line: mem=256M@0xc0000000 rootwait console=liteuart earlycon=sbi root=/dev/ram0 init=/sbin/init swiotlb=32

https://twitter.com/enjoy_digital/status/1176730658057654272

Enjoy Digital
@enjoy_digital
Replying to
@mithro

@realForkSand
and 5 others
To remove the limitation (https://github.com/enjoy-digital/litex/blob/master/litex/soc/integration/soc_sdram.py#L85
), the mapping needs to be modified (https://github.com/litex-hub/linux-on-litex-vexriscv/blob/master/soc_linux.py#L45-L53) as @fpga_dave
did to have 1gB address space.

Now at 512M

[    0.000000] Kernel command line: mem=512M@0xc0000000 rootwait console=liteuart earlycon=sbi root=/dev/ram0 init=/sbin/init swiotlb=32

root@buildroot:~# free 
              total        used        free      shared  buff/cache   available
Mem:         507272        3288      498688           0        5296      494692
Swap:             0           0           0

I think it is now line 65 not 85 that should be linked in the tweet above:

https://github.com/enjoy-digital/litex/blob/master/litex/soc/integration/soc_sdram.py#L65