VexRiscv #40

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opened 5 years ago by jebba · 1 comments
jebba commented 5 years ago
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Builds ok. May need features from: https://github.com/daveshah1/VexRiscv-verilog/commits/linux
jebba added this to the 1.0 milestone 5 years ago
jebba self-assigned this 5 years ago
jebba added the FPGA label 5 years ago
jebba commented 5 years ago
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https://github.com/daveshah1/VexRiscv/commits/Supervisor
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Reference: forksand/fs-TrellisBoard#40
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