From d8c12cb9e55d8508cdf1e54cb2dcbb451c73a3d3 Mon Sep 17 00:00:00 2001 From: Emard Date: Sun, 17 Feb 2019 12:44:58 +0100 Subject: [PATCH 1/7] manual update US2 bootloader and D28 soldering note for BTN0=PROGRAMN --- doc/MANUAL.md | 35 ++++++++++++++++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/doc/MANUAL.md b/doc/MANUAL.md index 504bb82..3171da3 100644 --- a/doc/MANUAL.md +++ b/doc/MANUAL.md @@ -124,7 +124,7 @@ Switching regulators use ferrite core coils L1,L2,L3 which can saturate at magnetic fields above 0.3T. Never approach neodymium magnets near powered board. -# Programming over USB +# Programming over USB port "US1" Use ftx_prog to allow max USB power consumption of 500mA and change product/manufacturer name of FT231X chip: @@ -202,6 +202,39 @@ ${CHIP_ID} and ${FILE_SVF}: svf -tap lfe5.tap -quiet -progress ${FILE_SVF} shutdown +# Programming over USB port "US2" + +There is possibility to program ULX3S SPI config flash thru +US2 connector and +a [fork of tinyfpga bootloader](https://github.com/tinyfpga/TinyFPGA-Bootloader) loaded +to FPGA, either loaded from US1 temporary to FPGA SRAM or permanently +to SPI config flash. Bootloader uses multiboot feature of ECP5 FPGA. +This programming option is experimental and not recommended for +regular use. + +ULX3S with fully functional US2 bootloader can be used without +USB-serial to JTAG chip FT231X. + +For bootloader convenience, it is recommented to solder D28 diode +at empty placeholder located on back side near OLED and JTAG header. +Observe diode polarity, see how other similar diodes are soldered on ULX3S. +Any general purpose or schottky diode in SOD-323 package will fit +like 1N914 1N4148 BAT54W etc. This diode will convert BTN0 function +to unconditionally switch to next multiboot image by pulling down +FPGA PROGRAMN pin. + +USB bootloader is in hacky state of development, you need hi quality +USB cable, a compatible PC and selected USB port and too much luck (try +all). I think bootloader's USB bus error recovery handling is wrong +but sometimes it just works. +US2 port should enumerate as some vendor specific USB-HID USB device +and "tiyfpgasp" application can be used to write or read arbitrary +image to FPGA SPI config FLASH. + +User bitstream should be uploaded to byte address 0x200000 of SPI config +FLASH. Bootloader itself resites at a0 address 0. Try not to overwrite +it with something else otherwise US1 or JTAG recovery will be required. + # Programming over JTAG header Any openocd compatible JTAG like FT2232 can be connected to JTAG header From b681e5c4f88bb0a32af3e580346f09d3871d3076 Mon Sep 17 00:00:00 2001 From: Emard Date: Sun, 17 Feb 2019 12:50:46 +0100 Subject: [PATCH 2/7] manual update --- doc/MANUAL.md | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/doc/MANUAL.md b/doc/MANUAL.md index 3171da3..931ab05 100644 --- a/doc/MANUAL.md +++ b/doc/MANUAL.md @@ -204,16 +204,16 @@ ${CHIP_ID} and ${FILE_SVF}: # Programming over USB port "US2" -There is possibility to program ULX3S SPI config flash thru +There is possibility to program ULX3S SPI config FLASH thru US2 connector and a [fork of tinyfpga bootloader](https://github.com/tinyfpga/TinyFPGA-Bootloader) loaded to FPGA, either loaded from US1 temporary to FPGA SRAM or permanently -to SPI config flash. Bootloader uses multiboot feature of ECP5 FPGA. +to SPI config FLASH. Bootloader uses multiboot feature of ECP5 FPGA. This programming option is experimental and not recommended for regular use. -ULX3S with fully functional US2 bootloader can be used without -USB-serial to JTAG chip FT231X. +ULX3S with fully functional US2 bootloader can be used to program +FPGA config FLASH without use of USB-serial chip FT231X. For bootloader convenience, it is recommented to solder D28 diode at empty placeholder located on back side near OLED and JTAG header. @@ -228,7 +228,7 @@ USB cable, a compatible PC and selected USB port and too much luck (try all). I think bootloader's USB bus error recovery handling is wrong but sometimes it just works. US2 port should enumerate as some vendor specific USB-HID USB device -and "tiyfpgasp" application can be used to write or read arbitrary +and "tinyfpgasp" application can be used to write or read arbitrary image to FPGA SPI config FLASH. User bitstream should be uploaded to byte address 0x200000 of SPI config From de636ea6cd8a4e38690ce2f59812c88bf6db44e1 Mon Sep 17 00:00:00 2001 From: Emard Date: Sun, 17 Feb 2019 12:51:43 +0100 Subject: [PATCH 3/7] manual typo --- doc/MANUAL.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/MANUAL.md b/doc/MANUAL.md index 931ab05..8fe3de5 100644 --- a/doc/MANUAL.md +++ b/doc/MANUAL.md @@ -215,7 +215,7 @@ regular use. ULX3S with fully functional US2 bootloader can be used to program FPGA config FLASH without use of USB-serial chip FT231X. -For bootloader convenience, it is recommented to solder D28 diode +For bootloader convenience, it is recommended to solder D28 diode at empty placeholder located on back side near OLED and JTAG header. Observe diode polarity, see how other similar diodes are soldered on ULX3S. Any general purpose or schottky diode in SOD-323 package will fit From 449dd31d452990c3dd77576994100124ec05c896 Mon Sep 17 00:00:00 2001 From: Emard Date: Sun, 17 Feb 2019 12:58:34 +0100 Subject: [PATCH 4/7] manual update, SPI flash addresses in multiboot mode comments --- doc/MANUAL.md | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/doc/MANUAL.md b/doc/MANUAL.md index 8fe3de5..48e3e29 100644 --- a/doc/MANUAL.md +++ b/doc/MANUAL.md @@ -232,8 +232,15 @@ and "tinyfpgasp" application can be used to write or read arbitrary image to FPGA SPI config FLASH. User bitstream should be uploaded to byte address 0x200000 of SPI config -FLASH. Bootloader itself resites at a0 address 0. Try not to overwrite -it with something else otherwise US1 or JTAG recovery will be required. +FLASH. Bootloader in multiboot mode resides in multiple copies on SPI config +FLASH chip. "primary" +bootloader image is at byte address 0 of SPI config FLASH, "golden" +bootloader image is at 0x140000 address on 45F chip but its location +varies on various sizes of FPGA 12/25/45/85F. At the last 256 bytes of +FLASH are some special FPGA lattice boot state machine commands +(like some primitive CPU assemlby) than setups and controls multiboot +function. Try not to overwrite any of boot realted areas with something +else otherwise US1 or JTAG recovery will be required. # Programming over JTAG header From 1801302c9b956521a9ea67395762e0601113142f Mon Sep 17 00:00:00 2001 From: Emard Date: Sun, 17 Feb 2019 12:59:43 +0100 Subject: [PATCH 5/7] manual update, multiboot image locations comment --- doc/MANUAL.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/MANUAL.md b/doc/MANUAL.md index 48e3e29..c188616 100644 --- a/doc/MANUAL.md +++ b/doc/MANUAL.md @@ -238,7 +238,7 @@ bootloader image is at byte address 0 of SPI config FLASH, "golden" bootloader image is at 0x140000 address on 45F chip but its location varies on various sizes of FPGA 12/25/45/85F. At the last 256 bytes of FLASH are some special FPGA lattice boot state machine commands -(like some primitive CPU assemlby) than setups and controls multiboot +(like some primitive CPU assemlby) that setups and controls multiboot function. Try not to overwrite any of boot realted areas with something else otherwise US1 or JTAG recovery will be required. From b595edb1039fd158112951f94f3a18a35dc587b5 Mon Sep 17 00:00:00 2001 From: Emard Date: Sun, 17 Feb 2019 13:02:24 +0100 Subject: [PATCH 6/7] manual multiboot note update --- doc/MANUAL.md | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/doc/MANUAL.md b/doc/MANUAL.md index c188616..f880291 100644 --- a/doc/MANUAL.md +++ b/doc/MANUAL.md @@ -232,14 +232,16 @@ and "tinyfpgasp" application can be used to write or read arbitrary image to FPGA SPI config FLASH. User bitstream should be uploaded to byte address 0x200000 of SPI config -FLASH. Bootloader in multiboot mode resides in multiple copies on SPI config +FLASH at 12/25/45F (I'm not sure for 85F). +Bootloader in multiboot mode resides in multiple copies on SPI config FLASH chip. "primary" bootloader image is at byte address 0 of SPI config FLASH, "golden" bootloader image is at 0x140000 address on 45F chip but its location varies on various sizes of FPGA 12/25/45/85F. At the last 256 bytes of FLASH are some special FPGA lattice boot state machine commands -(like some primitive CPU assemlby) that setups and controls multiboot -function. Try not to overwrite any of boot realted areas with something +(detailed meaning and format not yet known, it's like some primitive CPU assemlby) +that setups and controls multiboot function. +Try not to overwrite any of boot related areas with something else otherwise US1 or JTAG recovery will be required. # Programming over JTAG header From f3c8174b6958bba561098d9359b54e54743b2134 Mon Sep 17 00:00:00 2001 From: Emard Date: Sun, 17 Feb 2019 13:03:41 +0100 Subject: [PATCH 7/7] manual typo --- doc/MANUAL.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/doc/MANUAL.md b/doc/MANUAL.md index f880291..ce26110 100644 --- a/doc/MANUAL.md +++ b/doc/MANUAL.md @@ -239,8 +239,8 @@ bootloader image is at byte address 0 of SPI config FLASH, "golden" bootloader image is at 0x140000 address on 45F chip but its location varies on various sizes of FPGA 12/25/45/85F. At the last 256 bytes of FLASH are some special FPGA lattice boot state machine commands -(detailed meaning and format not yet known, it's like some primitive CPU assemlby) -that setups and controls multiboot function. +(detailed meaning and format not yet known, it's like some primitive CPU +assembly) that setups and controls multiboot function. Try not to overwrite any of boot related areas with something else otherwise US1 or JTAG recovery will be required.