USB directly to FPGA for possible USB1.1 core

README.md

@@ -68,7 +68,7 @@ section (thicker power lines, separately routed feedback)
     [x] Compile a f32c bitstream using the schematics
     [x] Compile differential GPDI output
     [ ] Connect more lines from ESP-32 to FPGA
-    [ ] Connect FPGA USB D+/D- with 1.5k pullup in USB 1.1 (full speed) mode
+    [x] Connect FPGA USB D+/D- with 1.5k pullup in USB 1.1 (full speed) mode
     [ ] Jumpers to switch 2.5V/3.3V for left IO banks
     [x] External JTAG header
     [ ] Move WiFi Disable jumper above the buttons

gpio.bak

@@ -641,9 +641,9 @@ Text GLabel 5700 2800 2    60   Input ~ 0
 BTN_PWRn
 Text Notes 7050 5750 0    60   ~ 0
 J2_5-J2_23 connected to  BANK2,3 on "ram" sheet\nJ2_25-J2_35 connected to BANK1 on "gpdi" sheet
-Text GLabel 4200 2500 0    60   Input ~ 0
-SW0
 Text GLabel 4200 2700 0    60   Input ~ 0
+SW0
+Text GLabel 4200 2500 0    60   Input ~ 0
 SW1
 Text GLabel 5700 2500 2    60   Input ~ 0
 SW2

ram.sch

@@ -397,4 +397,8 @@ Text GLabel 10050 5350 2    60   Input ~ 0
 ADC_CSn
 Text GLabel 10050 5550 2    60   Input ~ 0
 ADC_SCLK
+Text GLabel 8550 3850 0    60   Input ~ 0
+USB_FPGA_D+
+Text GLabel 10050 3850 2    60   Input ~ 0
+USB_FPGA_D-
 $EndSCHEMATC

usb.bak

@@ -534,4 +534,6 @@ Text Label 1850 1800 0    60   ~ 0
 FTD-
 Text Label 1850 1900 0    60   ~ 0
 FTD+
+Text Notes 2150 3150 0    60   ~ 0
+USB_FPGA connected to\nBANK2 on "ram" sheet
 $EndSCHEMATC

usb.sch

@@ -534,4 +534,6 @@ Text Label 1850 1800 0    60   ~ 0
 FTD-
 Text Label 1850 1900 0    60   ~ 0
 FTD+
+Text Notes 2150 3150 0    60   ~ 0
+USB_FPGA connected to\nBANK2 on "ram" sheet
 $EndSCHEMATC