diff --git a/blinkey.bak b/blinkey.bak index 7f32794..c1a496a 100644 --- a/blinkey.bak +++ b/blinkey.bak @@ -498,17 +498,6 @@ F 5 "AC0603FR-07150RL" V 7250 3400 50 0001 C CNN "MFG_PN" 1 7250 3400 0 -1 -1 0 $EndComp -$Comp -L power:+3V3 #PWR090 -U 1 1 595BA1C1 -P 7100 3400 -F 0 "#PWR090" H 7100 3250 50 0001 C CNN -F 1 "+3V3" H 7100 3540 50 0000 C CNN -F 2 "" H 7100 3400 50 0000 C CNN -F 3 "" H 7100 3400 50 0000 C CNN - 1 7100 3400 - 0 -1 -1 0 -$EndComp Wire Wire Line 7400 3400 7750 3400 Wire Wire Line @@ -856,4 +845,6 @@ Wire Wire Line 7750 3200 7750 3300 Wire Wire Line 7750 3300 7750 3400 +Text GLabel 7100 3400 0 60 Input ~ 0 +2V5_3V3 $EndSCHEMATC diff --git a/doc/ulx3s_bom_1.8.4.csv b/doc/ulx3s_bom.csv similarity index 99% rename from doc/ulx3s_bom_1.8.4.csv rename to doc/ulx3s_bom.csv index 513cb15..271dde6 100644 --- a/doc/ulx3s_bom_1.8.4.csv +++ b/doc/ulx3s_bom.csv @@ -69,8 +69,8 @@ Component Count:,196 Fitted Components:,196 Number of PCBs:,1 Total components:,196 -Schematic Version:,1.8.4 +Schematic Version:,1.8.5 Schematic Date:, -BoM Date:,"nedjelja, 20. svibnja 2018. 21:39:32 CEST" +BoM Date:,"utorak, 22. svibnja 2018. 09:18:42 CEST" Schematic Source:,/home/davor/src/circuits/fpga/ulx3s/ulx3s.sch KiCad Version:,Eeschema 5.0.0-rc2-dev-unknown+dfsg1+20180318-2 diff --git a/plot/pcbway/ulx3s_bom.csv b/plot/pcbway/ulx3s_bom.csv new file mode 120000 index 0000000..a5e1800 --- /dev/null +++ b/plot/pcbway/ulx3s_bom.csv @@ -0,0 +1 @@ +../../doc/ulx3s_bom.csv \ No newline at end of file diff --git a/plot/pcbway/ulx3s_bom_1.8.4.csv b/plot/pcbway/ulx3s_bom_1.8.4.csv deleted file mode 120000 index 1f21798..0000000 --- a/plot/pcbway/ulx3s_bom_1.8.4.csv +++ /dev/null @@ -1 +0,0 @@ -../../doc/ulx3s_bom_1.8.4.csv \ No newline at end of file diff --git a/ulx3s.sch b/ulx3s.sch index 3be236a..f1ef9a8 100644 --- a/ulx3s.sch +++ b/ulx3s.sch @@ -7,7 +7,7 @@ encoding utf-8 Sheet 1 11 Title "ULX3S" Date "" -Rev "1.8.4" +Rev "1.8.5" Comp "FER+RIZ+RADIONA" Comment1 "Root sheet" Comment2 ""