diff --git a/flash.bak b/flash.bak
index ec206fb..28efbf5 100644
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-F 3 "" H 9050 2550 50  0000 C CNN
-	1    9050 2550
+P 5400 2200
+F 0 "#PWR0157" H 5400 2050 50  0001 C CNN
+F 1 "+3V3" H 5400 2340 50  0000 C CNN
+F 2 "" H 5400 2200 50  0000 C CNN
+F 3 "" H 5400 2200 50  0000 C CNN
+	1    5400 2200
 	1    0    0    -1  
 $EndComp
 Wire Wire Line
-	4650 2750 5650 2750
-Text Label 4700 2750 0    60   ~ 0
+	5500 4400 6500 4400
+Text Label 5550 4400 0    60   ~ 0
 FPGA_INITN
 $Comp
 L R R33
 U 1 1 58EC72FD
-P 9250 2700
-F 0 "R33" V 9330 2700 50  0000 C CNN
-F 1 "10k" V 9250 2700 50  0000 C CNN
-F 2 "Resistors_SMD:R_0603_HandSoldering" V 9180 2700 50  0001 C CNN
-F 3 "" H 9250 2700 50  0000 C CNN
-	1    9250 2700
+P 5600 2350
+F 0 "R33" V 5680 2350 50  0000 C CNN
+F 1 "10k" V 5600 2350 50  0000 C CNN
+F 2 "Resistors_SMD:R_0603_HandSoldering" V 5530 2350 50  0001 C CNN
+F 3 "" H 5600 2350 50  0000 C CNN
+	1    5600 2350
 	1    0    0    -1  
 $EndComp
 Wire Wire Line
-	9250 2850 9250 3700
-Text Label 9250 3650 1    60   ~ 0
+	5600 2500 5600 3350
+Text Label 5600 3300 1    60   ~ 0
 FPGA_INITN
 $Comp
 L +3V3 #PWR0158
 U 1 1 58EC7305
-P 9250 2550
-F 0 "#PWR0158" H 9250 2400 50  0001 C CNN
-F 1 "+3V3" H 9250 2690 50  0000 C CNN
-F 2 "" H 9250 2550 50  0000 C CNN
-F 3 "" H 9250 2550 50  0000 C CNN
-	1    9250 2550
+P 5600 2200
+F 0 "#PWR0158" H 5600 2050 50  0001 C CNN
+F 1 "+3V3" H 5600 2340 50  0000 C CNN
+F 2 "" H 5600 2200 50  0000 C CNN
+F 3 "" H 5600 2200 50  0000 C CNN
+	1    5600 2200
 	1    0    0    -1  
 $EndComp
 $Comp
 L +3V3 #PWR0159
 U 1 1 58EC879F
-P 5650 2950
-F 0 "#PWR0159" H 5650 2800 50  0001 C CNN
-F 1 "+3V3" H 5650 3090 50  0000 C CNN
-F 2 "" H 5650 2950 50  0000 C CNN
-F 3 "" H 5650 2950 50  0000 C CNN
-	1    5650 2950
+P 6500 4600
+F 0 "#PWR0159" H 6500 4450 50  0001 C CNN
+F 1 "+3V3" H 6500 4740 50  0000 C CNN
+F 2 "" H 6500 4600 50  0000 C CNN
+F 3 "" H 6500 4600 50  0000 C CNN
+	1    6500 4600
 	0    -1   -1   0   
 $EndComp
 $Comp
 L +3V3 #PWR0160
 U 1 1 58EC8800
-P 5650 2550
-F 0 "#PWR0160" H 5650 2400 50  0001 C CNN
-F 1 "+3V3" H 5650 2690 50  0000 C CNN
-F 2 "" H 5650 2550 50  0000 C CNN
-F 3 "" H 5650 2550 50  0000 C CNN
-	1    5650 2550
+P 6500 4200
+F 0 "#PWR0160" H 6500 4050 50  0001 C CNN
+F 1 "+3V3" H 6500 4340 50  0000 C CNN
+F 2 "" H 6500 4200 50  0000 C CNN
+F 3 "" H 6500 4200 50  0000 C CNN
+	1    6500 4200
 	0    -1   -1   0   
 $EndComp
 $Comp
 L +3V3 #PWR0161
 U 1 1 58EC882A
-P 7150 2550
-F 0 "#PWR0161" H 7150 2400 50  0001 C CNN
-F 1 "+3V3" H 7150 2690 50  0000 C CNN
-F 2 "" H 7150 2550 50  0000 C CNN
-F 3 "" H 7150 2550 50  0000 C CNN
-	1    7150 2550
+P 8000 4200
+F 0 "#PWR0161" H 8000 4050 50  0001 C CNN
+F 1 "+3V3" H 8000 4340 50  0000 C CNN
+F 2 "" H 8000 4200 50  0000 C CNN
+F 3 "" H 8000 4200 50  0000 C CNN
+	1    8000 4200
 	0    1    1    0   
 $EndComp
-Text GLabel 5650 2150 0    60   Input ~ 0
+Text GLabel 6500 3800 0    60   Input ~ 0
 BTN_F1
-Text GLabel 7150 2150 2    60   Input ~ 0
+Text GLabel 8000 3800 2    60   Input ~ 0
 BTN_F2
-Text GLabel 7150 2250 2    60   Input ~ 0
+Text GLabel 8000 3900 2    60   Input ~ 0
 BTN_D
-Text GLabel 5650 2250 0    60   Input ~ 0
+Text GLabel 6500 3900 0    60   Input ~ 0
 BTN_L
-Text Notes 8350 2300 0    60   ~ 0
+Text Notes 4700 1950 0    60   ~ 0
 pullups to allow entering USER mode\nTN1260: lattice ECP5 sysCONFIG guide p.6, p.8, p.13
 $Comp
 L R R55
 U 1 1 59DEB568
-P 4500 3150
-F 0 "R55" V 4580 3150 50  0000 C CNN
-F 1 "15k" V 4500 3150 50  0000 C CNN
-F 2 "Resistors_SMD:R_0603_HandSoldering" V 4430 3150 50  0001 C CNN
-F 3 "" H 4500 3150 50  0000 C CNN
-	1    4500 3150
+P 5350 4800
+F 0 "R55" V 5430 4800 50  0000 C CNN
+F 1 "15k" V 5350 4800 50  0000 C CNN
+F 2 "Resistors_SMD:R_0603_HandSoldering" V 5280 4800 50  0001 C CNN
+F 3 "" H 5350 4800 50  0000 C CNN
+	1    5350 4800
 	0    1    1    0   
 $EndComp
-Text GLabel 4350 3150 0    60   Input ~ 0
+Text GLabel 5200 4800 0    60   Input ~ 0
 PROG_DONE
 $Comp
 L LFE5U-45F-6BG381C U1
 U 7 1 5A07BEF6
-P 6400 2850
+P 7250 4500
 AR Path="/5A07BEF6" Ref="U1"  Part="7" 
 AR Path="/58D913EC/5A07BEF6" Ref="U1"  Part="7" 
-F 0 "U1" H 6400 3800 60  0000 C CNN
-F 1 "LFE5U-45F-6BG381C" H 6400 3700 60  0000 C CNN
-F 2 "lfe5bg381:BGA-381_pitch0.8mm_dia0.4mm" H 5350 3800 60  0001 C CNN
-F 3 "http://www.latticesemi.com/~/media/LatticeSemi/Documents/ApplicationNotes/EH/TN1260.pdf" H 5350 3800 60  0001 C CNN
-F 4 "LFE5U-45F-6BG381C" H 6400 2850 60  0001 C CNN "MFG_PN"
-F 5 "www.mouser.com" H 6400 2850 60  0001 C CNN "Distributor1_URL"
-F 6 "842-LFE5U45F6BG381C" H 6400 2850 60  0001 C CNN "Distributor1_PN"
-	7    6400 2850
+F 0 "U1" H 7250 5450 60  0000 C CNN
+F 1 "LFE5U-45F-6BG381C" H 7250 5350 60  0000 C CNN
+F 2 "lfe5bg381:BGA-381_pitch0.8mm_dia0.4mm" H 6200 5450 60  0001 C CNN
+F 3 "http://www.latticesemi.com/~/media/LatticeSemi/Documents/ApplicationNotes/EH/TN1260.pdf" H 6200 5450 60  0001 C CNN
+F 4 "LFE5U-45F-6BG381C" H 7250 4500 60  0001 C CNN "MFG_PN"
+F 5 "www.mouser.com" H 7250 4500 60  0001 C CNN "Distributor1_URL"
+F 6 "842-LFE5U45F6BG381C" H 7250 4500 60  0001 C CNN "Distributor1_PN"
+	7    7250 4500
 	1    0    0    -1  
 $EndComp
-Text Notes 1500 3500 0    60   ~ 0
+Text Notes 2350 5150 0    60   ~ 0
 For programming Flash thru JTAG see\nLattice FPGA-TN-02050
-Text Notes 8600 2400 0    60   ~ 0
-WPn
 Wire Wire Line
-	7150 2350 8150 2350
+	8000 4000 9000 4000
 Wire Wire Line
-	5650 2350 4650 2350
-Text Label 4700 2350 0    60   ~ 0
+	6500 4000 5500 4000
+Text Label 5550 4000 0    60   ~ 0
 FLASH_nHOLD
-Text Label 7550 2350 0    60   ~ 0
+Text Label 8400 4000 0    60   ~ 0
 FLASH_nWP
+Text Notes 4950 4000 0    60   ~ 0
+BTN_U v1.7
+Text Notes 9050 4000 0    60   ~ 0
+BTN_R v1.7
 $EndSCHEMATC
diff --git a/gpdi.bak b/gpdi.bak
index f01d84c..a193cb8 100644
--- a/gpdi.bak
+++ b/gpdi.bak
@@ -494,12 +494,16 @@ Text Label 4450 2200 0    60   ~ 0
 FPGA_CEC
 Text Notes 800  5650 0    60   ~ 0
 i2c shared with RTC\non "power" sheet
-Text Notes 4450 2750 0    60   ~ 0
+Text Notes 4250 2750 0    60   ~ 0
 GP22 v1.7
-Text Notes 7700 2750 0    60   ~ 0
+Text Notes 7750 2750 0    60   ~ 0
 GN22 v1.7
-Text Notes 4450 2850 0    60   ~ 0
+Text Notes 4250 2850 0    60   ~ 0
 GP25 v1.7
-Text Notes 7700 2850 0    60   ~ 0
+Text Notes 7750 2850 0    60   ~ 0
 GN25 v1.7
+Text GLabel 5500 2700 0    60   Input ~ 0
+USB_FPGA_D+
+Text GLabel 7000 2700 2    60   Input ~ 0
+USB_FPGA_D-
 $EndSCHEMATC
diff --git a/ulx3s.sch b/ulx3s.sch
index 9efd198..668a254 100644
--- a/ulx3s.sch
+++ b/ulx3s.sch
@@ -49,7 +49,7 @@ encoding utf-8
 Sheet 1 11
 Title "ULX3S"
 Date ""
-Rev "1.7.9"
+Rev "1.7.10"
 Comp "FER+RIZ+RADIONA"
 Comment1 "Root sheet"
 Comment2 ""
diff --git a/usb.bak b/usb.bak
index 33ada93..051c1da 100644
--- a/usb.bak
+++ b/usb.bak
@@ -498,8 +498,8 @@ Text Label 1850 1800 0    60   ~ 0
 FTD-
 Text Label 1850 1900 0    60   ~ 0
 FTD+
-Text Notes 2850 3100 0    60   ~ 0
-USB_FPGA connected to\nBANK2 on "ram" sheet
+Text Notes 2850 3250 0    60   ~ 0
+USB_FPGA connected to\nBANK1 on "gpdi" sheet and\nBANK2 on "ram" sheet
 $Comp
 L R R52
 U 1 1 59C0F7B0
diff --git a/usb.sch b/usb.sch
index 33ada93..051c1da 100644
--- a/usb.sch
+++ b/usb.sch
@@ -498,8 +498,8 @@ Text Label 1850 1800 0    60   ~ 0
 FTD-
 Text Label 1850 1900 0    60   ~ 0
 FTD+
-Text Notes 2850 3100 0    60   ~ 0
-USB_FPGA connected to\nBANK2 on "ram" sheet
+Text Notes 2850 3250 0    60   ~ 0
+USB_FPGA connected to\nBANK1 on "gpdi" sheet and\nBANK2 on "ram" sheet
 $Comp
 L R R52
 U 1 1 59C0F7B0