b92a15489b
footprints: BGA rename fiducial pads 0->X (as 0 is usually gnd)
6 years ago
18379d51a8
footprints: BGA with fiducial pads for chip alignment
6 years ago
10ad82899b
footprints: fixing for Fab layer
6 years ago
0bc3844449
footprints: fixing fab layer for assembly layout printed on paper sheet
6 years ago
87c896a0bb
footprints: BGA pads 0.4mm copper, 0.5mm soldermask, 0.35mm paste=stencil
6 years ago
186c9793f8
BGA footprint with design rules according to Lattice Recommendations
6 years ago
6b50f65544
footprints: FPGA renaming Quad SPI lines D2,D3
...
schematics: reference FPGA footprint directly (not from rescue file)
7 years ago
702be2aa9e
FPGA chip bank 0: swap sides A9<->B10 (true-complement was wrong)
7 years ago
35b3a8b3dd
changing to 45F which is production device now
...
schem symbol 45F fixed typo T8->T7 (GND) and SERDES
7 years ago
220f575442
schematic "power" sheet and footprint cosmetics
7 years ago
1ea88bda53
Adding pins to schematic symbols for all chips in unit "H" (SERDES)
...
Non-serdes chips need GND connection on unit "H".
"power" sheet now connects GND's at unit "H".
7 years ago
8f452e4d43
filling up serdes block 50,51 for UM85F, halway done.
...
VCC are also planned to be moved to that block
7 years ago
fffde2cf88
Additional GND for 85F chips
7 years ago
6c23919a2d
Schematic symbol for 12F. Currently just a copy of 25F
...
and checked bank0 pinout, and randomly power bank seems to fit
at first glance.
7 years ago
e4fc99887e
moving GND and VCC on schematics symbols to
...
common locations for planned PCB which
supports upgrade path for example
12F->25F->45F->85F and if possible ECP5U->ECP5UM
7 years ago
cb69b2cc9a
ECP5 85E schematic footprint
7 years ago
3aac13deb4
footprint for ECP5:
...
fix 25E device, small pin naming swapping BANK0 one pin A/B
new 45E device, modified pin names to fit (needs more review)
new 85E device but pin names are wrong (need more work)
7 years ago
732323094c
BGA footprint: silkscreen ticks for verification
...
of relative alignment between BGA silkscreen and the pads
7 years ago
6b9a07a7ab
BGA footprint with double squares for manual alignment
7 years ago
a4b74230d3
fixing errors in schem symbol BANK6
8 years ago
af58a36fbd
delete old FPGA schem. symbol component from the library
8 years ago
e5f97e1897
schematic symbol FPGA: mark bank physical location
...
on the floorplan
8 years ago
4a26254f9a
correcting schematic symbol of FPGA
8 years ago
01d1cad2ec
add missing pins in schematic symbol for BANK3
8 years ago
d0791b1e47
correcting few pin numbering errors in FPGA schematic symbols
8 years ago
40aef19979
FPGA schematic symbol add mssing PR41A, PR41B to BANK3
8 years ago
9570c1137b
small edits
8 years ago
a477fbd050
connecting flash config chip
8 years ago
2de9717740
fpga bga schematic symbol set exact chip name
8 years ago
5d5a4031cc
pins VREF named on schematic symbol of fpga
8 years ago
067962ec48
fpga schematic symbol: renumbering bank units
8 years ago
4d31d658fb
Added pins for remaining banks.
...
Need to verify if everything is correct.
8 years ago
b62dc97d89
adding BANK2 pins to FPGA shematic symbol
8 years ago
09c209e137
BGA reducing solder mask clearance
8 years ago
d64741e825
BGA pads smaller 0.4->0.35 mm
8 years ago
aa1e65bd71
small edits
8 years ago
f6326e22d9
changing BANK0 (Unit A) shematic symbol and
...
adding BANK1 (Unit B)
8 years ago
25672b71ff
updating pins for BANK1 (still incomplete)
8 years ago
3f8b5009a9
Uploading initial kicad project for ULX3S
9 years ago
Emard