302cb6d867
small update for gerber readme
8 years ago
b17b4a481b
helper files for submission to seeedstudio production
8 years ago
962282a4ac
updated gerber drill file
8 years ago
9ddf4f58e5
delete old drill files
8 years ago
92f4d68d07
gerber update
8 years ago
c381c4c5c4
small PCB optimizations
8 years ago
a6cf1f07ac
deleting old gerbers
8 years ago
1f60f95a71
compatible OLED models: SSD1306 or SSD1331
8 years ago
ea97d2573c
schematics.pdf
8 years ago
bb82a9ac86
gerbers update
8 years ago
28c4106026
J2 GPIO: routed in the purple plane only
8 years ago
aabd353e71
J1 GPIO: grouping lines on purple plane
8 years ago
752eddee0e
J1 routed using only purple plane, (yellow plane made free)
8 years ago
1e5e0b01a6
connecting JTAG lines to FTDI serial lines RI DCD CTS DSR
...
as those pins are by default inputs and can be reconfigured as outputs
similar but not identical pinout as the one that works from ujprog
CBUS used to force-wakeup of the board from sleep state
2 LEDs to CBUS pins to display usb enumeration and activity status
8 years ago
57fa143c11
connecting 2.5V and 3.3V sources to BGA planes
8 years ago
4a0cc08307
connecting 1.2V core voltage, solving FPGA voltage plane,
...
still too thin wire leading to SMPS supply
8 years ago
ad274f07a2
recommendations for BGA381 4-layer PCB layout
8 years ago
5e953da6b9
connecting required pins for WiFi programming
8 years ago
5432fd6540
connecting clock and ftdi USB
8 years ago
4c13f262e8
connecting FTDI TXD/RXD
8 years ago
092e601af1
connecting LEDs
8 years ago
364957f9e0
connecting OLED
8 years ago
feb31c8f87
moving inner layer routes away from BGA
8 years ago
24c52062fa
moving routes under BGA out of inner layers
8 years ago
6e2e5f8c39
moving routing out of inner layers under BGA to allow
...
larger copper fill zone for power supply
8 years ago
3a9160cb16
scrapping current routing, placing power supply on copper zones under the BGA
8 years ago
21aa552e1a
placing copper fill zones for power supply by the book
...
similar to TN1074
8 years ago
37f7a62a25
reducing minimal drill size to 0.2 mm as
...
recommended in lattice BGA guide.
Seeedstudio meets this capabilities
OSHpark doesn't
8 years ago
1392c5aa2b
how to route BGA
8 years ago
8061b47da8
moving some resistor near flash chip
8 years ago
b12f1b64a6
routing spi flash lines
8 years ago
820f30f598
routing JTAG
8 years ago
3a079bd1d2
moving some resistor closer to ftdi
8 years ago
48f79d581b
reordering PCB elements to simplify or shorten routes
8 years ago
6e48d42150
fully routed GPIO
8 years ago
dcc2d375ea
routing additional pins to J2 GPIO. 2 differential pairs left to route
8 years ago
9f0d9c46a7
routing half of J2 gpio
8 years ago
e30bbeea40
routing 4 GPIO on J2
8 years ago
48dc148919
manually routing J1 differential
8 years ago
9050eefd6e
update fill zone
8 years ago
55ecd6c1c2
update 3D view top
8 years ago
56e8ad2710
update 3D view pictures
8 years ago
3446afcc08
optimizing PCB component placement
...
and audio bit ordering
8 years ago
19b884baef
using corrected schem symbol, reordering pins
8 years ago
a4b74230d3
fixing errors in schem symbol BANK6
8 years ago
af58a36fbd
delete old FPGA schem. symbol component from the library
8 years ago
39dce76f0a
use new schem symbol
8 years ago
e5f97e1897
schematic symbol FPGA: mark bank physical location
...
on the floorplan
8 years ago
2cda80c3a8
manually routed few tracks of GPIO
8 years ago
8a53acb71a
cleaning GPDI routes and moving OLED back in place
8 years ago
davor