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PCB for ULX3S FPGA R&D board. Fork Sand fork of https://github.com/emard/ulx3s https://www.forksand.com/
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connecting some GNDs and GNDing unnamed shield pads on USB connectors 		8 years ago
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footprints connecting some GNDs and GNDing unnamed shield pads on USB connectors 8 years ago
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plot updating gerbers 8 years ago
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README.md readme update 8 years ago
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blinkey.sch compatible OLED models: SSD1306 or SSD1331 8 years ago
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gpdi.bak compatible OLED models: SSD1306 or SSD1331 8 years ago
gpdi.sch J2 GPIO: routed in the purple plane only 8 years ago
gpio.bak J2 GPIO: routed in the purple plane only 8 years ago
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ram.sch connecting JTAG lines to FTDI serial lines RI DCD CTS DSR 8 years ago
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ulx3s.sch use new schem symbol 8 years ago
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README.md

ULX3S PCB

This is work-in-progress place for putting some wishes of a small (94x51 mm) FPGA board.

Instead of describing in written, it is better explained when drawn in kicad:

kicad ulx3s.pro

Schematics is mostly complete. PCB routing is not complete (about 50 routes missing).

3D preview

TOP BOTTOM

Features

FPGA: Lattice ECP5 LFE5U-25F-6BG381C

USB: FTDI FT231XS (1Mbit JTAG and 3Mbit usbserial)

GPIO: All differential, PMOD-friendly

RAM: 32MB SDRAM MT48LC16M16

Flash: 8MB SPI flash S25FL164 for FPGA config

Storage: Micro-SD slot

LEDs: 10 (8 blink-LEDs, 2 USB leds)

Buttons: 6 (4 direction and 2 fire buttons)

Audio: 3.5 mm stereo jack

Video: GPDI connector with 3.3V-5V I2C bidirectional level shifter

Display: placeholder for 0.96-1.3" SPI OLED COLOR or B/W

WiFi+bluetooth: placeholder for ESP-32 (JTAG and serial over WiFi possible)

Power: 3 Switching voltage regulators: 1.2V, 2.5V, 3.3V

Low power sleep: RTC clock wakeup, quartz and battery

GPDI is General Purpose Differential Interface, Electrically LVDS, mostly TMDS tolerant female receptacle more-or-less compatible with digital monitors/TVs

Todo

Finish routing and especially improve Power section (thicker power lines, separately routed feedback)

2.54 mm external JTAG header