update pcb from schematic

master
forksand 2 years ago
parent 6303200321
commit 9c188c64c9

@ -82,5 +82,1112 @@
)
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(net 3 "Net-(C1-Pad1)")
(net 4 "Net-(C2-Pad1)")
(net 5 "+9V")
(net 6 "Net-(C4-Pad1)")
(net 7 "Net-(C5-Pad1)")
(net 8 "Net-(D1-Pad2)")
(net 9 "Net-(D2-Pad2)")
(net 10 "Net-(Q1-Pad3)")
(net 11 "Net-(Q2-Pad1)")
(net 12 "Net-(R5-Pad1)")
(net 13 "Net-(R6-Pad2)")
(net 14 "Net-(R7-Pad1)")
(net 15 "GNDREF")
(net 16 "unconnected-(SW1-Pad4)")
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@ -2,26 +2,120 @@
"board": {
"design_settings": {
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"copper_text_upright": false,
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"dimension_precision": 4,
"dimension_units": 3,
"dimensions": {
"arrow_length": 1270000,
"extension_offset": 500000,
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"suppress_zeroes": false,
"text_position": 0,
"units_format": 1
},
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},
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"min_clearance": 0.508
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},
"diff_pair_dimensions": [],
"drc_exclusions": [],
"meta": {
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},
"rule_severities": {
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"clearance": "error",
"copper_edge_clearance": "error",
"courtyards_overlap": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint_type_mismatch": "error",
"hole_clearance": "error",
"hole_near_hole": "error",
"invalid_outline": "error",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
"missing_footprint": "warning",
"net_conflict": "warning",
"npth_inside_courtyard": "ignore",
"padstack": "error",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_over_copper": "warning",
"silk_overlap": "warning",
"skew_out_of_range": "error",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
"track_dangling": "warning",
"track_width": "error",
"tracks_crossing": "error",
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zone_has_empty_net": "error",
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"allow_microvias": false,
"max_error": 0.005,
"min_clearance": 0.0,
"min_copper_edge_clearance": 0.0,
"min_hole_clearance": 0.25,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.19999999999999998,
"min_microvia_drill": 0.09999999999999999,
"min_silk_clearance": 0.0,
"min_through_hole_diameter": 0.3,
"min_track_width": 0.19999999999999998,
"min_via_annular_width": 0.049999999999999996,
"min_via_diameter": 0.39999999999999997,
"solder_mask_clearance": 0.0,
"solder_mask_min_width": 0.0
"solder_mask_min_width": 0.0,
"use_height_for_length_calcs": true
},
"track_widths": [],
"via_dimensions": []
"via_dimensions": [],
"zones_allow_external_fillets": false,
"zones_use_no_outline": true
},
"layer_presets": []
},
@ -271,7 +365,7 @@
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "",
"netlist": "./",
"specctra_dsn": "",
"step": "",
"vrml": ""
@ -299,7 +393,7 @@
"meta": {
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},
"net_format_name": "",
"net_format_name": "KiCad",
"ngspice": {
"fix_include_paths": true,
"fix_passive_vals": false,

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