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34 KiB

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(outline (path signal 50 4500 -3250 4500 3250))
(outline (path signal 50 4500 3250 -1950 3250))
(pin Rect[A]Pad_1800x1800_um 1 0 0)
(pin Round[A]Pad_1800_um 2 2540 0)
)
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(pin Oval[A]Pad_1700x1400_um 2 5080 0)
(pin RoundRect[A]Pad_1700x1400_250.148_um_0.000000_0 1 0 0)
)
(image Capacitor_THT:CP_Axial_L10.0mm_D4.5mm_P15.00mm_Horizontal
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(pin Rect[A]Pad_2000x2000_um 1 0 0)
(pin Oval[A]Pad_2000x2000_um 2 15000 0)
)
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(pin Rect[A]Pad_2000x2000_um 1 0 0)
(pin Round[A]Pad_2000_um 2 7600 0)
)
(padstack Round[A]Pad_1440_um
(shape (circle F.Cu 1440))
(shape (circle B.Cu 1440))
(attach off)
)
(padstack Round[A]Pad_1600_um
(shape (circle F.Cu 1600))
(shape (circle B.Cu 1600))
(attach off)
)
(padstack Round[A]Pad_1800_um
(shape (circle F.Cu 1800))
(shape (circle B.Cu 1800))
(attach off)
)
(padstack Round[A]Pad_2000_um
(shape (circle F.Cu 2000))
(shape (circle B.Cu 2000))
(attach off)
)
(padstack Oval[A]Pad_1050x1500_um
(shape (path F.Cu 1050 0 -225 0 225))
(shape (path B.Cu 1050 0 -225 0 225))
(attach off)
)
(padstack Oval[A]Pad_1700x1400_um
(shape (path F.Cu 1400 -150 0 150 0))
(shape (path B.Cu 1400 -150 0 150 0))
(attach off)
)
(padstack Oval[A]Pad_1600x1600_um
(shape (path F.Cu 1600 0 0 0 0))
(shape (path B.Cu 1600 0 0 0 0))
(attach off)
)
(padstack Oval[A]Pad_2000x2000_um
(shape (path F.Cu 2000 0 0 0 0))
(shape (path B.Cu 2000 0 0 0 0))
(attach off)
)
(padstack RoundRect[A]Pad_1700x1400_250.148_um_0.000000_0
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(attach off)
)
(padstack Rect[A]Pad_2000x2000_um
(shape (rect F.Cu -1000 -1000 1000 1000))
(shape (rect B.Cu -1000 -1000 1000 1000))
(attach off)
)
(padstack Rect[A]Pad_1050x1500_um
(shape (rect F.Cu -525 -750 525 750))
(shape (rect B.Cu -525 -750 525 750))
(attach off)
)
(padstack Rect[A]Pad_1600x1600_um
(shape (rect F.Cu -800 -800 800 800))
(shape (rect B.Cu -800 -800 800 800))
(attach off)
)
(padstack Rect[A]Pad_1800x1800_um
(shape (rect F.Cu -900 -900 900 900))
(shape (rect B.Cu -900 -900 900 900))
(attach off)
)
(padstack "Via[0-1]_800:400_um"
(shape (circle F.Cu 800))
(shape (circle B.Cu 800))
(attach off)
)
)
(network
(net "Net-(BZ1-Pad1)"
(pins U1-7 R8-2 C5-2 BZ1-1)
)
(net GND
(pins RV1-3 R1-2 Q1-1 D2-1 C4-2 C3-2 C2-2 C1-2 BZ1-2)
)
(net "Net-(C1-Pad1)"
(pins R2-1 D1-1 C1-1)
)
(net "Net-(C2-Pad1)"
(pins R4-2 Q2-2 C2-1)
)
(net +9V
(pins U1-8 RV1-1 R4-1 Q2-3 C3-1)
)
(net "Net-(C4-Pad1)"
(pins R5-2 C4-1)
)
(net "Net-(C5-Pad1)"
(pins U1-5 R7-2 C5-1)
)
(net "Net-(D1-Pad2)"
(pins R1-1 Q1-2 D1-2)
)
(net "Net-(D2-Pad2)"
(pins R8-1 D2-2)
)
(net "Net-(Q1-Pad3)"
(pins U1-3 R3-2 Q1-3)
)
(net "Net-(Q2-Pad1)"
(pins R3-1 R2-2 Q2-1)
)
(net "Net-(R5-Pad1)"
(pins U1-2 R6-1 R5-1)
)
(net "Net-(R6-Pad2)"
(pins U1-1 U1-6 R6-2)
)
(net "Net-(R7-Pad1)"
(pins RV1-2 R7-1)
)
(net GNDREF
(pins U1-4)
)
(class kicad_default
(circuit
(use_via Via[0-1]_800:400_um)
)
(rule
(width 250)
(clearance 200.1)
)
)
)
(wiring
)
)