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570 lines
26 KiB
570 lines
26 KiB
EESchema-LIBRARY Version 2.4
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#encoding utf-8
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#
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# FE310-G000
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#
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DEF FE310-G000 U 0 40 Y Y 1 F N
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F0 "U" -1050 1250 50 H V L CNN
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F1 "FE310-G000" -1050 1350 50 H V L CNN
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F2 "Package_DFN_QFN:QFN-48-1EP_6x6mm_P0.4mm_EP4.66x4.66mm_ThermalVias" -1050 1450 50 H I L CNN
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F3 "" -1050 1250 50 H I C CNN
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$FPLIST
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QFN*
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$ENDFPLIST
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DRAW
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S -1050 1150 1050 -1150 0 1 10 f
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X QSPI_DQ_3 1 -1200 -100 150 R 50 50 1 1 B
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X XTAL_XO 10 -1200 900 150 R 50 50 1 1 O
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X IVDD 11 -400 1300 150 D 50 50 1 1 W
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X OTP_AIVDD 12 -100 1300 150 D 50 50 1 1 W
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X JTAG_TCK 13 -1200 700 150 R 50 50 1 1 I
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X JTAG_TDO 14 -1200 600 150 R 50 50 1 1 O
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X JTAG_TMS 15 -1200 500 150 R 50 50 1 1 I
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X JTAG_TDI 16 -1200 400 150 R 50 50 1 1 I
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X AON_PMU_OUT_1 17 -1200 -600 150 R 50 50 1 1 O
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X ~AON_PMU_DWAKEUP_N 18 -1200 -700 150 R 50 50 1 1 I
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X AON_IVDD 19 500 1300 150 D 50 50 1 1 W
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X QSPI_DQ_2 2 -1200 0 150 R 50 50 1 1 B
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X AON_PSD_LFALTCLK 20 -1200 -900 150 R 50 50 1 1 I
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X AON_PSD_LFCLKSEL 21 -1200 -1000 150 R 50 50 1 1 I
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X AON_PMU_OUT_0 22 -1200 -500 150 R 50 50 1 1 O
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X AON_VDD 23 400 1300 150 D 50 50 1 1 W
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X ~AON_ERST_N 24 -1200 -800 150 R 50 50 1 1 I
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X GPIO_0 25 1200 900 150 L 50 50 1 1 B
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X GPIO_1 26 1200 800 150 L 50 50 1 1 B
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X GPIO_2 27 1200 700 150 L 50 50 1 1 B
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X GPIO_3 28 1200 600 150 L 50 50 1 1 B
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X GPIO_4 29 1200 500 150 L 50 50 1 1 B
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X QSPI_DQ_1 3 -1200 100 150 R 50 50 1 1 B
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X VDD 30 200 1300 150 D 50 50 1 1 W
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X GPIO_5 31 1200 400 150 L 50 50 1 1 B
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X IVDD 32 -300 1300 150 D 50 50 1 1 W
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X GPIO_9 33 1200 300 150 L 50 50 1 1 B
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X GPIO_10 34 1200 200 150 L 50 50 1 1 B
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X GPIO_11 35 1200 100 150 L 50 50 1 1 B
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X GPIO_12 36 1200 0 150 L 50 50 1 1 B
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X GPIO_13 37 1200 -100 150 L 50 50 1 1 B
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X GPIO_16 38 1200 -200 150 L 50 50 1 1 B
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X GPIO_17 39 1200 -300 150 L 50 50 1 1 B
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X QSPI_DQ_0 4 -1200 200 150 R 50 50 1 1 B
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X GPIO_18 40 1200 -400 150 L 50 50 1 1 B
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X GPIO_19 41 1200 -500 150 L 50 50 1 1 B
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X GPIO_20 42 1200 -600 150 L 50 50 1 1 B
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X GPIO_21 43 1200 -700 150 L 50 50 1 1 B
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X GPIO_22 44 1200 -800 150 L 50 50 1 1 B
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X GPIO_23 45 1200 -900 150 L 50 50 1 1 B
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X VDD 46 300 1300 150 D 50 50 1 1 W
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X IVDD 47 -200 1300 150 D 50 50 1 1 W
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X QSPI_SCK 48 -1200 -300 150 R 50 50 1 1 O
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X GND 49 100 -1300 150 U 50 50 1 1 W
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X ~QSPI_CS 5 -1200 -200 150 R 50 50 1 1 O
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X VDD 6 100 1300 150 D 50 50 1 1 W
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X PLL_AVDD 7 600 1300 150 D 50 50 1 1 W
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X PLL_AVSS 8 300 -1300 150 U 50 50 1 1 W
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X XTAL_XI 9 -1200 1000 150 R 50 50 1 1 I
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ENDDRAW
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ENDDEF
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#
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# FU540-C000
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#
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DEF FU540-C000 U 0 40 Y Y 6 L N
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F0 "U" -50 0 60 H V L BNN
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F1 "FU540-C000" 50 -50 50 H V C CNN
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F2 "" 0 1950 60 H V C CNN
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F3 "https://static.dev.sifive.com/FU540-C000-v1.0.pdf" 0 1950 60 H I C CNN
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DRAW
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S -1500 -1800 1500 1800 1 1 10 f
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S -1350 -4850 1350 4850 2 1 10 f
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S -1350 -1300 1350 1300 3 1 10 f
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S -950 -1800 950 1800 4 1 10 f
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S -1300 -1700 1300 1700 5 1 10 f
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S -600 -3500 600 3500 6 1 10 f
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X IO_CHIPLINK_0_B2C_DATA_2 AA18 -1800 1400 300 R 50 50 1 1 I
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X IO_CHIPLINK_0_B2C_DATA_8 AA19 -1800 800 300 R 50 50 1 1 I
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X IO_CHIPLINK_0_B2C_DATA_23 AA20 -1800 -700 300 R 50 50 1 1 I
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X IO_CHIPLINK_0_B2C_DATA_29 AA21 -1800 -1300 300 R 50 50 1 1 I
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X IO_CHIPLINK_0_B2C_CLK AA22 -1800 1700 300 R 50 50 1 1 I
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X IO_CHIPLINK_0_B2C_DATA_1 AB18 -1800 1500 300 R 50 50 1 1 I
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X IO_CHIPLINK_0_B2C_DATA_13 AB19 -1800 300 300 R 50 50 1 1 I
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X IO_CHIPLINK_0_B2C_DATA_22 AB20 -1800 -600 300 R 50 50 1 1 I
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X IO_CHIPLINK_0_B2C_DATA_26 AB21 -1800 -1000 300 R 50 50 1 1 I
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X IO_CHIPLINK_0_C2B_DATA_28 K19 1800 -1200 300 L 50 50 1 1 O
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X IO_CHIPLINK_0_C2B_DATA_24 K20 1800 -800 300 L 50 50 1 1 O
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X IO_CHIPLINK_0_C2B_DATA_26 K22 1800 -1000 300 L 50 50 1 1 O
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X IO_CHIPLINK_0_C2B_DATA_31 L17 1800 -1500 300 L 50 50 1 1 O
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X IO_CHIPLINK_0_C2B_DATA_30 L18 1800 -1400 300 L 50 50 1 1 O
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X IO_CHIPLINK_0_C2B_DATA_27 L19 1800 -1100 300 L 50 50 1 1 O
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X IO_CHIPLINK_0_C2B_DATA_20 L20 1800 -400 300 L 50 50 1 1 O
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X IO_CHIPLINK_0_C2B_DATA_18 L21 1800 -200 300 L 50 50 1 1 O
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X IO_CHIPLINK_0_C2B_DATA_29 L22 1800 -1300 300 L 50 50 1 1 O
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X IO_CHIPLINK_0_C2B_DATA_15 M17 1800 100 300 L 50 50 1 1 O
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X IO_CHIPLINK_0_C2B_DATA_19 M18 1800 -300 300 L 50 50 1 1 O
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X IO_CHIPLINK_0_C2B_DATA_23 M19 1800 -700 300 L 50 50 1 1 O
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X IO_CHIPLINK_0_C2B_DATA_12 M20 1800 400 300 L 50 50 1 1 O
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X IO_CHIPLINK_0_C2B_DATA_25 M21 1800 -900 300 L 50 50 1 1 O
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X IO_CHIPLINK_0_C2B_DATA_22 M22 1800 -600 300 L 50 50 1 1 O
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X IO_CHIPLINK_0_C2B_SEND N17 1800 -1700 300 L 50 50 1 1 O
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X IO_CHIPLINK_0_C2B_DATA_2 N18 1800 1400 300 L 50 50 1 1 O
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X IO_CHIPLINK_0_C2B_DATA_6 N19 1800 1000 300 L 50 50 1 1 O
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X IO_CHIPLINK_0_C2B_DATA_21 N20 1800 -500 300 L 50 50 1 1 O
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X IO_CHIPLINK_0_C2B_DATA_16 N21 1800 0 300 L 50 50 1 1 O
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X IO_CHIPLINK_0_C2B_DATA_14 N22 1800 200 300 L 50 50 1 1 O
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X IO_CHIPLINK_0_B2C_RST P17 -1800 -1600 300 R 50 50 1 1 I
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X IO_CHIPLINK_0_B2C_DATA_21 P18 -1800 -500 300 R 50 50 1 1 I
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X IO_CHIPLINK_0_C2B_CLK P19 1800 1700 300 L 50 50 1 1 O
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X IO_CHIPLINK_0_C2B_DATA_4 P20 1800 1200 300 L 50 50 1 1 O
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X IO_CHIPLINK_0_B2C_DATA_24 R17 -1800 -800 300 R 50 50 1 1 I
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X IO_CHIPLINK_0_B2C_DATA_17 R18 -1800 -100 300 R 50 50 1 1 I
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X IO_CHIPLINK_0_C2B_DATA_1 R19 1800 1500 300 L 50 50 1 1 O
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X IO_CHIPLINK_0_C2B_DATA_3 R20 1800 1300 300 L 50 50 1 1 O
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X IO_CHIPLINK_0_C2B_DATA_8 R21 1800 800 300 L 50 50 1 1 O
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X IO_CHIPLINK_0_C2B_DATA_17 R22 1800 -100 300 L 50 50 1 1 O
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X IO_CHIPLINK_0_B2C_DATA_19 T18 -1800 -300 300 R 50 50 1 1 I
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X IO_CHIPLINK_0_C2B_DATA_0 T19 1800 1600 300 L 50 50 1 1 O
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X IO_CHIPLINK_0_C2B_RST T20 1800 -1600 300 L 50 50 1 1 O
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X IO_CHIPLINK_0_C2B_DATA_13 T21 1800 300 300 L 50 50 1 1 O
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X IO_CHIPLINK_0_C2B_DATA_10 T22 1800 600 300 L 50 50 1 1 O
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X IO_CHIPLINK_0_B2C_DATA_20 U17 -1800 -400 300 R 50 50 1 1 I
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X IO_CHIPLINK_0_B2C_DATA_14 U18 -1800 200 300 R 50 50 1 1 I
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X IO_CHIPLINK_0_B2C_DATA_18 U19 -1800 -200 300 R 50 50 1 1 I
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X IO_CHIPLINK_0_C2B_DATA_5 U20 1800 1100 300 L 50 50 1 1 O
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X IO_CHIPLINK_0_C2B_DATA_11 U21 1800 500 300 L 50 50 1 1 O
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X IO_CHIPLINK_0_C2B_DATA_7 U22 1800 900 300 L 50 50 1 1 O
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X IO_CHIPLINK_0_B2C_DATA_12 V16 -1800 400 300 R 50 50 1 1 I
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X IO_CHIPLINK_0_B2C_DATA_16 V17 -1800 0 300 R 50 50 1 1 I
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X IO_CHIPLINK_0_B2C_DATA_9 V18 -1800 700 300 R 50 50 1 1 I
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X IO_CHIPLINK_0_B2C_DATA_15 V19 -1800 100 300 R 50 50 1 1 I
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X IO_CHIPLINK_0_B2C_DATA_25 V20 -1800 -900 300 R 50 50 1 1 I
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X IO_CHIPLINK_0_B2C_DATA_4 W16 -1800 1200 300 R 50 50 1 1 I
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X IO_CHIPLINK_0_B2C_DATA_3 W17 -1800 1300 300 R 50 50 1 1 I
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X IO_CHIPLINK_0_B2C_DATA_5 W18 -1800 1100 300 R 50 50 1 1 I
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X IO_CHIPLINK_0_B2C_DATA_11 W19 -1800 500 300 R 50 50 1 1 I
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X IO_CHIPLINK_0_B2C_DATA_28 W20 -1800 -1200 300 R 50 50 1 1 I
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X IO_CHIPLINK_0_B2C_SEND W21 -1800 -1700 300 R 50 50 1 1 I
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X IO_CHIPLINK_0_C2B_DATA_9 W22 1800 700 300 L 50 50 1 1 O
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X IO_CHIPLINK_0_B2C_DATA_0 Y16 -1800 1600 300 R 50 50 1 1 I
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X IO_CHIPLINK_0_B2C_DATA_7 Y17 -1800 900 300 R 50 50 1 1 I
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X IO_CHIPLINK_0_B2C_DATA_6 Y18 -1800 1000 300 R 50 50 1 1 I
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X IO_CHIPLINK_0_B2C_DATA_10 Y19 -1800 600 300 R 50 50 1 1 I
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X IO_CHIPLINK_0_B2C_DATA_27 Y20 -1800 -1100 300 R 50 50 1 1 I
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X IO_CHIPLINK_0_B2C_DATA_31 Y21 -1800 -1500 300 R 50 50 1 1 I
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X IO_CHIPLINK_0_B2C_DATA_30 Y22 -1800 -1400 300 R 50 50 1 1 I
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X IO_DDR_MEM_DATA[18] A4 1650 1800 300 L 50 50 2 1 B
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X IO_DDR_MEM_DATA[19] A5 1650 1900 300 L 50 50 2 1 B
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X IO_DDR_MEM_DQS_P[2] A6 1650 1500 300 L 50 50 2 1 B
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X IO_DDR_MEM_DQS_M[2] A7 1650 1400 300 L 50 50 2 1 B
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X IO_DDR_MEM_DATA[41] AA1 1650 -1900 300 L 50 50 2 1 B
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X IO_DDR_MEM_DATA[61] AA10 1650 -3900 300 L 50 50 2 1 B
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X IO_DDR_MEM_DATA[63] AA11 1650 -3700 300 L 50 50 2 1 B
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X IO_DDR_MEM_DATA[58] AA12 1650 -4200 300 L 50 50 2 1 B
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X IO_DDR_MEM_DATA[56] AA13 1650 -4400 300 L 50 50 2 1 B
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X IO_DDR_MEM_DATA[45] AA3 1650 -1500 300 L 50 50 2 1 B
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X IO_DDR_MEM_DATA[47] AA4 1650 -1300 300 L 50 50 2 1 B
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X IO_DDR_MEM_ODT[0] AA5 -1650 -100 300 R 50 50 2 1 O
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X IO_DDR_MEM_CKE[1] AA6 -1650 -400 300 R 50 50 2 1 O
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X IO_DDR_MEM_DQS_M[6] AA7 1650 -3400 300 L 50 50 2 1 B
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X IO_DDR_MEM_DQS_P[7] AA8 1650 -4500 300 L 50 50 2 1 B
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X IO_DDR_MEM_DATA[62] AA9 1650 -3800 300 L 50 50 2 1 B
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X IO_DDR_MEM_DATA[60] AB11 1650 -4000 300 L 50 50 2 1 B
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X IO_DDR_MEM_DM[7] AB12 1650 -4700 300 L 50 50 2 1 B
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X IO_DDR_MEM_DATA[44] AB2 1650 -1600 300 L 50 50 2 1 B
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X IO_DDR_MEM_DATA[46] AB3 1650 -1400 300 L 50 50 2 1 B
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X IO_DDR_MEM_ODT[1] AB5 -1650 -200 300 R 50 50 2 1 O
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X IO_DDR_MEM_CKE[0] AB6 -1650 -300 300 R 50 50 2 1 O
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X IO_DDR_MEM_DATA[57] AB8 1650 -4300 300 L 50 50 2 1 B
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X IO_DDR_MEM_DATA[59] AB9 1650 -4100 300 L 50 50 2 1 B
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X IO_DDR_MEM_DATA[1] B1 1650 4100 300 L 50 50 2 1 B
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X IO_DDR_MEM_DATA[17] B2 1650 1700 300 L 50 50 2 1 B
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X IO_DDR_MEM_DATA[22] B3 1650 2200 300 L 50 50 2 1 B
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X IO_DDR_MEM_DATA[16] B4 1650 1600 300 L 50 50 2 1 B
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X IO_DDR_MEM_DATA[20] B5 1650 2000 300 L 50 50 2 1 B
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X IO_DDR_MEM_DATA[23] B6 1650 2300 300 L 50 50 2 1 B
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X IO_DDR_MEM_DATA[4] C1 1650 4400 300 L 50 50 2 1 B
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X IO_DDR_MEM_DATA[29] C2 1650 900 300 L 50 50 2 1 B
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X IO_DDR_MEM_DATA[27] C3 1650 700 300 L 50 50 2 1 B
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X IO_DDR_MEM_DATA[24] C4 1650 400 300 L 50 50 2 1 B
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X IO_DDR_MEM_DATA[21] C5 1650 2100 300 L 50 50 2 1 B
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X IO_DDR_MEM_DM[2] C6 1650 1300 300 L 50 50 2 1 B
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X IO_DDR_MEM_DATA[31] C7 1650 1100 300 L 50 50 2 1 B
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X IO_DDR_MEM_DATA[0] D2 1650 4000 300 L 50 50 2 1 B
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X IO_DDR_MEM_DATA[30] D3 1650 1000 300 L 50 50 2 1 B
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X IO_DDR_MEM_DATA[25] D4 1650 500 300 L 50 50 2 1 B
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X IO_DDR_MEM_DM[3] D5 1650 100 300 L 50 50 2 1 B
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X IO_DDR_MEM_DATA[26] D6 1650 600 300 L 50 50 2 1 B
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X IO_DDR_MEM_DQS_M[3] D7 1650 200 300 L 50 50 2 1 B
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X IO_DDR_RSVD1 D8 -1650 -2700 300 R 50 50 2 1 P
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X IO_DDR_MEM_DATA[6] E1 1650 4600 300 L 50 50 2 1 B
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X IO_DDR_MEM_DATA[3] E2 1650 4300 300 L 50 50 2 1 B
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X IO_DDR_MEM_DM[0] E5 1650 3700 300 L 50 50 2 1 B
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X IO_DDR_MEM_DATA[28] E6 1650 800 300 L 50 50 2 1 B
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X IO_DDR_MEM_DQS_P[3] E7 1650 300 300 L 50 50 2 1 B
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X IO_DDR_RSVD0 E8 -1650 -2600 300 R 50 50 2 1 P
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X IO_DDR_MEM_DATA[9] F1 1650 2900 300 L 50 50 2 1 B
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X IO_DDR_MEM_DQS_P[0] F2 1650 3900 300 L 50 50 2 1 B
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X IO_DDR_MEM_DQS_M[0] F3 1650 3800 300 L 50 50 2 1 B
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X IO_DDR_MEM_DATA[2] F4 1650 4200 300 L 50 50 2 1 B
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X IO_DDR_MEM_DATA[10] F5 1650 3000 300 L 50 50 2 1 B
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X IO_DDR_CAL_0 F6 -1650 -4700 300 R 50 50 2 1 P
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X IO_DDR_RSVD2 F8 -1650 -2800 300 R 50 50 2 1 P
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X IO_DDR_RSVD3 F9 -1650 -2900 300 R 50 50 2 1 P
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X IO_DDR_MEM_DATA[11] G1 1650 3100 300 L 50 50 2 1 B
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X IO_DDR_MEM_DATA[7] G3 1650 4700 300 L 50 50 2 1 B
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X IO_DDR_MEM_DATA[5] G4 1650 4500 300 L 50 50 2 1 B
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X IO_DDR_MEM_DM[1] G5 1650 2500 300 L 50 50 2 1 B
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X DDR_VDDQ G7 -1650 4700 300 R 50 50 2 1 W
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X IO_DDR_MEM_DATA[12] H1 1650 3200 300 L 50 50 2 1 B
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X IO_DDR_MEM_DQS_P[1] H2 1650 2700 300 L 50 50 2 1 B
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X IO_DDR_MEM_DQS_M[1] H3 1650 2600 300 L 50 50 2 1 B
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X IO_DDR_MEM_DATA[8] H4 1650 2800 300 L 50 50 2 1 B
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X IO_DDR_MEM_ECC_DATA[0] H5 -1650 -2000 300 R 50 50 2 1 B
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X DDR_VDDQ H6 -1650 4600 300 R 50 50 2 1 W
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X DDRPLL_AVSS J13 -1650 3200 300 R 50 50 2 1 P
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X IO_DDR_MEM_DATA[14] J2 1650 3400 300 L 50 50 2 1 B
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X IO_DDR_MEM_DATA[13] J3 1650 3300 300 L 50 50 2 1 B
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X IO_DDR_MEM_DATA[15] J4 1650 3500 300 L 50 50 2 1 B
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X IO_DDR_MEM_ECC_DM J5 -1650 -2300 300 R 50 50 2 1 B
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X DDR_VDDQ J7 -1650 4500 300 R 50 50 2 1 W
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X IO_DDR_MEM_ECC_DATA[1] K1 -1650 -1900 300 R 50 50 2 1 B
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X DDRPLL_AVDD K13 -1650 3300 300 R 50 50 2 1 W
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X IO_DDR_MEM_ECC_DQS_P K2 -1650 -2100 300 R 50 50 2 1 B
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X IO_DDR_MEM_ECC_DQS_M K3 -1650 -2200 300 R 50 50 2 1 B
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X IO_DDR_MEM_ECC_DATA[2] K4 -1650 -1800 300 R 50 50 2 1 B
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X IO_DDR_MEM_CLK K5 -1650 -1000 300 R 50 50 2 1 O
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X DDR_VDDQ K6 -1650 4400 300 R 50 50 2 1 W
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X IO_DDR_MEM_ECC_DATA[4] L1 -1650 -1600 300 R 50 50 2 1 B
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X IO_DDR_MEM_ECC_DATA[3] L2 -1650 -1700 300 R 50 50 2 1 B
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X IO_DDR_MEM_ECC_DATA[7] L3 -1650 -1300 300 R 50 50 2 1 B
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X IO_DDR_MEM_ECC_DATA[5] L4 -1650 -1500 300 R 50 50 2 1 B
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X IO_DDR_MEM_CLK_N L5 -1650 -1100 300 R 50 50 2 1 O
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X DDR_VDDQ L7 -1650 4300 300 R 50 50 2 1 W
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X DDR_VDDPLL L9 -1650 3500 300 R 50 50 2 1 W
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X IO_DDR_MEM_ECC_DATA[6] M1 -1650 -1400 300 R 50 50 2 1 B
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X IO_DDR_MEM_RAS_N M2 -1650 300 300 R 50 50 2 1 O
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X IO_DDR_MEM_CAS_N M3 -1650 400 300 R 50 50 2 1 O
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X IO_DDR_MEM_BANK[0] M4 -1650 500 300 R 50 50 2 1 O
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X IO_DDR_MEM_BANK[2] M5 -1650 700 300 R 50 50 2 1 O
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X DDR_VDDQ M6 -1650 4200 300 R 50 50 2 1 W
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X DDR_VDDPLL M9 -1650 3400 300 R 50 50 2 1 W
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X IO_DDR_MEM_WE_N N1 -1650 200 300 R 50 50 2 1 O
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X IO_DDR_MEM_BANK[1] N2 -1650 600 300 R 50 50 2 1 O
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X IO_DDR_MEM_ADDRESS[0] N3 -1650 800 300 R 50 50 2 1 O
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X IO_DDR_MEM_ADDRESS[2] N4 -1650 1000 300 R 50 50 2 1 O
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X IO_DDR_MEM_ADDRESS[5] N5 -1650 1300 300 R 50 50 2 1 O
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X DDR_VDDQ N7 -1650 4100 300 R 50 50 2 1 W
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X IO_DDR_MEM_ADDRESS[3] P3 -1650 1100 300 R 50 50 2 1 O
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X IO_DDR_MEM_ADDRESS[6] P4 -1650 1400 300 R 50 50 2 1 O
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X IO_DDR_MEM_ADDRESS[12] P5 -1650 2000 300 R 50 50 2 1 O
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X DDR_VDDQ P6 -1650 4000 300 R 50 50 2 1 W
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X IO_DDR_MEM_ADDRESS[1] R1 -1650 900 300 R 50 50 2 1 O
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X IO_DDR_MEM_ADDRESS[7] R2 -1650 1500 300 R 50 50 2 1 O
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X IO_DDR_MEM_ADDRESS[8] R3 -1650 1600 300 R 50 50 2 1 O
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X IO_DDR_MEM_ADDRESS[11] R4 -1650 1900 300 R 50 50 2 1 O
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X IO_DDR_MEM_DATA[32] R5 1650 -800 300 L 50 50 2 1 B
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X DDR_VDDQ R7 -1650 3900 300 R 50 50 2 1 W
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X IO_DDR_MEM_ADDRESS[4] T1 -1650 1200 300 R 50 50 2 1 O
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X IO_DDR_MEM_ADDRESS[13] T2 -1650 2100 300 R 50 50 2 1 O
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X IO_DDR_MEM_ADDRESS[9] T3 -1650 1700 300 R 50 50 2 1 O
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X IO_DDR_MEM_DATA[34] T4 1650 -600 300 L 50 50 2 1 B
|
|
X IO_DDR_MEM_DM[4] T5 1650 -1100 300 L 50 50 2 1 B
|
|
X DDR_VDDQ T6 -1650 3800 300 R 50 50 2 1 W
|
|
X IO_DDR_MEM_ADDRESS[10] U1 -1650 1800 300 R 50 50 2 1 O
|
|
X IO_DDR_MEM_PARITY_IN U2 -1650 100 300 R 50 50 2 1 O
|
|
X IO_DDR_MEM_ADDRESS[14] U3 -1650 2200 300 R 50 50 2 1 O
|
|
X IO_DDR_MEM_DQS_M[4] U4 1650 -1000 300 L 50 50 2 1 B
|
|
X IO_DDR_MEM_DATA[39] U5 1650 -100 300 L 50 50 2 1 B
|
|
X DDR_VDDQCK U7 -1650 3700 300 R 50 50 2 1 W
|
|
X IO_DDR_MEM_DATA[35] V2 1650 -500 300 L 50 50 2 1 B
|
|
X IO_DDR_MEM_ADDRESS[15] V3 -1650 2300 300 R 50 50 2 1 O
|
|
X IO_DDR_MEM_DQS_P[4] V4 1650 -900 300 L 50 50 2 1 B
|
|
X IO_DDR_MEM_DATA[40] V5 1650 -2000 300 L 50 50 2 1 B
|
|
X IO_DDR_MEM_DATA[33] W1 1650 -700 300 L 50 50 2 1 B
|
|
X IO_DDR_MEM_DM[6] W10 1650 -3500 300 L 50 50 2 1 B
|
|
X IO_DDR_MEM_DATA[49] W11 1650 -3100 300 L 50 50 2 1 B
|
|
X IO_DDR_MEM_DATA[54] W12 1650 -2600 300 L 50 50 2 1 B
|
|
X IO_DDR_MEM_DATA[38] W2 1650 -200 300 L 50 50 2 1 B
|
|
X IO_DDR_MEM_DATA[37] W3 1650 -300 300 L 50 50 2 1 B
|
|
X IO_DDR_MEM_DQS_M[5] W4 1650 -2200 300 L 50 50 2 1 B
|
|
X IO_DDR_MEM_DM[5] W5 1650 -2300 300 L 50 50 2 1 B
|
|
X IO_DDR_MEM_ERROR_N W6 -1650 0 300 R 50 50 2 1 I
|
|
X IO_DDR_MEM_CS_N[1] W7 -1650 -600 300 R 50 50 2 1 O
|
|
X IO_DDR_MEM_DATA[51] W8 1650 -2900 300 L 50 50 2 1 B
|
|
X IO_DDR_MEM_DATA[55] W9 1650 -2500 300 L 50 50 2 1 B
|
|
X IO_DDR_MEM_DATA[36] Y1 1650 -400 300 L 50 50 2 1 B
|
|
X IO_DDR_MEM_DATA[52] Y10 1650 -2800 300 L 50 50 2 1 B
|
|
X IO_DDR_MEM_DATA[50] Y11 1650 -3000 300 L 50 50 2 1 B
|
|
X IO_DDR_MEM_DATA[48] Y12 1650 -3200 300 L 50 50 2 1 B
|
|
X IO_DDR_MEM_DATA[43] Y2 1650 -1700 300 L 50 50 2 1 B
|
|
X IO_DDR_MEM_DATA[42] Y3 1650 -1800 300 L 50 50 2 1 B
|
|
X IO_DDR_MEM_DQS_P[5] Y4 1650 -2100 300 L 50 50 2 1 B
|
|
X IO_DDR_MEM_RESET_N Y5 -1650 -700 300 R 50 50 2 1 O
|
|
X IO_DDR_MEM_CS_N[0] Y6 -1650 -500 300 R 50 50 2 1 O
|
|
X IO_DDR_MEM_DQS_P[6] Y7 1650 -3300 300 L 50 50 2 1 B
|
|
X IO_DDR_MEM_DQS_M[7] Y8 1650 -4600 300 L 50 50 2 1 B
|
|
X IO_DDR_MEM_DATA[53] Y9 1650 -2700 300 L 50 50 2 1 B
|
|
X IO_GEMGXL_0_RXD_2 A10 -1650 0 300 R 50 50 3 1 I
|
|
X IO_GEMGXL_0_RX_DV A11 -1650 -600 300 R 50 50 3 1 I
|
|
X IO_GEMGXL_0_RXD_0 A12 -1650 200 300 R 50 50 3 1 I
|
|
X IO_GEMGXL_0_COL A13 -1650 -900 300 R 50 50 3 1 I
|
|
X IO_GEMGXL_0_RXD_5 A8 -1650 -300 300 R 50 50 3 1 I
|
|
X IO_GEMGXL_0_RXD_1 B10 -1650 100 300 R 50 50 3 1 I
|
|
X IO_GEMGXL_0_RX_ER B11 -1650 -700 300 R 50 50 3 1 I
|
|
X IO_GEMGXL_0_TXD_0 B12 1650 200 300 L 50 50 3 1 O
|
|
X IO_GEMGXL_0_MDC B13 -1650 -1100 300 R 50 50 3 1 O
|
|
X IO_GEMGXL_0_TX_EN B7 1650 -600 300 L 50 50 3 1 O
|
|
X IO_GEMGXL_0_TXD_6 B8 1650 -400 300 L 50 50 3 1 O
|
|
X IO_GEMGXL_0_TXD_4 C10 1650 -200 300 L 50 50 3 1 O
|
|
X IO_GEMGXL_0_TXD_1 C11 1650 100 300 L 50 50 3 1 O
|
|
X IO_GEMGXL_0_MDIO C12 -1650 -1200 300 R 50 50 3 1 B
|
|
X IO_GEMGXL_0_CRS C13 -1650 -800 300 R 50 50 3 1 I
|
|
X IO_GEMGXL_0_TX_CLK C8 1650 300 300 L 50 50 3 1 I
|
|
X IO_GEMGXL_0_RXD_6 C9 -1650 -400 300 R 50 50 3 1 I
|
|
X IO_GEMGXL_0_TXD_5 D10 1650 -300 300 L 50 50 3 1 O
|
|
X IO_GEMGXL_0_TXD_2 D11 1650 0 300 L 50 50 3 1 O
|
|
X IO_GEMGXL_0_TXD_7 D9 1650 -500 300 L 50 50 3 1 O
|
|
X IO_GEMGXL_0_RXD_4 E10 -1650 -200 300 R 50 50 3 1 I
|
|
X IO_GEMGXL_0_RXD_3 E11 -1650 -100 300 R 50 50 3 1 I
|
|
X IO_GEMGXL_0_GTX_CLK E12 -1650 400 300 R 50 50 3 1 I
|
|
X IO_GEMGXL_0_RXD_7 E9 -1650 -500 300 R 50 50 3 1 I
|
|
X IO_GEMGXL_0_TX_ER F10 1650 -700 300 L 50 50 3 1 O
|
|
X IO_GEMGXL_0_TXD_3 F11 1650 -100 300 L 50 50 3 1 O
|
|
X IO_GEMGXL_0_RX_CLK F12 -1650 300 300 R 50 50 3 1 I
|
|
X GIVSS H11 -1650 800 300 R 50 50 3 1 P
|
|
X GIVDD J11 -1650 1200 300 R 50 50 3 1 W
|
|
X GEMGXLPLL_AVSS J12 1650 800 300 L 50 50 3 1 W
|
|
X GEMGXLPLL_AVDD K12 1650 1200 300 L 50 50 3 1 W
|
|
X IO_GPIO_0_PINS_9 A21 -1250 200 300 R 50 50 4 1 B
|
|
X IO_UART_1_RXD AA14 1250 1350 300 L 50 50 4 1 I
|
|
X IO_UART_1_TXD AA15 1250 1450 300 L 50 50 4 1 O
|
|
X IO_QSPI_2_DQ_0 AA16 1250 1050 300 L 50 50 4 1 B
|
|
X IO_QSPI_2_CS_0 AB14 1250 650 300 L 50 50 4 1 O
|
|
X IO_QSPI_2_DQ_1 AB15 1250 950 300 L 50 50 4 1 B
|
|
X IO_QSPI_2_DQ_2 AB16 1250 850 300 L 50 50 4 1 B
|
|
X IO_GPIO_0_PINS_11 B20 -1250 0 300 R 50 50 4 1 B
|
|
X IO_GPIO_0_PINS_12 B21 -1250 -100 300 R 50 50 4 1 B
|
|
X IO_GPIO_0_PINS_14 B22 -1250 -300 300 R 50 50 4 1 B
|
|
X IO_GPIO_0_PINS_7 C20 -1250 400 300 R 50 50 4 1 B
|
|
X IO_GPIO_0_PINS_2 C21 -1250 900 300 R 50 50 4 1 B
|
|
X IO_GPIO_0_PINS_1 C22 -1250 1000 300 R 50 50 4 1 B
|
|
X IO_GPIO_0_PINS_8 D19 -1250 300 300 R 50 50 4 1 B
|
|
X IO_GPIO_0_PINS_5 D20 -1250 600 300 R 50 50 4 1 B
|
|
X IO_GPIO_0_PINS_3 D21 -1250 800 300 R 50 50 4 1 B
|
|
X IO_PWM_1_PWM_0 D22 -1250 -1350 300 R 50 50 4 1 B
|
|
X IO_GPIO_0_PINS_4 E18 -1250 700 300 R 50 50 4 1 B
|
|
X IO_GPIO_0_PINS_13 E19 -1250 -200 300 R 50 50 4 1 B
|
|
X IO_GPIO_0_PINS_6 E20 -1250 500 300 R 50 50 4 1 B
|
|
X IO_GPIO_0_PINS_0 F17 -1250 1100 300 R 50 50 4 1 B
|
|
X IO_GPIO_0_PINS_10 F18 -1250 100 300 R 50 50 4 1 B
|
|
X IO_PWM_1_PWM_3 F19 -1250 -1650 300 R 50 50 4 1 B
|
|
X IO_PWM_0_PWM_2 F20 -1250 -1150 300 R 50 50 4 1 B
|
|
X IO_PWM_0_PWM_1 F21 -1250 -1050 300 R 50 50 4 1 B
|
|
X IO_QSPI_1_DQ_2 F22 1250 -600 300 L 50 50 4 1 B
|
|
X IO_GPIO_0_PINS_15 G17 -1250 -400 300 R 50 50 4 1 B
|
|
X IO_PWM_1_PWM_2 G18 -1250 -1550 300 R 50 50 4 1 B
|
|
X IO_PWM_0_PWM_0 G19 -1250 -950 300 R 50 50 4 1 B
|
|
X IO_PWM_0_PWM_3 G20 -1250 -1250 300 R 50 50 4 1 B
|
|
X IO_QSPI_1_CS_1 G21 1250 -900 300 L 50 50 4 1 O
|
|
X IO_QSPI_1_DQ_0 G22 1250 -400 300 L 50 50 4 1 B
|
|
X IO_PWM_1_PWM_1 H17 -1250 -1450 300 R 50 50 4 1 B
|
|
X IO_QSPI_1_SCK H18 1250 -300 300 L 50 50 4 1 O
|
|
X IO_QSPI_1_CS_2 H19 1250 -1000 300 L 50 50 4 1 O
|
|
X IO_QSPI_0_DQ_3 H20 1250 0 300 L 50 50 4 1 B
|
|
X IO_QSPI_0_DQ_0 H21 1250 300 300 L 50 50 4 1 B
|
|
X IO_QSPI_0_DQ_1 H22 1250 200 300 L 50 50 4 1 B
|
|
X IO_QSPI_1_DQ_3 J17 1250 -700 300 L 50 50 4 1 B
|
|
X IO_QSPI_1_DQ_1 J18 1250 -500 300 L 50 50 4 1 B
|
|
X IO_QSPI_0_CS_0 J19 1250 -100 300 L 50 50 4 1 O
|
|
X IO_QSPI_1_CS_3 J20 1250 -1100 300 L 50 50 4 1 O
|
|
X IO_QSPI_0_DQ_2 J21 1250 100 300 L 50 50 4 1 B
|
|
X IVSS K15 1250 -1350 300 L 50 50 4 1 P
|
|
X IVDD K16 -1250 1650 300 R 50 50 4 1 W
|
|
X IO_QSPI_1_CS_0 K17 1250 -800 300 L 50 50 4 1 O
|
|
X IO_QSPI_0_SCK K18 1250 400 300 L 50 50 4 1 O
|
|
X IVSS L15 1250 -1450 300 L 50 50 4 1 P
|
|
X IVDD L16 -1250 1550 300 R 50 50 4 1 W
|
|
X IVSS M15 1250 -1550 300 L 50 50 4 1 P
|
|
X IVDD M16 -1250 1450 300 R 50 50 4 1 W
|
|
X IVSS N15 1250 -1650 300 L 50 50 4 1 P
|
|
X IVDD N16 -1250 1350 300 R 50 50 4 1 W
|
|
X IO_I2C_0_SDA W13 -1250 -750 300 R 50 50 4 1 B
|
|
X IO_UART_0_RXD W14 1250 1550 300 L 50 50 4 1 I
|
|
X IO_QSPI_2_SCK W15 1250 1150 300 L 50 50 4 1 O
|
|
X IO_UART_0_TXD Y13 1250 1650 300 L 50 50 4 1 O
|
|
X IO_I2C_0_SCL Y14 -1250 -650 300 R 50 50 4 1 B
|
|
X IO_QSPI_2_DQ_3 Y15 1250 750 300 L 50 50 4 1 B
|
|
X HFXOSCIN A15 1600 -500 300 L 50 50 5 1 P
|
|
X IO_PRCI_RSVD0 A16 -1600 1600 300 R 50 50 5 1 P
|
|
X IO_PRCI_PORESET_N A17 -1600 -1600 300 R 50 50 5 1 I
|
|
X IO_MSEL_MSEL_0 A19 1600 -1300 300 L 50 50 5 1 I
|
|
X IO_MSEL_MSEL_2 A20 1600 -1500 300 L 50 50 5 1 I
|
|
X HFXOSCOUT B15 1600 -800 300 L 50 50 5 1 P
|
|
X IO_PRCI_RTCXALTCLKIN B16 -1600 1400 300 R 50 50 5 1 P
|
|
X IO_PRCI_RSVD6 B17 -1600 600 300 R 50 50 5 1 P
|
|
X IO_MSEL_MSEL_3 B19 1600 -1600 300 L 50 50 5 1 I
|
|
X IO_PRCI_RSVD15 C14 1600 -100 300 L 50 50 5 1 P
|
|
X IO_PRCI_HFXSEL C15 -1600 -300 300 R 50 50 5 1 I
|
|
X IO_PRCI_RSVD4 C16 -1600 800 300 R 50 50 5 1 P
|
|
X IO_PRCI_ERESET_N C17 -1600 -1300 300 R 50 50 5 1 I
|
|
X IO_MSEL_MSEL_1 C18 1600 -1400 300 L 50 50 5 1 I
|
|
X IO_JTAG_TDI C19 1600 500 300 L 70 50 5 1 I
|
|
X IO_PRCI_RSVD1 D13 -1600 1200 300 R 50 50 5 1 P
|
|
X IO_PRCI_RSVD11 D14 -1600 0 300 R 50 50 5 1 P
|
|
X IO_PRCI_RTCXSEL D15 -1600 1500 300 R 50 50 5 1 I
|
|
X IO_PRCI_RSVD3 D16 -1600 900 300 R 50 50 5 1 P
|
|
X IO_PRCI_RSVD10 D17 -1600 100 300 R 50 50 5 1 P
|
|
X IO_JTAG_TCK D18 1600 600 300 L 70 50 5 1 I
|
|
X IO_PRCI_RSVD2 E13 -1600 1100 300 R 50 50 5 1 P
|
|
X IO_PRCI_RSVD12 E14 -1600 -100 300 R 50 50 5 1 P
|
|
X IO_PRCI_RSVD5 E15 -1600 700 300 R 50 50 5 1 P
|
|
X IO_PRCI_RSVD9 E16 -1600 300 300 R 50 50 5 1 P
|
|
X IO_JTAG_TDO E17 1600 400 300 L 50 50 5 1 O
|
|
X IO_PRCI_RSVD14 F13 1600 0 300 L 50 50 5 1 P
|
|
X IO_PRCI_RSVD13 F14 1600 100 300 L 50 50 5 1 P
|
|
X IO_PRCI_HFXCLKIN F15 1600 -300 300 L 50 50 5 1 I
|
|
X IO_JTAG_TMS F16 1600 300 300 L 50 50 5 1 I
|
|
X IO_PRCI_RSVD7 G13 -1600 500 300 R 50 50 5 1 P
|
|
X OTP_VDD G14 1600 1600 300 L 50 50 5 1 I
|
|
X IO_PRCI_RSVD8 H13 -1600 400 300 R 50 50 5 1 P
|
|
X COREPLL_AVSS J14 1600 900 300 L 50 50 5 1 I
|
|
X COREPLL_AVDD K14 1600 1200 300 L 50 50 5 1 I
|
|
X VSS A1 -900 -2200 300 R 50 50 6 1 P
|
|
X VSS A14 -900 -2600 300 R 50 50 6 1 P
|
|
X VSS A18 -900 -2700 300 R 50 50 6 1 P
|
|
X VSS A2 -900 -2300 300 R 50 50 6 1 P
|
|
X VSS A22 -900 -2800 300 R 50 50 6 1 P
|
|
X VSS A3 -900 -2400 300 R 50 50 6 1 P
|
|
X VSS A9 -900 -2500 300 R 50 50 6 1 P
|
|
X VDD AA17 -900 -1900 300 R 50 50 6 1 W
|
|
X VSS AA2 -900 -2900 300 R 50 50 6 1 P
|
|
X VSS AB1 -900 -3000 300 R 50 50 6 1 P
|
|
X VSS AB10 -900 -3300 300 R 50 50 6 1 P
|
|
X VSS AB13 -900 -3400 300 R 50 50 6 1 P
|
|
X VSS AB17 900 -3400 300 L 50 50 6 1 P
|
|
X VSS AB22 900 -3300 300 L 50 50 6 1 P
|
|
X VSS AB4 -900 -3100 300 R 50 50 6 1 P
|
|
X VSS AB7 -900 -3200 300 R 50 50 6 1 P
|
|
X VDD B14 -900 3300 300 R 50 50 6 1 W
|
|
X VDD B18 -900 3200 300 R 50 50 6 1 W
|
|
X VDD B9 -900 3400 300 R 50 50 6 1 W
|
|
X VSS D1 900 -3200 300 L 50 50 6 1 P
|
|
X VSS D12 900 -3100 300 L 50 50 6 1 P
|
|
X VDD E21 -900 3000 300 R 50 50 6 1 W
|
|
X VSS E22 900 -2900 300 L 50 50 6 1 P
|
|
X VDD E3 -900 3100 300 R 50 50 6 1 W
|
|
X VSS E4 900 -3000 300 L 50 50 6 1 P
|
|
X VSS F7 900 -2800 300 L 50 50 6 1 P
|
|
X VSS G10 900 -2400 300 L 50 50 6 1 P
|
|
X VDD G11 -900 2800 300 R 50 50 6 1 W
|
|
X VSS G12 900 -2300 300 L 50 50 6 1 P
|
|
X VDD G15 -900 2700 300 R 50 50 6 1 W
|
|
X VSS G16 900 -2200 300 L 50 50 6 1 P
|
|
X VSS G2 900 -2700 300 L 50 50 6 1 P
|
|
X VSS G6 900 -2600 300 L 50 50 6 1 P
|
|
X VSS G8 900 -2500 300 L 50 50 6 1 P
|
|
X VDD G9 -900 2900 300 R 50 50 6 1 W
|
|
X VDD H10 -900 2500 300 R 50 50 6 1 W
|
|
X VDD H12 -900 2400 300 R 50 50 6 1 W
|
|
X VDD H14 -900 2300 300 R 50 50 6 1 W
|
|
X VSS H15 900 -1900 300 L 50 50 6 1 P
|
|
X VDD H16 -900 2200 300 R 50 50 6 1 W
|
|
X VSS H7 900 -2100 300 L 50 50 6 1 P
|
|
X VDD H8 -900 2600 300 R 50 50 6 1 W
|
|
X VSS H9 900 -2000 300 L 50 50 6 1 P
|
|
X VSS J1 900 -1800 300 L 50 50 6 1 P
|
|
X VSS J10 900 -1500 300 L 50 50 6 1 P
|
|
X VDD J15 -900 2000 300 R 50 50 6 1 W
|
|
X VSS J16 900 -1400 300 L 50 50 6 1 P
|
|
X VSS J22 900 -1300 300 L 50 50 6 1 P
|
|
X VSS J6 900 -1700 300 L 50 50 6 1 P
|
|
X VSS J8 900 -1600 300 L 50 50 6 1 P
|
|
X VDD J9 -900 2100 300 R 50 50 6 1 W
|
|
X VDD K10 -900 1800 300 R 50 50 6 1 W
|
|
X VSS K11 900 -1000 300 L 50 50 6 1 P
|
|
X VDD K21 -900 1700 300 R 50 50 6 1 W
|
|
X VSS K7 900 -1200 300 L 50 50 6 1 P
|
|
X VDD K8 -900 1900 300 R 50 50 6 1 W
|
|
X VSS K9 900 -1100 300 L 50 50 6 1 P
|
|
X VSS L10 -900 -2100 300 R 50 50 6 1 P
|
|
X VDD L11 -900 1600 300 R 50 50 6 1 W
|
|
X VSS L12 900 -700 300 L 50 50 6 1 P
|
|
X VDD L13 -900 1500 300 R 50 50 6 1 W
|
|
X VSS L14 900 -600 300 L 50 50 6 1 P
|
|
X VSS L6 900 -900 300 L 50 50 6 1 P
|
|
X VSS L8 900 -800 300 L 50 50 6 1 P
|
|
X VDD M10 -900 1300 300 R 50 50 6 1 W
|
|
X VSS M11 900 -400 300 L 50 50 6 1 P
|
|
X VDD M12 -900 1200 300 R 50 50 6 1 W
|
|
X VSS M13 900 -300 300 L 50 50 6 1 P
|
|
X VDD M14 -900 1100 300 R 50 50 6 1 W
|
|
X VSS M7 900 -500 300 L 50 50 6 1 P
|
|
X VDD M8 -900 1400 300 R 50 50 6 1 W
|
|
X VSS N10 900 0 300 L 50 50 6 1 P
|
|
X VDD N11 -900 900 300 R 50 50 6 1 W
|
|
X VSS N12 900 100 300 L 50 50 6 1 P
|
|
X VDD N13 -900 800 300 R 50 50 6 1 W
|
|
X VSS N14 900 200 300 L 50 50 6 1 P
|
|
X VSS N6 900 -200 300 L 50 50 6 1 P
|
|
X VSS N8 900 -100 300 L 50 50 6 1 P
|
|
X VDD N9 -900 1000 300 R 50 50 6 1 W
|
|
X VSS P1 900 300 300 L 50 50 6 1 P
|
|
X VDD P10 -900 500 300 R 70 50 6 1 W
|
|
X VSS P11 900 600 300 L 50 50 6 1 P
|
|
X VDD P12 -900 400 300 R 50 50 6 1 W
|
|
X VSS P13 900 700 300 L 50 50 6 1 P
|
|
X VDD P14 -900 300 300 R 50 50 6 1 W
|
|
X VSS P15 900 800 300 L 50 50 6 1 P
|
|
X VDD P16 -900 200 300 R 50 50 6 1 W
|
|
X VDD P2 -900 700 300 R 50 50 6 1 W
|
|
X VDD P21 -900 100 300 R 50 50 6 1 W
|
|
X VSS P22 900 900 300 L 50 50 6 1 P
|
|
X VSS P7 900 400 300 L 50 50 6 1 P
|
|
X VDD P8 -900 600 300 R 50 50 6 1 W
|
|
X VSS P9 900 500 300 L 50 50 6 1 P
|
|
X VSS R10 900 1200 300 L 50 50 6 1 P
|
|
X VDD R11 -900 -100 300 R 70 50 6 1 W
|
|
X VSS R12 900 1300 300 L 50 50 6 1 P
|
|
X VDD R13 -900 -200 300 R 50 50 6 1 W
|
|
X VSS R14 900 1400 300 L 50 50 6 1 P
|
|
X VDD R15 -900 -300 300 R 50 50 6 1 W
|
|
X VSS R16 900 1500 300 L 50 50 6 1 P
|
|
X VSS R6 900 1000 300 L 50 50 6 1 P
|
|
X VSS R8 900 1100 300 L 50 50 6 1 P
|
|
X VDD R9 -900 0 300 R 50 50 6 1 W
|
|
X VDD T10 -900 -500 300 R 50 50 6 1 W
|
|
X VSS T11 900 1800 300 L 50 50 6 1 P
|
|
X VDD T12 -900 -600 300 R 50 50 6 1 W
|
|
X VSS T13 900 1900 300 L 50 50 6 1 P
|
|
X VDD T14 -900 -700 300 R 50 50 6 1 W
|
|
X VSS T15 900 2000 300 L 50 50 6 1 P
|
|
X VDD T16 -900 -800 300 R 50 50 6 1 W
|
|
X VSS T17 900 2100 300 L 50 50 6 1 P
|
|
X VSS T7 900 1600 300 L 50 50 6 1 P
|
|
X VDD T8 -900 -400 300 R 50 50 6 1 W
|
|
X VSS T9 900 1700 300 L 50 50 6 1 P
|
|
X VSS U10 900 2400 300 L 50 50 6 1 P
|
|
X VDD U11 -900 -1000 300 R 50 50 6 1 W
|
|
X VSS U12 900 2500 300 L 50 50 6 1 P
|
|
X VDD U13 -900 -1100 300 R 50 50 6 1 W
|
|
X VSS U14 900 2600 300 L 50 50 6 1 P
|
|
X VDD U15 -900 -1200 300 R 50 50 6 1 W
|
|
X VSS U16 900 2700 300 L 50 50 6 1 P
|
|
X VSS U6 900 2200 300 L 50 50 6 1 P
|
|
X VSS U8 900 2300 300 L 50 50 6 1 P
|
|
X VDD U9 -900 -900 300 R 50 50 6 1 W
|
|
X VSS V1 900 2800 300 L 50 50 6 1 P
|
|
X VDD V10 -900 -1500 300 R 50 50 6 1 W
|
|
X VSS V11 900 3100 300 L 50 50 6 1 P
|
|
X VDD V12 -900 -1600 300 R 50 50 6 1 W
|
|
X VSS V13 900 3200 300 L 50 50 6 1 P
|
|
X VDD V14 -900 -1700 300 R 50 50 6 1 W
|
|
X VSS V15 900 3300 300 L 50 50 6 1 P
|
|
X VDD V21 -900 -1800 300 R 50 50 6 1 W
|
|
X VSS V22 900 3400 300 L 50 50 6 1 P
|
|
X VDD V6 -900 -1300 300 R 50 50 6 1 W
|
|
X VSS V7 900 2900 300 L 50 50 6 1 P
|
|
X VDD V8 -900 -1400 300 R 50 50 6 1 W
|
|
X VSS V9 900 3000 300 L 50 50 6 1 P
|
|
ENDDRAW
|
|
ENDDEF
|
|
#
|
|
#End Library
|