# SAM3XA UOTGHS

## USB On-The-Go Interface (UOTGHS) User Interface

### Registers

Register Mapping
Address | Register | Name | Access | Reset
--- | --- | --- | --- | ---
0x400AC000 | Device General Control Register | UOTGHS_DEVCTRL | read-write | 0x00000100
0x400AC004 | Device Global Interrupt Status Register | UOTGHS_DEVISR | read-only | 0x00000000
0x400AC008 | Device Global Interrupt Clear Register | UOTGHS_DEVICR | write-only | -
0x400AC00C | Device Global Interrupt Set Register | UOTGHS_DEVIFR | write-only | -
0x400AC010 | Device Global Interrupt Mask Register | UOTGHS_DEVIMR | read-only | 0x00000000
0x400AC014 | Device Global Interrupt Disable Register | UOTGHS_DEVIDR | write-only | -
0x400AC018 | Device Global Interrupt Enable Register | UOTGHS_DEVIER | write-only | -
0x400AC01C | Device Endpoint Register | UOTGHS_DEVEPT | read-write | 0x00000000
0x400AC020 | Device Frame Number Register | UOTGHS_DEVFNUM | read-only | 0x00000000
0x400AC100 | Device Endpoint Configuration Register (n = 0) | UOTGHS_DEVEPTCFG[10] | read-write | 0x00002000000020000000200000002000000020000000200000002000000020000000200000002000
0x400AC130 | Device Endpoint Status Register (n = 0) | UOTGHS_DEVEPTISR[10] | read-only | 0x00000100000001000000010000000100000001000000010000000100000001000000010000000100
0x400AC160 | Device Endpoint Clear Register (n = 0) | UOTGHS_DEVEPTICR[10] | write-only | -
0x400AC190 | Device Endpoint Set Register (n = 0) | UOTGHS_DEVEPTIFR[10] | write-only | -
0x400AC1C0 | Device Endpoint Mask Register (n = 0) | UOTGHS_DEVEPTIMR[10] | read-only | 0x0
0x400AC1F0 | Device Endpoint Enable Register (n = 0) | UOTGHS_DEVEPTIER[10] | write-only | -
0x400AC220 | Device Endpoint Disable Register (n = 0) | UOTGHS_DEVEPTIDR[10] | write-only | -
0x400AC310 | Device DMA Channel Next Descriptor Address Register (n = 1) | UOTGHS_DEVDMANXTDSC1 | read-write | 0x00000000
0x400AC314 | Device DMA Channel Address Register (n = 1) | UOTGHS_DEVDMAADDRESS1 | read-write | 0x00000000
0x400AC318 | Device DMA Channel Control Register (n = 1) | UOTGHS_DEVDMACONTROL1 | read-write | 0x00000000
0x400AC31C | Device DMA Channel Status Register (n = 1) | UOTGHS_DEVDMASTATUS1 | read-write | 0x00000000
0x400AC320 | Device DMA Channel Next Descriptor Address Register (n = 2) | UOTGHS_DEVDMANXTDSC2 | read-write | 0x00000000
0x400AC324 | Device DMA Channel Address Register (n = 2) | UOTGHS_DEVDMAADDRESS2 | read-write | 0x00000000
0x400AC328 | Device DMA Channel Control Register (n = 2) | UOTGHS_DEVDMACONTROL2 | read-write | 0x00000000
0x400AC32C | Device DMA Channel Status Register (n = 2) | UOTGHS_DEVDMASTATUS2 | read-write | 0x00000000
0x400AC330 | Device DMA Channel Next Descriptor Address Register (n = 3) | UOTGHS_DEVDMANXTDSC3 | read-write | 0x00000000
0x400AC334 | Device DMA Channel Address Register (n = 3) | UOTGHS_DEVDMAADDRESS3 | read-write | 0x00000000
0x400AC338 | Device DMA Channel Control Register (n = 3) | UOTGHS_DEVDMACONTROL3 | read-write | 0x00000000
0x400AC33C | Device DMA Channel Status Register (n = 3) | UOTGHS_DEVDMASTATUS3 | read-write | 0x00000000
0x400AC340 | Device DMA Channel Next Descriptor Address Register (n = 4) | UOTGHS_DEVDMANXTDSC4 | read-write | 0x00000000
0x400AC344 | Device DMA Channel Address Register (n = 4) | UOTGHS_DEVDMAADDRESS4 | read-write | 0x00000000
0x400AC348 | Device DMA Channel Control Register (n = 4) | UOTGHS_DEVDMACONTROL4 | read-write | 0x00000000
0x400AC34C | Device DMA Channel Status Register (n = 4) | UOTGHS_DEVDMASTATUS4 | read-write | 0x00000000
0x400AC350 | Device DMA Channel Next Descriptor Address Register (n = 5) | UOTGHS_DEVDMANXTDSC5 | read-write | 0x00000000
0x400AC354 | Device DMA Channel Address Register (n = 5) | UOTGHS_DEVDMAADDRESS5 | read-write | 0x00000000
0x400AC358 | Device DMA Channel Control Register (n = 5) | UOTGHS_DEVDMACONTROL5 | read-write | 0x00000000
0x400AC35C | Device DMA Channel Status Register (n = 5) | UOTGHS_DEVDMASTATUS5 | read-write | 0x00000000
0x400AC360 | Device DMA Channel Next Descriptor Address Register (n = 6) | UOTGHS_DEVDMANXTDSC6 | read-write | 0x00000000
0x400AC364 | Device DMA Channel Address Register (n = 6) | UOTGHS_DEVDMAADDRESS6 | read-write | 0x00000000
0x400AC368 | Device DMA Channel Control Register (n = 6) | UOTGHS_DEVDMACONTROL6 | read-write | 0x00000000
0x400AC36C | Device DMA Channel Status Register (n = 6) | UOTGHS_DEVDMASTATUS6 | read-write | 0x00000000
0x400AC370 | Device DMA Channel Next Descriptor Address Register (n = 7) | UOTGHS_DEVDMANXTDSC7 | read-write | 0x00000000
0x400AC374 | Device DMA Channel Address Register (n = 7) | UOTGHS_DEVDMAADDRESS7 | read-write | 0x00000000
0x400AC378 | Device DMA Channel Control Register (n = 7) | UOTGHS_DEVDMACONTROL7 | read-write | 0x00000000
0x400AC37C | Device DMA Channel Status Register (n = 7) | UOTGHS_DEVDMASTATUS7 | read-write | 0x00000000
0x400AC400 | Host General Control Register | UOTGHS_HSTCTRL | read-write | 0x00000000
0x400AC404 | Host Global Interrupt Status Register | UOTGHS_HSTISR | read-only | 0x00000000
0x400AC408 | Host Global Interrupt Clear Register | UOTGHS_HSTICR | write-only | -
0x400AC40C | Host Global Interrupt Set Register | UOTGHS_HSTIFR | write-only | -
0x400AC410 | Host Global Interrupt Mask Register | UOTGHS_HSTIMR | read-only | 0x00000000
0x400AC414 | Host Global Interrupt Disable Register | UOTGHS_HSTIDR | write-only | -
0x400AC418 | Host Global Interrupt Enable Register | UOTGHS_HSTIER | write-only | -
0x400AC41C | Host Pipe Register | UOTGHS_HSTPIP | read-write | 0x00000000
0x400AC420 | Host Frame Number Register | UOTGHS_HSTFNUM | read-write | 0x00000000
0x400AC424 | Host Address 1 Register | UOTGHS_HSTADDR1 | read-write | 0x00000000
0x400AC428 | Host Address 2 Register | UOTGHS_HSTADDR2 | read-write | 0x00000000
0x400AC42C | Host Address 3 Register | UOTGHS_HSTADDR3 | read-write | 0x00000000
0x400AC500 | Host Pipe Configuration Register (n = 0) | UOTGHS_HSTPIPCFG[10] | read-write | 0x0
0x400AC530 | Host Pipe Status Register (n = 0) | UOTGHS_HSTPIPISR[10] | read-only | 0x0
0x400AC560 | Host Pipe Clear Register (n = 0) | UOTGHS_HSTPIPICR[10] | write-only | -
0x400AC590 | Host Pipe Set Register (n = 0) | UOTGHS_HSTPIPIFR[10] | write-only | -
0x400AC5C0 | Host Pipe Mask Register (n = 0) | UOTGHS_HSTPIPIMR[10] | read-only | 0x0
0x400AC5F0 | Host Pipe Enable Register (n = 0) | UOTGHS_HSTPIPIER[10] | write-only | -
0x400AC620 | Host Pipe Disable Register (n = 0) | UOTGHS_HSTPIPIDR[10] | write-only | -
0x400AC650 | Host Pipe IN Request Register (n = 0) | UOTGHS_HSTPIPINRQ[10] | read-write | 0x0
0x400AC680 | Host Pipe Error Register (n = 0) | UOTGHS_HSTPIPERR[10] | read-write | 0x0
0x400AC710 | Host DMA Channel Next Descriptor Address Register (n = 1) | UOTGHS_HSTDMANXTDSC1 | read-write | 0x00000000
0x400AC714 | Host DMA Channel Address Register (n = 1) | UOTGHS_HSTDMAADDRESS1 | read-write | 0x00000000
0x400AC718 | Host DMA Channel Control Register (n = 1) | UOTGHS_HSTDMACONTROL1 | read-write | 0x00000000
0x400AC71C | Host DMA Channel Status Register (n = 1) | UOTGHS_HSTDMASTATUS1 | read-write | 0x00000000
0x400AC720 | Host DMA Channel Next Descriptor Address Register (n = 2) | UOTGHS_HSTDMANXTDSC2 | read-write | 0x00000000
0x400AC724 | Host DMA Channel Address Register (n = 2) | UOTGHS_HSTDMAADDRESS2 | read-write | 0x00000000
0x400AC728 | Host DMA Channel Control Register (n = 2) | UOTGHS_HSTDMACONTROL2 | read-write | 0x00000000
0x400AC72C | Host DMA Channel Status Register (n = 2) | UOTGHS_HSTDMASTATUS2 | read-write | 0x00000000
0x400AC730 | Host DMA Channel Next Descriptor Address Register (n = 3) | UOTGHS_HSTDMANXTDSC3 | read-write | 0x00000000
0x400AC734 | Host DMA Channel Address Register (n = 3) | UOTGHS_HSTDMAADDRESS3 | read-write | 0x00000000
0x400AC738 | Host DMA Channel Control Register (n = 3) | UOTGHS_HSTDMACONTROL3 | read-write | 0x00000000
0x400AC73C | Host DMA Channel Status Register (n = 3) | UOTGHS_HSTDMASTATUS3 | read-write | 0x00000000
0x400AC740 | Host DMA Channel Next Descriptor Address Register (n = 4) | UOTGHS_HSTDMANXTDSC4 | read-write | 0x00000000
0x400AC744 | Host DMA Channel Address Register (n = 4) | UOTGHS_HSTDMAADDRESS4 | read-write | 0x00000000
0x400AC748 | Host DMA Channel Control Register (n = 4) | UOTGHS_HSTDMACONTROL4 | read-write | 0x00000000
0x400AC74C | Host DMA Channel Status Register (n = 4) | UOTGHS_HSTDMASTATUS4 | read-write | 0x00000000
0x400AC750 | Host DMA Channel Next Descriptor Address Register (n = 5) | UOTGHS_HSTDMANXTDSC5 | read-write | 0x00000000
0x400AC754 | Host DMA Channel Address Register (n = 5) | UOTGHS_HSTDMAADDRESS5 | read-write | 0x00000000
0x400AC758 | Host DMA Channel Control Register (n = 5) | UOTGHS_HSTDMACONTROL5 | read-write | 0x00000000
0x400AC75C | Host DMA Channel Status Register (n = 5) | UOTGHS_HSTDMASTATUS5 | read-write | 0x00000000
0x400AC760 | Host DMA Channel Next Descriptor Address Register (n = 6) | UOTGHS_HSTDMANXTDSC6 | read-write | 0x00000000
0x400AC764 | Host DMA Channel Address Register (n = 6) | UOTGHS_HSTDMAADDRESS6 | read-write | 0x00000000
0x400AC768 | Host DMA Channel Control Register (n = 6) | UOTGHS_HSTDMACONTROL6 | read-write | 0x00000000
0x400AC76C | Host DMA Channel Status Register (n = 6) | UOTGHS_HSTDMASTATUS6 | read-write | 0x00000000
0x400AC770 | Host DMA Channel Next Descriptor Address Register (n = 7) | UOTGHS_HSTDMANXTDSC7 | read-write | 0x00000000
0x400AC774 | Host DMA Channel Address Register (n = 7) | UOTGHS_HSTDMAADDRESS7 | read-write | 0x00000000
0x400AC778 | Host DMA Channel Control Register (n = 7) | UOTGHS_HSTDMACONTROL7 | read-write | 0x00000000
0x400AC77C | Host DMA Channel Status Register (n = 7) | UOTGHS_HSTDMASTATUS7 | read-write | 0x00000000
0x400AC800 | General Control Register | UOTGHS_CTRL | read-write | 0x03004000
0x400AC804 | General Status Register | UOTGHS_SR | read-only | 0x00000400
0x400AC808 | General Status Clear Register | UOTGHS_SCR | write-only | -
0x400AC80C | General Status Set Register | UOTGHS_SFR | write-only | -
0x400AC82C | General Finite State Machine Register | UOTGHS_FSM | read-only | 0x00000009

### Register Fields

#### UOTGHS Device General Control Register

Name: UOTGHS_DEVCTRL

Access: read-write

Address: 0x400AC000

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | OPMODE2
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TSTPCKT | TSTK | TSTJ | LS | SPDCONF | RMWKUP | DETACH
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
ADDEN | UADD

- UADD: USB Address

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

- ADDEN: Address Enable

-

- DETACH: Detach

-

- RMWKUP: Remote Wake-Up

-

- SPDCONF: Mode Configuration

  Value | Name | Description
  --- | --- | ---
  0x0 | NORMAL | The peripheral starts in full-speed mode and performs a high-speed reset to switch to the high-speed mode if the host is high-speed capable.
  0x1 | LOW_POWER | For a better consumption, if high-speed is not needed.
  0x2 | HIGH_SPEED | Forced high speed.
  0x3 | FORCED_FS | The peripheral remains in full-speed mode whatever the host speed capability.

- LS: Low-Speed Mode Force

  Value | Name | Description
  --- | --- | ---
  0 | - | The full-speed mode is active.
  1 | - | The low-speed mode is active.

- TSTJ: Test mode J

  Value | Name | Description
  --- | --- | ---
  0 | - | The UTMI transceiver is in normal operation mode.
  1 | - | The UTMI transceiver generates high-speed J state for test purpose.

- TSTK: Test mode K

  Value | Name | Description
  --- | --- | ---
  0 | - | The UTMI transceiver is in normal operation mode.
  1 | - | The UTMI transceiver generates high-speed K state for test purpose.

- TSTPCKT: Test packet mode

  Value | Name | Description
  --- | --- | ---
  0 | - | The UTMI transceiver is in normal operation mode.
  1 | - | The UTMI transceiver generates test packets for test purpose.

- OPMODE2: Specific Operational mode

  Value | Name | Description
  --- | --- | ---
  0 | - | The UTMI transceiver is in normal operation mode.
  1 | - | The UTMI transceiver is in the \xc7 disable bit stuffing and NRZI encoding\xc8 operational mode for test purpose.

#### UOTGHS Device Global Interrupt Status Register

Name: UOTGHS_DEVISR

Access: read-only

Address: 0x400AC004

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | DMA_6 | DMA_5 | DMA_4 | DMA_3 | DMA_2 | DMA_1 | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | PEP_9 | PEP_8 | PEP_7 | PEP_6 | PEP_5 | PEP_4
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
PEP_3 | PEP_2 | PEP_1 | PEP_0 | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | UPRSM | EORSM | WAKEUP | EORST | SOF | MSOF | SUSP

- SUSP: Suspend Interrupt

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

- MSOF: Micro Start of Frame Interrupt

-

- SOF: Start of Frame Interrupt

-

- EORST: End of Reset Interrupt

-

- WAKEUP: Wake-Up Interrupt

-

- EORSM: End of Resume Interrupt

-

- UPRSM: Upstream Resume Interrupt

-

- PEP_0: Endpoint 0 Interrupt

-

- PEP_1: Endpoint 1 Interrupt

-

- PEP_2: Endpoint 2 Interrupt

-

- PEP_3: Endpoint 3 Interrupt

-

- PEP_4: Endpoint 4 Interrupt

-

- PEP_5: Endpoint 5 Interrupt

-

- PEP_6: Endpoint 6 Interrupt

-

- PEP_7: Endpoint 7 Interrupt

-

- PEP_8: Endpoint 8 Interrupt

-

- PEP_9: Endpoint 9 Interrupt

-

- DMA_1: DMA Channel 1 Interrupt

-

- DMA_2: DMA Channel 2 Interrupt

-

- DMA_3: DMA Channel 3 Interrupt

-

- DMA_4: DMA Channel 4 Interrupt

-

- DMA_5: DMA Channel 5 Interrupt

-

- DMA_6: DMA Channel 6 Interrupt

-

#### UOTGHS Device Global Interrupt Clear Register

Name: UOTGHS_DEVICR

Access: write-only

Address: 0x400AC008

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | UPRSMC | EORSMC | WAKEUPC | EORSTC | SOFC | MSOFC | SUSPC

- SUSPC: Suspend Interrupt Clear

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

- MSOFC: Micro Start of Frame Interrupt Clear

-

- SOFC: Start of Frame Interrupt Clear

-

- EORSTC: End of Reset Interrupt Clear

-

- WAKEUPC: Wake-Up Interrupt Clear

-

- EORSMC: End of Resume Interrupt Clear

-

- UPRSMC: Upstream Resume Interrupt Clear

-

#### UOTGHS Device Global Interrupt Set Register

Name: UOTGHS_DEVIFR

Access: write-only

Address: 0x400AC00C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | DMA_6 | DMA_5 | DMA_4 | DMA_3 | DMA_2 | DMA_1 | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | UPRSMS | EORSMS | WAKEUPS | EORSTS | SOFS | MSOFS | SUSPS

- SUSPS: Suspend Interrupt Set

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

- MSOFS: Micro Start of Frame Interrupt Set

-

- SOFS: Start of Frame Interrupt Set

-

- EORSTS: End of Reset Interrupt Set

-

- WAKEUPS: Wake-Up Interrupt Set

-

- EORSMS: End of Resume Interrupt Set

-

- UPRSMS: Upstream Resume Interrupt Set

-

- DMA_1: DMA Channel 1 Interrupt Set

-

- DMA_2: DMA Channel 2 Interrupt Set

-

- DMA_3: DMA Channel 3 Interrupt Set

-

- DMA_4: DMA Channel 4 Interrupt Set

-

- DMA_5: DMA Channel 5 Interrupt Set

-

- DMA_6: DMA Channel 6 Interrupt Set

-

#### UOTGHS Device Global Interrupt Mask Register

Name: UOTGHS_DEVIMR

Access: read-only

Address: 0x400AC010

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | DMA_6 | DMA_5 | DMA_4 | DMA_3 | DMA_2 | DMA_1 | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | PEP_9 | PEP_8 | PEP_7 | PEP_6 | PEP_5 | PEP_4
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
PEP_3 | PEP_2 | PEP_1 | PEP_0 | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | UPRSME | EORSME | WAKEUPE | EORSTE | SOFE | MSOFE | SUSPE

- SUSPE: Suspend Interrupt Mask

-

- MSOFE: Micro Start of Frame Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | The interrupt is disabled.
  1 | - | The interrupt is enabled.

- SOFE: Start of Frame Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | The interrupt is disabled.
  1 | - | The interrupt is enabled.

- EORSTE: End of Reset Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | The interrupt is disabled.
  1 | - | The interrupt is enabled.

- WAKEUPE: Wake-Up Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | The interrupt is disabled.
  1 | - | The interrupt is enabled.

- EORSME: End of Resume Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | The interrupt is disabled.
  1 | - | The interrupt is enabled.

- UPRSME: Upstream Resume Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | The interrupt is disabled.
  1 | - | The interrupt is enabled.

- PEP_0: Endpoint 0 Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | The interrupt is disabled.
  1 | - | The interrupt is enabled.

- PEP_1: Endpoint 1 Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | The interrupt is disabled.
  1 | - | The interrupt is enabled.

- PEP_2: Endpoint 2 Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | The interrupt is disabled.
  1 | - | The interrupt is enabled.

- PEP_3: Endpoint 3 Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | The interrupt is disabled.
  1 | - | The interrupt is enabled.

- PEP_4: Endpoint 4 Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | The interrupt is disabled.
  1 | - | The interrupt is enabled.

- PEP_5: Endpoint 5 Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | The interrupt is disabled.
  1 | - | The interrupt is enabled.

- PEP_6: Endpoint 6 Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | The interrupt is disabled.
  1 | - | The interrupt is enabled.

- PEP_7: Endpoint 7 Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | The interrupt is disabled.
  1 | - | The interrupt is enabled.

- PEP_8: Endpoint 8 Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | The interrupt is disabled.
  1 | - | The interrupt is enabled.

- PEP_9: Endpoint 9 Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | The interrupt is disabled.
  1 | - | The interrupt is enabled.

- DMA_1: DMA Channel 1 Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | The interrupt is disabled.
  1 | - | The interrupt is enabled.

- DMA_2: DMA Channel 2 Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | The interrupt is disabled.
  1 | - | The interrupt is enabled.

- DMA_3: DMA Channel 3 Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | The interrupt is disabled.
  1 | - | The interrupt is enabled.

- DMA_4: DMA Channel 4 Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | The interrupt is disabled.
  1 | - | The interrupt is enabled.

- DMA_5: DMA Channel 5 Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | The interrupt is disabled.
  1 | - | The interrupt is enabled.

- DMA_6: DMA Channel 6 Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | The interrupt is disabled.
  1 | - | The interrupt is enabled.

#### UOTGHS Device Global Interrupt Disable Register

Name: UOTGHS_DEVIDR

Access: write-only

Address: 0x400AC014

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | DMA_6 | DMA_5 | DMA_4 | DMA_3 | DMA_2 | DMA_1 | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | PEP_9 | PEP_8 | PEP_7 | PEP_6 | PEP_5 | PEP_4
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
PEP_3 | PEP_2 | PEP_1 | PEP_0 | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | UPRSMEC | EORSMEC | WAKEUPEC | EORSTEC | SOFEC | MSOFEC | SUSPEC

- SUSPEC: Suspend Interrupt Disable

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

- MSOFEC: Micro Start of Frame Interrupt Disable

-

- SOFEC: Start of Frame Interrupt Disable

-

- EORSTEC: End of Reset Interrupt Disable

-

- WAKEUPEC: Wake-Up Interrupt Disable

-

- EORSMEC: End of Resume Interrupt Disable

-

- UPRSMEC: Upstream Resume Interrupt Disable

-

- PEP_0: Endpoint 0 Interrupt Disable

-

- PEP_1: Endpoint 1 Interrupt Disable

-

- PEP_2: Endpoint 2 Interrupt Disable

-

- PEP_3: Endpoint 3 Interrupt Disable

-

- PEP_4: Endpoint 4 Interrupt Disable

-

- PEP_5: Endpoint 5 Interrupt Disable

-

- PEP_6: Endpoint 6 Interrupt Disable

-

- PEP_7: Endpoint 7 Interrupt Disable

-

- PEP_8: Endpoint 8 Interrupt Disable

-

- PEP_9: Endpoint 9 Interrupt Disable

-

- DMA_1: DMA Channel 1 Interrupt Disable

-

- DMA_2: DMA Channel 2 Interrupt Disable

-

- DMA_3: DMA Channel 3 Interrupt Disable

-

- DMA_4: DMA Channel 4 Interrupt Disable

-

- DMA_5: DMA Channel 5 Interrupt Disable

-

- DMA_6: DMA Channel 6 Interrupt Disable

-

#### UOTGHS Device Global Interrupt Enable Register

Name: UOTGHS_DEVIER

Access: write-only

Address: 0x400AC018

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | DMA_6 | DMA_5 | DMA_4 | DMA_3 | DMA_2 | DMA_1 | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | PEP_9 | PEP_8 | PEP_7 | PEP_6 | PEP_5 | PEP_4
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
PEP_3 | PEP_2 | PEP_1 | PEP_0 | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | UPRSMES | EORSMES | WAKEUPES | EORSTES | SOFES | MSOFES | SUSPES

- SUSPES: Suspend Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

- MSOFES: Micro Start of Frame Interrupt Enable

-

- SOFES: Start of Frame Interrupt Enable

-

- EORSTES: End of Reset Interrupt Enable

-

- WAKEUPES: Wake-Up Interrupt Enable

-

- EORSMES: End of Resume Interrupt Enable

-

- UPRSMES: Upstream Resume Interrupt Enable

-

- PEP_0: Endpoint 0 Interrupt Enable

-

- PEP_1: Endpoint 1 Interrupt Enable

-

- PEP_2: Endpoint 2 Interrupt Enable

-

- PEP_3: Endpoint 3 Interrupt Enable

-

- PEP_4: Endpoint 4 Interrupt Enable

-

- PEP_5: Endpoint 5 Interrupt Enable

-

- PEP_6: Endpoint 6 Interrupt Enable

-

- PEP_7: Endpoint 7 Interrupt Enable

-

- PEP_8: Endpoint 8 Interrupt Enable

-

- PEP_9: Endpoint 9 Interrupt Enable

-

- DMA_1: DMA Channel 1 Interrupt Enable

-

- DMA_2: DMA Channel 2 Interrupt Enable

-

- DMA_3: DMA Channel 3 Interrupt Enable

-

- DMA_4: DMA Channel 4 Interrupt Enable

-

- DMA_5: DMA Channel 5 Interrupt Enable

-

- DMA_6: DMA Channel 6 Interrupt Enable

-

#### UOTGHS Device Endpoint Register

Name: UOTGHS_DEVEPT

Access: read-write

Address: 0x400AC01C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | EPRST8
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
EPRST7 | EPRST6 | EPRST5 | EPRST4 | EPRST3 | EPRST2 | EPRST1 | EPRST0
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | EPEN8
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
EPEN7 | EPEN6 | EPEN5 | EPEN4 | EPEN3 | EPEN2 | EPEN1 | EPEN0

- EPEN0: Endpoint 0 Enable

-

- EPEN1: Endpoint 1 Enable

-

- EPEN2: Endpoint 2 Enable

-

- EPEN3: Endpoint 3 Enable

-

- EPEN4: Endpoint 4 Enable

-

- EPEN5: Endpoint 5 Enable

-

- EPEN6: Endpoint 6 Enable

-

- EPEN7: Endpoint 7 Enable

-

- EPEN8: Endpoint 8 Enable

-

- EPRST0: Endpoint 0 Reset

-

- EPRST1: Endpoint 1 Reset

-

- EPRST2: Endpoint 2 Reset

-

- EPRST3: Endpoint 3 Reset

-

- EPRST4: Endpoint 4 Reset

-

- EPRST5: Endpoint 5 Reset

-

- EPRST6: Endpoint 6 Reset

-

- EPRST7: Endpoint 7 Reset

-

- EPRST8: Endpoint 8 Reset

-

#### UOTGHS Device Frame Number Register

Name: UOTGHS_DEVFNUM

Access: read-only

Address: 0x400AC020

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
FNCERR | - | FNUM
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
FNUM | MFNUM

- MFNUM: Micro Frame Number

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

- FNUM: Frame Number

-

- FNCERR: Frame Number CRC Error

-

#### UOTGHS Device Endpoint Configuration Register (n = 0)

Name: UOTGHS_DEVEPTCFG[0:9]

Access: read-write

Address: 0x400AC100

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | NBTRANS | EPTYPE | - | AUTOSW | EPDIR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | EPSIZE | EPBK | ALLOC | -

- ALLOC: Endpoint Memory Allocate

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

- EPBK: Endpoint Banks

  Value | Name | Description
  --- | --- | ---
  0x0 | 1_BANK | Single-bank endpoint
  0x1 | 2_BANK | Double-bank endpoint
  0x2 | 3_BANK | Triple-bank endpoint

- EPSIZE: Endpoint Size

  Value | Name | Description
  --- | --- | ---
  0x0 | 8_BYTE | 8 bytes
  0x1 | 16_BYTE | 16 bytes
  0x2 | 32_BYTE | 32 bytes
  0x3 | 64_BYTE | 64 bytes
  0x4 | 128_BYTE | 128 bytes
  0x5 | 256_BYTE | 256 bytes
  0x6 | 512_BYTE | 512 bytes
  0x7 | 1024_BYTE | 1024 bytes

- EPDIR: Endpoint Direction

  Value | Name | Description
  --- | --- | ---
  0 | OUT | The endpoint direction is OUT.
  1 | IN | The endpoint direction is IN (nor for control endpoints).

- AUTOSW: Automatic Switch

  Value | Name | Description
  --- | --- | ---
  0 | - | The automatic bank switching is disabled.
  1 | - | The automatic bank switching is enabled.

- EPTYPE: Endpoint Type

  Value | Name | Description
  --- | --- | ---
  0x0 | CTRL | Control
  0x1 | ISO | Isochronous
  0x2 | BLK | Bulk
  0x3 | INTRPT | Interrupt

- NBTRANS: Number of transaction per microframe for isochronous endpoint

  Value | Name | Description
  --- | --- | ---
  0x0 | 0_TRANS | reserved to endpoint that does not have the high-bandwidth isochronous capability.
  0x1 | 1_TRANS | default value: one transaction per micro-frame.
  0x2 | 2_TRANS | 2 transactions per micro-frame. This endpoint should be configured as double-bank.
  0x3 | 3_TRANS | 3 transactions per micro-frame. This endpoint should be configured as triple-bank.

#### UOTGHS Device Endpoint Status Register (n = 0)

Name: UOTGHS_DEVEPTISR[0:9]

Access: read-only

Address: 0x400AC130

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | BYCT
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
BYCT | - | CFGOK | CTRLDIR | RWALL
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CURRBK | NBUSYBK | - | ERRORTRANS | DTSEQ
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
SHORTPACKET | STALLEDI | OVERFI | NAKINI | NAKOUTI | RXSTPI | RXOUTI | TXINI

- TXINI: Transmitted IN Data Interrupt

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

- RXOUTI: Received OUT Data Interrupt

-

- RXSTPI: Received SETUP Interrupt

-

- UNDERFI: Underflow Interrupt

-

- NAKOUTI: NAKed OUT Interrupt

-

- HBISOINERRI: High bandwidth isochronous IN Underflow Error Interrupt

-

- NAKINI: NAKed IN Interrupt

-

- HBISOFLUSHI: High Bandwidth Isochronous IN Flush Interrupt

-

- OVERFI: Overflow Interrupt

-

- STALLEDI: STALLed Interrupt

-

- CRCERRI: CRC Error Interrupt

-

- SHORTPACKET: Short Packet Interrupt

-

- DTSEQ: Data Toggle Sequence

  Value | Name | Description
  --- | --- | ---
  0x0 | DATA0 | Data0 toggle sequence
  0x1 | DATA1 | Data1 toggle sequence
  0x2 | DATA2 | Data2 toggle sequence (for high-bandwidth isochronous endpoint)
  0x3 | MDATA | MData toggle sequence (for high-bandwidth isochronous endpoint)

- ERRORTRANS: High-bandwidth isochronous OUT endpoint transaction error Interrupt

-

- NBUSYBK: Number of Busy Banks

  Value | Name | Description
  --- | --- | ---
  0x0 | 0_BUSY | 0 busy bank (all banks free)
  0x1 | 1_BUSY | 1 busy bank
  0x2 | 2_BUSY | 2 busy banks
  0x3 | 3_BUSY | 3 busy banks

- CURRBK: Current Bank

  Value | Name | Description
  --- | --- | ---
  0x0 | BANK0 | Current bank is bank0
  0x1 | BANK1 | Current bank is bank1
  0x2 | BANK2 | Current bank is bank2

- RWALL: Read-write Allowed

-

- CTRLDIR: Control Direction

-

- CFGOK: Configuration OK Status

-

- BYCT: Byte Count

-

#### UOTGHS Device Endpoint Clear Register (n = 0)

Name: UOTGHS_DEVEPTICR[0:9]

Access: write-only

Address: 0x400AC160

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
SHORTPACKETC | STALLEDIC | OVERFIC | NAKINIC | NAKOUTIC | RXSTPIC | RXOUTIC | TXINIC

- TXINIC: Transmitted IN Data Interrupt Clear

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

- RXOUTIC: Received OUT Data Interrupt Clear

-

- RXSTPIC: Received SETUP Interrupt Clear

-

- UNDERFIC: Underflow Interrupt Clear

-

- NAKOUTIC: NAKed OUT Interrupt Clear

-

- HBISOINERRIC: High bandwidth isochronous IN Underflow Error Interrupt Clear

-

- NAKINIC: NAKed IN Interrupt Clear

-

- HBISOFLUSHIC: High Bandwidth Isochronous IN Flush Interrupt Clear

-

- OVERFIC: Overflow Interrupt Clear

-

- STALLEDIC: STALLed Interrupt Clear

-

- CRCERRIC: CRC Error Interrupt Clear

-

- SHORTPACKETC: Short Packet Interrupt Clear

-

#### UOTGHS Device Endpoint Set Register (n = 0)

Name: UOTGHS_DEVEPTIFR[0:9]

Access: write-only

Address: 0x400AC190

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | NBUSYBKS | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
SHORTPACKETS | STALLEDIS | OVERFIS | NAKINIS | NAKOUTIS | RXSTPIS | RXOUTIS | TXINIS

- TXINIS: Transmitted IN Data Interrupt Set

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

- RXOUTIS: Received OUT Data Interrupt Set

-

- RXSTPIS: Received SETUP Interrupt Set

-

- UNDERFIS: Underflow Interrupt Set

-

- NAKOUTIS: NAKed OUT Interrupt Set

-

- HBISOINERRIS: High bandwidth isochronous IN Underflow Error Interrupt Set

-

- NAKINIS: NAKed IN Interrupt Set

-

- HBISOFLUSHIS: High Bandwidth Isochronous IN Flush Interrupt Set

-

- OVERFIS: Overflow Interrupt Set

-

- STALLEDIS: STALLed Interrupt Set

-

- CRCERRIS: CRC Error Interrupt Set

-

- SHORTPACKETS: Short Packet Interrupt Set

-

- NBUSYBKS: Number of Busy Banks Interrupt Set

-

#### UOTGHS Device Endpoint Mask Register (n = 0)

Name: UOTGHS_DEVEPTIMR[0:9]

Access: read-only

Address: 0x400AC1C0

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | STALLRQ | RSTDT | NYETDIS | EPDISHDMA
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | FIFOCON | KILLBK | NBUSYBKE | - | ERRORTRANSE | DATAXE | MDATAE
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
SHORTPACKETE | STALLEDE | OVERFE | NAKINE | NAKOUTE | RXSTPE | RXOUTE | TXINE

- TXINE: Transmitted IN Data Interrupt

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

- RXOUTE: Received OUT Data Interrupt

-

- RXSTPE: Received SETUP Interrupt

-

- UNDERFE: Underflow Interrupt

-

- NAKOUTE: NAKed OUT Interrupt

-

- HBISOINERRE: High Bandwidth Isochronous IN Error Interrupt

-

- NAKINE: NAKed IN Interrupt

-

- HBISOFLUSHE: High Bandwidth Isochronous IN Flush Interrupt

-

- OVERFE: Overflow Interrupt

-

- STALLEDE: STALLed Interrupt

-

- CRCERRE: CRC Error Interrupt

-

- SHORTPACKETE: Short Packet Interrupt

-

- MDATAE: MData Interrupt

-

- DATAXE: DataX Interrupt

-

- ERRORTRANSE: Transaction Error Interrupt

-

- NBUSYBKE: Number of Busy Banks Interrupt

-

- KILLBK: Kill IN Bank

-

- FIFOCON: FIFO Control

-

- EPDISHDMA: Endpoint Interrupts Disable HDMA Request

-

- NYETDIS: NYET Token Disable

-

- RSTDT: Reset Data Toggle

-

- STALLRQ: STALL Request

-

#### UOTGHS Device Endpoint Enable Register (n = 0)

Name: UOTGHS_DEVEPTIER[0:9]

Access: write-only

Address: 0x400AC1F0

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | STALLRQS | RSTDTS | NYETDISS | EPDISHDMAS
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | KILLBKS | NBUSYBKES | - | ERRORTRANSES | DATAXES | MDATAES
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
SHORTPACKETES | STALLEDES | OVERFES | NAKINES | NAKOUTES | RXSTPES | RXOUTES | TXINES

- TXINES: Transmitted IN Data Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

- RXOUTES: Received OUT Data Interrupt Enable

-

- RXSTPES: Received SETUP Interrupt Enable

-

- UNDERFES: Underflow Interrupt Enable

-

- NAKOUTES: NAKed OUT Interrupt Enable

-

- HBISOINERRES: High Bandwidth Isochronous IN Error Interrupt Enable

-

- NAKINES: NAKed IN Interrupt Enable

-

- HBISOFLUSHES: High Bandwidth Isochronous IN Flush Interrupt Enable

-

- OVERFES: Overflow Interrupt Enable

-

- STALLEDES: STALLed Interrupt Enable

-

- CRCERRES: CRC Error Interrupt Enable

-

- SHORTPACKETES: Short Packet Interrupt Enable

-

- MDATAES: MData Interrupt Enable

-

- DATAXES: DataX Interrupt Enable

-

- ERRORTRANSES: Transaction Error Interrupt Enable

-

- NBUSYBKES: Number of Busy Banks Interrupt Enable

-

- KILLBKS: Kill IN Bank

-

- EPDISHDMAS: Endpoint Interrupts Disable HDMA Request Enable

-

- NYETDISS: NYET Token Disable Enable

-

- RSTDTS: Reset Data Toggle Enable

-

- STALLRQS: STALL Request Enable

-

#### UOTGHS Device Endpoint Disable Register (n = 0)

Name: UOTGHS_DEVEPTIDR[0:9]

Access: write-only

Address: 0x400AC220

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | STALLRQC | - | NYETDISC | EPDISHDMAC
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | FIFOCONC | - | NBUSYBKEC | - | ERRORTRANSEC | DATAXEC | MDATEC
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
SHORTPACKETEC | STALLEDEC | OVERFEC | NAKINEC | NAKOUTEC | RXSTPEC | RXOUTEC | TXINEC

- TXINEC: Transmitted IN Interrupt Clear

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

- RXOUTEC: Received OUT Data Interrupt Clear

-

- RXSTPEC: Received SETUP Interrupt Clear

-

- UNDERFEC: Underflow Interrupt Clear

-

- NAKOUTEC: NAKed OUT Interrupt Clear

-

- HBISOINERREC: High Bandwidth Isochronous IN Error Interrupt Clear

-

- NAKINEC: NAKed IN Interrupt Clear

-

- HBISOFLUSHEC: High Bandwidth Isochronous IN Flush Interrupt Clear

-

- OVERFEC: Overflow Interrupt Clear

-

- STALLEDEC: STALLed Interrupt Clear

-

- CRCERREC: CRC Error Interrupt Clear

-

- SHORTPACKETEC: Shortpacket Interrupt Clear

-

- MDATEC: MData Interrupt Clear

-

- DATAXEC: DataX Interrupt Clear

-

- ERRORTRANSEC: Transaction Error Interrupt Clear

-

- NBUSYBKEC: Number of Busy Banks Interrupt Clear

-

- FIFOCONC: FIFO Control Clear

-

- EPDISHDMAC: Endpoint Interrupts Disable HDMA Request Clear

-

- NYETDISC: NYET Token Disable Clear

-

- STALLRQC: STALL Request Clear

-

#### UOTGHS Device DMA Channel Next Descriptor Address Register (n = 1)

Name: UOTGHS_DEVDMANXTDSC1

Access: read-write

Address: 0x400AC310

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
NXT_DSC_ADD
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NXT_DSC_ADD
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NXT_DSC_ADD
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NXT_DSC_ADD

- NXT_DSC_ADD: Next Descriptor Address

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

#### UOTGHS Device DMA Channel Address Register (n = 1)

Name: UOTGHS_DEVDMAADDRESS1

Access: read-write

Address: 0x400AC314

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
BUFF_ADD
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
BUFF_ADD
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
BUFF_ADD
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
BUFF_ADD

- BUFF_ADD: Buffer Address

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

#### UOTGHS Device DMA Channel Control Register (n = 1)

Name: UOTGHS_DEVDMACONTROL1

Access: read-write

Address: 0x400AC318

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
BUFF_LENGTH
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
BUFF_LENGTH
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
BURST_LCK | DESC_LD_IT | END_BUFFIT | END_TR_IT | END_B_EN | END_TR_EN | LDNXT_DSC | CHANN_ENB

- CHANN_ENB: Channel Enable Command

-

- LDNXT_DSC: Load Next Channel Transfer Descriptor Enable Command

-

- END_TR_EN: End of Transfer Enable Control

  Value | Name | Description
  --- | --- | ---
  0 | - | USB end of transfer is ignored.
  1 | - | UOTGHS device can put an end to the current buffer transfer.

- END_B_EN: End of Buffer Enable Control

  Value | Name | Description
  --- | --- | ---
  0 | - | DMA Buffer End has no impact on USB packet transfer.
  1 | - | the endpoint can validate the packet (according to the values programmed in the UOTGHS_DEVEPTCFGx.AUTOSW field, and in the UOTGHS_DEVEPTIERx.SHORTPACKETES field) at DMA Buffer End, i.e. when the UOTGHS_DEVDMASTATUS.BUFF_COUNT reaches 0.

- END_TR_IT: End of Transfer Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | UOTGHS device initiated buffer transfer completion will not trigger any interrupt at UOTGHS_DEVDMASTATUSx.END_TR_ST rising.
  1 | - | an interrupt is sent after the buffer transfer is complete, if the UOTGHS device has ended the buffer transfer.

- END_BUFFIT: End of Buffer Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | UOTGHS_DEVDMA_STATUSx.END_BF_ST rising will not trigger any interrupt.
  1 | - | an interrupt is generated when the UOTGHS_HSTDMASTATUSx.BUFF_COUNT reaches zero.

- DESC_LD_IT: Descriptor Loaded Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | UOTGHS_DEVDMASTATUSx.DESC_LDST rising will not trigger any interrupt.
  1 | - | an interrupt is generated when a descriptor has been loaded from the bus.

- BURST_LCK: Burst Lock Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | the DMA never locks bus access.
  1 | - | USB packets AHB data bursts are locked for maximum optimization of the bus bandwidth usage and maximization of fly-by AHB burst duration.

- BUFF_LENGTH: Buffer Byte Length (Write-only)

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

#### UOTGHS Device DMA Channel Status Register (n = 1)

Name: UOTGHS_DEVDMASTATUS1

Access: read-write

Address: 0x400AC31C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
BUFF_COUNT
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
BUFF_COUNT
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | DESC_LDST | END_BF_ST | END_TR_ST | - | - | CHANN_ACT | CHANN_ENB

- CHANN_ENB: Channel Enable Status

  Value | Name | Description
  --- | --- | ---
  0 | - | if cleared, the DMA channel no longer transfers data, and may load the next descriptor if the UOTGHS_DEVDMACONTROLx.LDNXT_DSC bit is set.
  1 | - | if set, the DMA channel is currently enabled and transfers data upon request.

- CHANN_ACT: Channel Active Status

  Value | Name | Description
  --- | --- | ---
  0 | - | the DMA channel is no longer trying to source the packet data.
  1 | - | the DMA channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel.

- END_TR_ST: End of Channel Transfer Status

  Value | Name | Description
  --- | --- | ---
  0 | - | cleared automatically when read by software.
  1 | - | set by hardware when the last packet transfer is complete, if the UOTGHS device has ended the transfer.

- END_BF_ST: End of Channel Buffer Status

  Value | Name | Description
  --- | --- | ---
  0 | - | cleared automatically when read by software.
  1 | - | set by hardware when the BUFF_COUNT count-down reaches zero.

- DESC_LDST: Descriptor Loaded Status

  Value | Name | Description
  --- | --- | ---
  0 | - | cleared automatically when read by software.
  1 | - | set by hardware when a descriptor has been loaded from the system bus.

- BUFF_COUNT: Buffer Byte Count

-

#### UOTGHS Device DMA Channel Next Descriptor Address Register (n = 2)

Name: UOTGHS_DEVDMANXTDSC2

Access: read-write

Address: 0x400AC320

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
NXT_DSC_ADD
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NXT_DSC_ADD
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NXT_DSC_ADD
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NXT_DSC_ADD

- NXT_DSC_ADD: Next Descriptor Address

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

#### UOTGHS Device DMA Channel Address Register (n = 2)

Name: UOTGHS_DEVDMAADDRESS2

Access: read-write

Address: 0x400AC324

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
BUFF_ADD
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
BUFF_ADD
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
BUFF_ADD
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
BUFF_ADD

- BUFF_ADD: Buffer Address

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

#### UOTGHS Device DMA Channel Control Register (n = 2)

Name: UOTGHS_DEVDMACONTROL2

Access: read-write

Address: 0x400AC328

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
BUFF_LENGTH
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
BUFF_LENGTH
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
BURST_LCK | DESC_LD_IT | END_BUFFIT | END_TR_IT | END_B_EN | END_TR_EN | LDNXT_DSC | CHANN_ENB

- CHANN_ENB: Channel Enable Command

-

- LDNXT_DSC: Load Next Channel Transfer Descriptor Enable Command

-

- END_TR_EN: End of Transfer Enable Control

  Value | Name | Description
  --- | --- | ---
  0 | - | USB end of transfer is ignored.
  1 | - | UOTGHS device can put an end to the current buffer transfer.

- END_B_EN: End of Buffer Enable Control

  Value | Name | Description
  --- | --- | ---
  0 | - | DMA Buffer End has no impact on USB packet transfer.
  1 | - | the endpoint can validate the packet (according to the values programmed in the UOTGHS_DEVEPTCFGx.AUTOSW field, and in the UOTGHS_DEVEPTIERx.SHORTPACKETES field) at DMA Buffer End, i.e. when the UOTGHS_DEVDMASTATUS.BUFF_COUNT reaches 0.

- END_TR_IT: End of Transfer Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | UOTGHS device initiated buffer transfer completion will not trigger any interrupt at UOTGHS_DEVDMASTATUSx.END_TR_ST rising.
  1 | - | an interrupt is sent after the buffer transfer is complete, if the UOTGHS device has ended the buffer transfer.

- END_BUFFIT: End of Buffer Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | UOTGHS_DEVDMA_STATUSx.END_BF_ST rising will not trigger any interrupt.
  1 | - | an interrupt is generated when the UOTGHS_HSTDMASTATUSx.BUFF_COUNT reaches zero.

- DESC_LD_IT: Descriptor Loaded Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | UOTGHS_DEVDMASTATUSx.DESC_LDST rising will not trigger any interrupt.
  1 | - | an interrupt is generated when a descriptor has been loaded from the bus.

- BURST_LCK: Burst Lock Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | the DMA never locks bus access.
  1 | - | USB packets AHB data bursts are locked for maximum optimization of the bus bandwidth usage and maximization of fly-by AHB burst duration.

- BUFF_LENGTH: Buffer Byte Length (Write-only)

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

#### UOTGHS Device DMA Channel Status Register (n = 2)

Name: UOTGHS_DEVDMASTATUS2

Access: read-write

Address: 0x400AC32C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
BUFF_COUNT
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
BUFF_COUNT
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | DESC_LDST | END_BF_ST | END_TR_ST | - | - | CHANN_ACT | CHANN_ENB

- CHANN_ENB: Channel Enable Status

  Value | Name | Description
  --- | --- | ---
  0 | - | if cleared, the DMA channel no longer transfers data, and may load the next descriptor if the UOTGHS_DEVDMACONTROLx.LDNXT_DSC bit is set.
  1 | - | if set, the DMA channel is currently enabled and transfers data upon request.

- CHANN_ACT: Channel Active Status

  Value | Name | Description
  --- | --- | ---
  0 | - | the DMA channel is no longer trying to source the packet data.
  1 | - | the DMA channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel.

- END_TR_ST: End of Channel Transfer Status

  Value | Name | Description
  --- | --- | ---
  0 | - | cleared automatically when read by software.
  1 | - | set by hardware when the last packet transfer is complete, if the UOTGHS device has ended the transfer.

- END_BF_ST: End of Channel Buffer Status

  Value | Name | Description
  --- | --- | ---
  0 | - | cleared automatically when read by software.
  1 | - | set by hardware when the BUFF_COUNT count-down reaches zero.

- DESC_LDST: Descriptor Loaded Status

  Value | Name | Description
  --- | --- | ---
  0 | - | cleared automatically when read by software.
  1 | - | set by hardware when a descriptor has been loaded from the system bus.

- BUFF_COUNT: Buffer Byte Count

-

#### UOTGHS Device DMA Channel Next Descriptor Address Register (n = 3)

Name: UOTGHS_DEVDMANXTDSC3

Access: read-write

Address: 0x400AC330

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
NXT_DSC_ADD
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NXT_DSC_ADD
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NXT_DSC_ADD
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NXT_DSC_ADD

- NXT_DSC_ADD: Next Descriptor Address

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

#### UOTGHS Device DMA Channel Address Register (n = 3)

Name: UOTGHS_DEVDMAADDRESS3

Access: read-write

Address: 0x400AC334

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
BUFF_ADD
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
BUFF_ADD
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
BUFF_ADD
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
BUFF_ADD

- BUFF_ADD: Buffer Address

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

#### UOTGHS Device DMA Channel Control Register (n = 3)

Name: UOTGHS_DEVDMACONTROL3

Access: read-write

Address: 0x400AC338

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
BUFF_LENGTH
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
BUFF_LENGTH
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
BURST_LCK | DESC_LD_IT | END_BUFFIT | END_TR_IT | END_B_EN | END_TR_EN | LDNXT_DSC | CHANN_ENB

- CHANN_ENB: Channel Enable Command

-

- LDNXT_DSC: Load Next Channel Transfer Descriptor Enable Command

-

- END_TR_EN: End of Transfer Enable Control

  Value | Name | Description
  --- | --- | ---
  0 | - | USB end of transfer is ignored.
  1 | - | UOTGHS device can put an end to the current buffer transfer.

- END_B_EN: End of Buffer Enable Control

  Value | Name | Description
  --- | --- | ---
  0 | - | DMA Buffer End has no impact on USB packet transfer.
  1 | - | the endpoint can validate the packet (according to the values programmed in the UOTGHS_DEVEPTCFGx.AUTOSW field, and in the UOTGHS_DEVEPTIERx.SHORTPACKETES field) at DMA Buffer End, i.e. when the UOTGHS_DEVDMASTATUS.BUFF_COUNT reaches 0.

- END_TR_IT: End of Transfer Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | UOTGHS device initiated buffer transfer completion will not trigger any interrupt at UOTGHS_DEVDMASTATUSx.END_TR_ST rising.
  1 | - | an interrupt is sent after the buffer transfer is complete, if the UOTGHS device has ended the buffer transfer.

- END_BUFFIT: End of Buffer Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | UOTGHS_DEVDMA_STATUSx.END_BF_ST rising will not trigger any interrupt.
  1 | - | an interrupt is generated when the UOTGHS_HSTDMASTATUSx.BUFF_COUNT reaches zero.

- DESC_LD_IT: Descriptor Loaded Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | UOTGHS_DEVDMASTATUSx.DESC_LDST rising will not trigger any interrupt.
  1 | - | an interrupt is generated when a descriptor has been loaded from the bus.

- BURST_LCK: Burst Lock Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | the DMA never locks bus access.
  1 | - | USB packets AHB data bursts are locked for maximum optimization of the bus bandwidth usage and maximization of fly-by AHB burst duration.

- BUFF_LENGTH: Buffer Byte Length (Write-only)

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

#### UOTGHS Device DMA Channel Status Register (n = 3)

Name: UOTGHS_DEVDMASTATUS3

Access: read-write

Address: 0x400AC33C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
BUFF_COUNT
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
BUFF_COUNT
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | DESC_LDST | END_BF_ST | END_TR_ST | - | - | CHANN_ACT | CHANN_ENB

- CHANN_ENB: Channel Enable Status

  Value | Name | Description
  --- | --- | ---
  0 | - | if cleared, the DMA channel no longer transfers data, and may load the next descriptor if the UOTGHS_DEVDMACONTROLx.LDNXT_DSC bit is set.
  1 | - | if set, the DMA channel is currently enabled and transfers data upon request.

- CHANN_ACT: Channel Active Status

  Value | Name | Description
  --- | --- | ---
  0 | - | the DMA channel is no longer trying to source the packet data.
  1 | - | the DMA channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel.

- END_TR_ST: End of Channel Transfer Status

  Value | Name | Description
  --- | --- | ---
  0 | - | cleared automatically when read by software.
  1 | - | set by hardware when the last packet transfer is complete, if the UOTGHS device has ended the transfer.

- END_BF_ST: End of Channel Buffer Status

  Value | Name | Description
  --- | --- | ---
  0 | - | cleared automatically when read by software.
  1 | - | set by hardware when the BUFF_COUNT count-down reaches zero.

- DESC_LDST: Descriptor Loaded Status

  Value | Name | Description
  --- | --- | ---
  0 | - | cleared automatically when read by software.
  1 | - | set by hardware when a descriptor has been loaded from the system bus.

- BUFF_COUNT: Buffer Byte Count

-

#### UOTGHS Device DMA Channel Next Descriptor Address Register (n = 4)

Name: UOTGHS_DEVDMANXTDSC4

Access: read-write

Address: 0x400AC340

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
NXT_DSC_ADD
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NXT_DSC_ADD
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NXT_DSC_ADD
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NXT_DSC_ADD

- NXT_DSC_ADD: Next Descriptor Address

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

#### UOTGHS Device DMA Channel Address Register (n = 4)

Name: UOTGHS_DEVDMAADDRESS4

Access: read-write

Address: 0x400AC344

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
BUFF_ADD
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
BUFF_ADD
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
BUFF_ADD
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
BUFF_ADD

- BUFF_ADD: Buffer Address

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

#### UOTGHS Device DMA Channel Control Register (n = 4)

Name: UOTGHS_DEVDMACONTROL4

Access: read-write

Address: 0x400AC348

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
BUFF_LENGTH
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
BUFF_LENGTH
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
BURST_LCK | DESC_LD_IT | END_BUFFIT | END_TR_IT | END_B_EN | END_TR_EN | LDNXT_DSC | CHANN_ENB

- CHANN_ENB: Channel Enable Command

-

- LDNXT_DSC: Load Next Channel Transfer Descriptor Enable Command

-

- END_TR_EN: End of Transfer Enable Control

  Value | Name | Description
  --- | --- | ---
  0 | - | USB end of transfer is ignored.
  1 | - | UOTGHS device can put an end to the current buffer transfer.

- END_B_EN: End of Buffer Enable Control

  Value | Name | Description
  --- | --- | ---
  0 | - | DMA Buffer End has no impact on USB packet transfer.
  1 | - | the endpoint can validate the packet (according to the values programmed in the UOTGHS_DEVEPTCFGx.AUTOSW field, and in the UOTGHS_DEVEPTIERx.SHORTPACKETES field) at DMA Buffer End, i.e. when the UOTGHS_DEVDMASTATUS.BUFF_COUNT reaches 0.

- END_TR_IT: End of Transfer Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | UOTGHS device initiated buffer transfer completion will not trigger any interrupt at UOTGHS_DEVDMASTATUSx.END_TR_ST rising.
  1 | - | an interrupt is sent after the buffer transfer is complete, if the UOTGHS device has ended the buffer transfer.

- END_BUFFIT: End of Buffer Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | UOTGHS_DEVDMA_STATUSx.END_BF_ST rising will not trigger any interrupt.
  1 | - | an interrupt is generated when the UOTGHS_HSTDMASTATUSx.BUFF_COUNT reaches zero.

- DESC_LD_IT: Descriptor Loaded Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | UOTGHS_DEVDMASTATUSx.DESC_LDST rising will not trigger any interrupt.
  1 | - | an interrupt is generated when a descriptor has been loaded from the bus.

- BURST_LCK: Burst Lock Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | the DMA never locks bus access.
  1 | - | USB packets AHB data bursts are locked for maximum optimization of the bus bandwidth usage and maximization of fly-by AHB burst duration.

- BUFF_LENGTH: Buffer Byte Length (Write-only)

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

#### UOTGHS Device DMA Channel Status Register (n = 4)

Name: UOTGHS_DEVDMASTATUS4

Access: read-write

Address: 0x400AC34C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
BUFF_COUNT
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
BUFF_COUNT
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | DESC_LDST | END_BF_ST | END_TR_ST | - | - | CHANN_ACT | CHANN_ENB

- CHANN_ENB: Channel Enable Status

  Value | Name | Description
  --- | --- | ---
  0 | - | if cleared, the DMA channel no longer transfers data, and may load the next descriptor if the UOTGHS_DEVDMACONTROLx.LDNXT_DSC bit is set.
  1 | - | if set, the DMA channel is currently enabled and transfers data upon request.

- CHANN_ACT: Channel Active Status

  Value | Name | Description
  --- | --- | ---
  0 | - | the DMA channel is no longer trying to source the packet data.
  1 | - | the DMA channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel.

- END_TR_ST: End of Channel Transfer Status

  Value | Name | Description
  --- | --- | ---
  0 | - | cleared automatically when read by software.
  1 | - | set by hardware when the last packet transfer is complete, if the UOTGHS device has ended the transfer.

- END_BF_ST: End of Channel Buffer Status

  Value | Name | Description
  --- | --- | ---
  0 | - | cleared automatically when read by software.
  1 | - | set by hardware when the BUFF_COUNT count-down reaches zero.

- DESC_LDST: Descriptor Loaded Status

  Value | Name | Description
  --- | --- | ---
  0 | - | cleared automatically when read by software.
  1 | - | set by hardware when a descriptor has been loaded from the system bus.

- BUFF_COUNT: Buffer Byte Count

-

#### UOTGHS Device DMA Channel Next Descriptor Address Register (n = 5)

Name: UOTGHS_DEVDMANXTDSC5

Access: read-write

Address: 0x400AC350

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
NXT_DSC_ADD
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NXT_DSC_ADD
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NXT_DSC_ADD
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NXT_DSC_ADD

- NXT_DSC_ADD: Next Descriptor Address

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

#### UOTGHS Device DMA Channel Address Register (n = 5)

Name: UOTGHS_DEVDMAADDRESS5

Access: read-write

Address: 0x400AC354

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
BUFF_ADD
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
BUFF_ADD
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
BUFF_ADD
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
BUFF_ADD

- BUFF_ADD: Buffer Address

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

#### UOTGHS Device DMA Channel Control Register (n = 5)

Name: UOTGHS_DEVDMACONTROL5

Access: read-write

Address: 0x400AC358

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
BUFF_LENGTH
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
BUFF_LENGTH
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
BURST_LCK | DESC_LD_IT | END_BUFFIT | END_TR_IT | END_B_EN | END_TR_EN | LDNXT_DSC | CHANN_ENB

- CHANN_ENB: Channel Enable Command

-

- LDNXT_DSC: Load Next Channel Transfer Descriptor Enable Command

-

- END_TR_EN: End of Transfer Enable Control

  Value | Name | Description
  --- | --- | ---
  0 | - | USB end of transfer is ignored.
  1 | - | UOTGHS device can put an end to the current buffer transfer.

- END_B_EN: End of Buffer Enable Control

  Value | Name | Description
  --- | --- | ---
  0 | - | DMA Buffer End has no impact on USB packet transfer.
  1 | - | the endpoint can validate the packet (according to the values programmed in the UOTGHS_DEVEPTCFGx.AUTOSW field, and in the UOTGHS_DEVEPTIERx.SHORTPACKETES field) at DMA Buffer End, i.e. when the UOTGHS_DEVDMASTATUS.BUFF_COUNT reaches 0.

- END_TR_IT: End of Transfer Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | UOTGHS device initiated buffer transfer completion will not trigger any interrupt at UOTGHS_DEVDMASTATUSx.END_TR_ST rising.
  1 | - | an interrupt is sent after the buffer transfer is complete, if the UOTGHS device has ended the buffer transfer.

- END_BUFFIT: End of Buffer Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | UOTGHS_DEVDMA_STATUSx.END_BF_ST rising will not trigger any interrupt.
  1 | - | an interrupt is generated when the UOTGHS_HSTDMASTATUSx.BUFF_COUNT reaches zero.

- DESC_LD_IT: Descriptor Loaded Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | UOTGHS_DEVDMASTATUSx.DESC_LDST rising will not trigger any interrupt.
  1 | - | an interrupt is generated when a descriptor has been loaded from the bus.

- BURST_LCK: Burst Lock Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | the DMA never locks bus access.
  1 | - | USB packets AHB data bursts are locked for maximum optimization of the bus bandwidth usage and maximization of fly-by AHB burst duration.

- BUFF_LENGTH: Buffer Byte Length (Write-only)

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

#### UOTGHS Device DMA Channel Status Register (n = 5)

Name: UOTGHS_DEVDMASTATUS5

Access: read-write

Address: 0x400AC35C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
BUFF_COUNT
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
BUFF_COUNT
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | DESC_LDST | END_BF_ST | END_TR_ST | - | - | CHANN_ACT | CHANN_ENB

- CHANN_ENB: Channel Enable Status

  Value | Name | Description
  --- | --- | ---
  0 | - | if cleared, the DMA channel no longer transfers data, and may load the next descriptor if the UOTGHS_DEVDMACONTROLx.LDNXT_DSC bit is set.
  1 | - | if set, the DMA channel is currently enabled and transfers data upon request.

- CHANN_ACT: Channel Active Status

  Value | Name | Description
  --- | --- | ---
  0 | - | the DMA channel is no longer trying to source the packet data.
  1 | - | the DMA channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel.

- END_TR_ST: End of Channel Transfer Status

  Value | Name | Description
  --- | --- | ---
  0 | - | cleared automatically when read by software.
  1 | - | set by hardware when the last packet transfer is complete, if the UOTGHS device has ended the transfer.

- END_BF_ST: End of Channel Buffer Status

  Value | Name | Description
  --- | --- | ---
  0 | - | cleared automatically when read by software.
  1 | - | set by hardware when the BUFF_COUNT count-down reaches zero.

- DESC_LDST: Descriptor Loaded Status

  Value | Name | Description
  --- | --- | ---
  0 | - | cleared automatically when read by software.
  1 | - | set by hardware when a descriptor has been loaded from the system bus.

- BUFF_COUNT: Buffer Byte Count

-

#### UOTGHS Device DMA Channel Next Descriptor Address Register (n = 6)

Name: UOTGHS_DEVDMANXTDSC6

Access: read-write

Address: 0x400AC360

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
NXT_DSC_ADD
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NXT_DSC_ADD
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NXT_DSC_ADD
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NXT_DSC_ADD

- NXT_DSC_ADD: Next Descriptor Address

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

#### UOTGHS Device DMA Channel Address Register (n = 6)

Name: UOTGHS_DEVDMAADDRESS6

Access: read-write

Address: 0x400AC364

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
BUFF_ADD
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
BUFF_ADD
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
BUFF_ADD
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
BUFF_ADD

- BUFF_ADD: Buffer Address

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

#### UOTGHS Device DMA Channel Control Register (n = 6)

Name: UOTGHS_DEVDMACONTROL6

Access: read-write

Address: 0x400AC368

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
BUFF_LENGTH
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
BUFF_LENGTH
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
BURST_LCK | DESC_LD_IT | END_BUFFIT | END_TR_IT | END_B_EN | END_TR_EN | LDNXT_DSC | CHANN_ENB

- CHANN_ENB: Channel Enable Command

-

- LDNXT_DSC: Load Next Channel Transfer Descriptor Enable Command

-

- END_TR_EN: End of Transfer Enable Control

  Value | Name | Description
  --- | --- | ---
  0 | - | USB end of transfer is ignored.
  1 | - | UOTGHS device can put an end to the current buffer transfer.

- END_B_EN: End of Buffer Enable Control

  Value | Name | Description
  --- | --- | ---
  0 | - | DMA Buffer End has no impact on USB packet transfer.
  1 | - | the endpoint can validate the packet (according to the values programmed in the UOTGHS_DEVEPTCFGx.AUTOSW field, and in the UOTGHS_DEVEPTIERx.SHORTPACKETES field) at DMA Buffer End, i.e. when the UOTGHS_DEVDMASTATUS.BUFF_COUNT reaches 0.

- END_TR_IT: End of Transfer Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | UOTGHS device initiated buffer transfer completion will not trigger any interrupt at UOTGHS_DEVDMASTATUSx.END_TR_ST rising.
  1 | - | an interrupt is sent after the buffer transfer is complete, if the UOTGHS device has ended the buffer transfer.

- END_BUFFIT: End of Buffer Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | UOTGHS_DEVDMA_STATUSx.END_BF_ST rising will not trigger any interrupt.
  1 | - | an interrupt is generated when the UOTGHS_HSTDMASTATUSx.BUFF_COUNT reaches zero.

- DESC_LD_IT: Descriptor Loaded Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | UOTGHS_DEVDMASTATUSx.DESC_LDST rising will not trigger any interrupt.
  1 | - | an interrupt is generated when a descriptor has been loaded from the bus.

- BURST_LCK: Burst Lock Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | the DMA never locks bus access.
  1 | - | USB packets AHB data bursts are locked for maximum optimization of the bus bandwidth usage and maximization of fly-by AHB burst duration.

- BUFF_LENGTH: Buffer Byte Length (Write-only)

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

#### UOTGHS Device DMA Channel Status Register (n = 6)

Name: UOTGHS_DEVDMASTATUS6

Access: read-write

Address: 0x400AC36C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
BUFF_COUNT
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
BUFF_COUNT
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | DESC_LDST | END_BF_ST | END_TR_ST | - | - | CHANN_ACT | CHANN_ENB

- CHANN_ENB: Channel Enable Status

  Value | Name | Description
  --- | --- | ---
  0 | - | if cleared, the DMA channel no longer transfers data, and may load the next descriptor if the UOTGHS_DEVDMACONTROLx.LDNXT_DSC bit is set.
  1 | - | if set, the DMA channel is currently enabled and transfers data upon request.

- CHANN_ACT: Channel Active Status

  Value | Name | Description
  --- | --- | ---
  0 | - | the DMA channel is no longer trying to source the packet data.
  1 | - | the DMA channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel.

- END_TR_ST: End of Channel Transfer Status

  Value | Name | Description
  --- | --- | ---
  0 | - | cleared automatically when read by software.
  1 | - | set by hardware when the last packet transfer is complete, if the UOTGHS device has ended the transfer.

- END_BF_ST: End of Channel Buffer Status

  Value | Name | Description
  --- | --- | ---
  0 | - | cleared automatically when read by software.
  1 | - | set by hardware when the BUFF_COUNT count-down reaches zero.

- DESC_LDST: Descriptor Loaded Status

  Value | Name | Description
  --- | --- | ---
  0 | - | cleared automatically when read by software.
  1 | - | set by hardware when a descriptor has been loaded from the system bus.

- BUFF_COUNT: Buffer Byte Count

-

#### UOTGHS Device DMA Channel Next Descriptor Address Register (n = 7)

Name: UOTGHS_DEVDMANXTDSC7

Access: read-write

Address: 0x400AC370

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
NXT_DSC_ADD
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NXT_DSC_ADD
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NXT_DSC_ADD
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NXT_DSC_ADD

- NXT_DSC_ADD: Next Descriptor Address

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

#### UOTGHS Device DMA Channel Address Register (n = 7)

Name: UOTGHS_DEVDMAADDRESS7

Access: read-write

Address: 0x400AC374

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
BUFF_ADD
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
BUFF_ADD
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
BUFF_ADD
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
BUFF_ADD

- BUFF_ADD: Buffer Address

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

#### UOTGHS Device DMA Channel Control Register (n = 7)

Name: UOTGHS_DEVDMACONTROL7

Access: read-write

Address: 0x400AC378

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
BUFF_LENGTH
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
BUFF_LENGTH
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
BURST_LCK | DESC_LD_IT | END_BUFFIT | END_TR_IT | END_B_EN | END_TR_EN | LDNXT_DSC | CHANN_ENB

- CHANN_ENB: Channel Enable Command

-

- LDNXT_DSC: Load Next Channel Transfer Descriptor Enable Command

-

- END_TR_EN: End of Transfer Enable Control

  Value | Name | Description
  --- | --- | ---
  0 | - | USB end of transfer is ignored.
  1 | - | UOTGHS device can put an end to the current buffer transfer.

- END_B_EN: End of Buffer Enable Control

  Value | Name | Description
  --- | --- | ---
  0 | - | DMA Buffer End has no impact on USB packet transfer.
  1 | - | the endpoint can validate the packet (according to the values programmed in the UOTGHS_DEVEPTCFGx.AUTOSW field, and in the UOTGHS_DEVEPTIERx.SHORTPACKETES field) at DMA Buffer End, i.e. when the UOTGHS_DEVDMASTATUS.BUFF_COUNT reaches 0.

- END_TR_IT: End of Transfer Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | UOTGHS device initiated buffer transfer completion will not trigger any interrupt at UOTGHS_DEVDMASTATUSx.END_TR_ST rising.
  1 | - | an interrupt is sent after the buffer transfer is complete, if the UOTGHS device has ended the buffer transfer.

- END_BUFFIT: End of Buffer Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | UOTGHS_DEVDMA_STATUSx.END_BF_ST rising will not trigger any interrupt.
  1 | - | an interrupt is generated when the UOTGHS_HSTDMASTATUSx.BUFF_COUNT reaches zero.

- DESC_LD_IT: Descriptor Loaded Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | UOTGHS_DEVDMASTATUSx.DESC_LDST rising will not trigger any interrupt.
  1 | - | an interrupt is generated when a descriptor has been loaded from the bus.

- BURST_LCK: Burst Lock Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | the DMA never locks bus access.
  1 | - | USB packets AHB data bursts are locked for maximum optimization of the bus bandwidth usage and maximization of fly-by AHB burst duration.

- BUFF_LENGTH: Buffer Byte Length (Write-only)

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

#### UOTGHS Device DMA Channel Status Register (n = 7)

Name: UOTGHS_DEVDMASTATUS7

Access: read-write

Address: 0x400AC37C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
BUFF_COUNT
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
BUFF_COUNT
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | DESC_LDST | END_BF_ST | END_TR_ST | - | - | CHANN_ACT | CHANN_ENB

- CHANN_ENB: Channel Enable Status

  Value | Name | Description
  --- | --- | ---
  0 | - | if cleared, the DMA channel no longer transfers data, and may load the next descriptor if the UOTGHS_DEVDMACONTROLx.LDNXT_DSC bit is set.
  1 | - | if set, the DMA channel is currently enabled and transfers data upon request.

- CHANN_ACT: Channel Active Status

  Value | Name | Description
  --- | --- | ---
  0 | - | the DMA channel is no longer trying to source the packet data.
  1 | - | the DMA channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel.

- END_TR_ST: End of Channel Transfer Status

  Value | Name | Description
  --- | --- | ---
  0 | - | cleared automatically when read by software.
  1 | - | set by hardware when the last packet transfer is complete, if the UOTGHS device has ended the transfer.

- END_BF_ST: End of Channel Buffer Status

  Value | Name | Description
  --- | --- | ---
  0 | - | cleared automatically when read by software.
  1 | - | set by hardware when the BUFF_COUNT count-down reaches zero.

- DESC_LDST: Descriptor Loaded Status

  Value | Name | Description
  --- | --- | ---
  0 | - | cleared automatically when read by software.
  1 | - | set by hardware when a descriptor has been loaded from the system bus.

- BUFF_COUNT: Buffer Byte Count

-

#### UOTGHS Host General Control Register

Name: UOTGHS_HSTCTRL

Access: read-write

Address: 0x400AC400

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | SPDCONF | - | RESUME | RESET | SOFE
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | -

- SOFE: Start of Frame Generation Enable

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

- RESET: Send USB Reset

-

- RESUME: Send USB Resume

-

- SPDCONF: Mode Configuration

  Value | Name | Description
  --- | --- | ---
  0x0 | NORMAL | The host starts in full-speed mode and performs a high-speed reset to switch to the high-speed mode if the downstream peripheral is high-speed capable.
  0x1 | LOW_POWER | For a better consumption, if high-speed is not needed.
  0x2 | HIGH_SPEED | Forced high speed.
  0x3 | FORCED_FS | The host remains to full-speed mode whatever the peripheral speed capability.

#### UOTGHS Host Global Interrupt Status Register

Name: UOTGHS_HSTISR

Access: read-only

Address: 0x400AC404

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | DMA_6 | DMA_5 | DMA_4 | DMA_3 | DMA_2 | DMA_1 | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | PEP_9 | PEP_8
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
PEP_7 | PEP_6 | PEP_5 | PEP_4 | PEP_3 | PEP_2 | PEP_1 | PEP_0
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | HWUPI | HSOFI | RXRSMI | RSMEDI | RSTI | DDISCI | DCONNI

- DCONNI: Device Connection Interrupt

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

- DDISCI: Device Disconnection Interrupt

-

- RSTI: USB Reset Sent Interrupt

-

- RSMEDI: Downstream Resume Sent Interrupt

-

- RXRSMI: Upstream Resume Received Interrupt

-

- HSOFI: Host Start of Frame Interrupt

-

- HWUPI: Host Wake-Up Interrupt

-

- PEP_0: Pipe 0 Interrupt

-

- PEP_1: Pipe 1 Interrupt

-

- PEP_2: Pipe 2 Interrupt

-

- PEP_3: Pipe 3 Interrupt

-

- PEP_4: Pipe 4 Interrupt

-

- PEP_5: Pipe 5 Interrupt

-

- PEP_6: Pipe 6 Interrupt

-

- PEP_7: Pipe 7 Interrupt

-

- PEP_8: Pipe 8 Interrupt

-

- PEP_9: Pipe 9 Interrupt

-

- DMA_1: DMA Channel 1 Interrupt

-

- DMA_2: DMA Channel 2 Interrupt

-

- DMA_3: DMA Channel 3 Interrupt

-

- DMA_4: DMA Channel 4 Interrupt

-

- DMA_5: DMA Channel 5 Interrupt

-

- DMA_6: DMA Channel 6 Interrupt

-

#### UOTGHS Host Global Interrupt Clear Register

Name: UOTGHS_HSTICR

Access: write-only

Address: 0x400AC408

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | HWUPIC | HSOFIC | RXRSMIC | RSMEDIC | RSTIC | DDISCIC | DCONNIC

- DCONNIC: Device Connection Interrupt Clear

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

- DDISCIC: Device Disconnection Interrupt Clear

-

- RSTIC: USB Reset Sent Interrupt Clear

-

- RSMEDIC: Downstream Resume Sent Interrupt Clear

-

- RXRSMIC: Upstream Resume Received Interrupt Clear

-

- HSOFIC: Host Start of Frame Interrupt Clear

-

- HWUPIC: Host Wake-Up Interrupt Clear

-

#### UOTGHS Host Global Interrupt Set Register

Name: UOTGHS_HSTIFR

Access: write-only

Address: 0x400AC40C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | DMA_6 | DMA_5 | DMA_4 | DMA_3 | DMA_2 | DMA_1 | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | HWUPIS | HSOFIS | RXRSMIS | RSMEDIS | RSTIS | DDISCIS | DCONNIS

- DCONNIS: Device Connection Interrupt Set

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

- DDISCIS: Device Disconnection Interrupt Set

-

- RSTIS: USB Reset Sent Interrupt Set

-

- RSMEDIS: Downstream Resume Sent Interrupt Set

-

- RXRSMIS: Upstream Resume Received Interrupt Set

-

- HSOFIS: Host Start of Frame Interrupt Set

-

- HWUPIS: Host Wake-Up Interrupt Set

-

- DMA_1: DMA Channel 1 Interrupt Set

-

- DMA_2: DMA Channel 2 Interrupt Set

-

- DMA_3: DMA Channel 3 Interrupt Set

-

- DMA_4: DMA Channel 4 Interrupt Set

-

- DMA_5: DMA Channel 5 Interrupt Set

-

- DMA_6: DMA Channel 6 Interrupt Set

-

#### UOTGHS Host Global Interrupt Mask Register

Name: UOTGHS_HSTIMR

Access: read-only

Address: 0x400AC410

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | DMA_6 | DMA_5 | DMA_4 | DMA_3 | DMA_2 | DMA_1 | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | PEP_9 | PEP_8
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
PEP_7 | PEP_6 | PEP_5 | PEP_4 | PEP_3 | PEP_2 | PEP_1 | PEP_0
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | HWUPIE | HSOFIE | RXRSMIE | RSMEDIE | RSTIE | DDISCIE | DCONNIE

- DCONNIE: Device Connection Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

- DDISCIE: Device Disconnection Interrupt Enable

-

- RSTIE: USB Reset Sent Interrupt Enable

-

- RSMEDIE: Downstream Resume Sent Interrupt Enable

-

- RXRSMIE: Upstream Resume Received Interrupt Enable

-

- HSOFIE: Host Start of Frame Interrupt Enable

-

- HWUPIE: Host Wake-Up Interrupt Enable

-

- PEP_0: Pipe 0 Interrupt Enable

-

- PEP_1: Pipe 1 Interrupt Enable

-

- PEP_2: Pipe 2 Interrupt Enable

-

- PEP_3: Pipe 3 Interrupt Enable

-

- PEP_4: Pipe 4 Interrupt Enable

-

- PEP_5: Pipe 5 Interrupt Enable

-

- PEP_6: Pipe 6 Interrupt Enable

-

- PEP_7: Pipe 7 Interrupt Enable

-

- PEP_8: Pipe 8 Interrupt Enable

-

- PEP_9: Pipe 9 Interrupt Enable

-

- DMA_1: DMA Channel 1 Interrupt Enable

-

- DMA_2: DMA Channel 2 Interrupt Enable

-

- DMA_3: DMA Channel 3 Interrupt Enable

-

- DMA_4: DMA Channel 4 Interrupt Enable

-

- DMA_5: DMA Channel 5 Interrupt Enable

-

- DMA_6: DMA Channel 6 Interrupt Enable

-

#### UOTGHS Host Global Interrupt Disable Register

Name: UOTGHS_HSTIDR

Access: write-only

Address: 0x400AC414

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | DMA_6 | DMA_5 | DMA_4 | DMA_3 | DMA_2 | DMA_1 | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | PEP_9 | PEP_8
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
PEP_7 | PEP_6 | PEP_5 | PEP_4 | PEP_3 | PEP_2 | PEP_1 | PEP_0
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | HWUPIEC | HSOFIEC | RXRSMIEC | RSMEDIEC | RSTIEC | DDISCIEC | DCONNIEC

- DCONNIEC: Device Connection Interrupt Disable

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

- DDISCIEC: Device Disconnection Interrupt Disable

-

- RSTIEC: USB Reset Sent Interrupt Disable

-

- RSMEDIEC: Downstream Resume Sent Interrupt Disable

-

- RXRSMIEC: Upstream Resume Received Interrupt Disable

-

- HSOFIEC: Host Start of Frame Interrupt Disable

-

- HWUPIEC: Host Wake-Up Interrupt Disable

-

- PEP_0: Pipe 0 Interrupt Disable

-

- PEP_1: Pipe 1 Interrupt Disable

-

- PEP_2: Pipe 2 Interrupt Disable

-

- PEP_3: Pipe 3 Interrupt Disable

-

- PEP_4: Pipe 4 Interrupt Disable

-

- PEP_5: Pipe 5 Interrupt Disable

-

- PEP_6: Pipe 6 Interrupt Disable

-

- PEP_7: Pipe 7 Interrupt Disable

-

- PEP_8: Pipe 8 Interrupt Disable

-

- PEP_9: Pipe 9 Interrupt Disable

-

- DMA_1: DMA Channel 1 Interrupt Disable

-

- DMA_2: DMA Channel 2 Interrupt Disable

-

- DMA_3: DMA Channel 3 Interrupt Disable

-

- DMA_4: DMA Channel 4 Interrupt Disable

-

- DMA_5: DMA Channel 5 Interrupt Disable

-

- DMA_6: DMA Channel 6 Interrupt Disable

-

#### UOTGHS Host Global Interrupt Enable Register

Name: UOTGHS_HSTIER

Access: write-only

Address: 0x400AC418

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | DMA_6 | DMA_5 | DMA_4 | DMA_3 | DMA_2 | DMA_1 | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | PEP_9 | PEP_8
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
PEP_7 | PEP_6 | PEP_5 | PEP_4 | PEP_3 | PEP_2 | PEP_1 | PEP_0
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | HWUPIES | HSOFIES | RXRSMIES | RSMEDIES | RSTIES | DDISCIES | DCONNIES

- DCONNIES: Device Connection Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

- DDISCIES: Device Disconnection Interrupt Enable

-

- RSTIES: USB Reset Sent Interrupt Enable

-

- RSMEDIES: Downstream Resume Sent Interrupt Enable

-

- RXRSMIES: Upstream Resume Received Interrupt Enable

-

- HSOFIES: Host Start of Frame Interrupt Enable

-

- HWUPIES: Host Wake-Up Interrupt Enable

-

- PEP_0: Pipe 0 Interrupt Enable

-

- PEP_1: Pipe 1 Interrupt Enable

-

- PEP_2: Pipe 2 Interrupt Enable

-

- PEP_3: Pipe 3 Interrupt Enable

-

- PEP_4: Pipe 4 Interrupt Enable

-

- PEP_5: Pipe 5 Interrupt Enable

-

- PEP_6: Pipe 6 Interrupt Enable

-

- PEP_7: Pipe 7 Interrupt Enable

-

- PEP_8: Pipe 8 Interrupt Enable

-

- PEP_9: Pipe 9 Interrupt Enable

-

- DMA_1: DMA Channel 1 Interrupt Enable

-

- DMA_2: DMA Channel 2 Interrupt Enable

-

- DMA_3: DMA Channel 3 Interrupt Enable

-

- DMA_4: DMA Channel 4 Interrupt Enable

-

- DMA_5: DMA Channel 5 Interrupt Enable

-

- DMA_6: DMA Channel 6 Interrupt Enable

-

#### UOTGHS Host Pipe Register

Name: UOTGHS_HSTPIP

Access: read-write

Address: 0x400AC41C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | PRST8
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
PRST7 | PRST6 | PRST5 | PRST4 | PRST3 | PRST2 | PRST1 | PRST0
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | PEN8
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
PEN7 | PEN6 | PEN5 | PEN4 | PEN3 | PEN2 | PEN1 | PEN0

- PEN0: Pipe 0 Enable

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

- PEN1: Pipe 1 Enable

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

- PEN2: Pipe 2 Enable

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

- PEN3: Pipe 3 Enable

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

- PEN4: Pipe 4 Enable

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

- PEN5: Pipe 5 Enable

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

- PEN6: Pipe 6 Enable

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

- PEN7: Pipe 7 Enable

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

- PEN8: Pipe 8 Enable

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

- PRST0: Pipe 0 Reset

-

- PRST1: Pipe 1 Reset

-

- PRST2: Pipe 2 Reset

-

- PRST3: Pipe 3 Reset

-

- PRST4: Pipe 4 Reset

-

- PRST5: Pipe 5 Reset

-

- PRST6: Pipe 6 Reset

-

- PRST7: Pipe 7 Reset

-

- PRST8: Pipe 8 Reset

-

#### UOTGHS Host Frame Number Register

Name: UOTGHS_HSTFNUM

Access: read-write

Address: 0x400AC420

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
FLENHIGH
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | FNUM
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
FNUM | MFNUM

- MFNUM: Micro Frame Number

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

- FNUM: Frame Number

-

- FLENHIGH: Frame Length

-

#### UOTGHS Host Address 1 Register

Name: UOTGHS_HSTADDR1

Access: read-write

Address: 0x400AC424

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | HSTADDRP3
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | HSTADDRP2
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | HSTADDRP1
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | HSTADDRP0

- HSTADDRP0: USB Host Address

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

- HSTADDRP1: USB Host Address

-

- HSTADDRP2: USB Host Address

-

- HSTADDRP3: USB Host Address

-

#### UOTGHS Host Address 2 Register

Name: UOTGHS_HSTADDR2

Access: read-write

Address: 0x400AC428

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | HSTADDRP7
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | HSTADDRP6
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | HSTADDRP5
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | HSTADDRP4

- HSTADDRP4: USB Host Address

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

- HSTADDRP5: USB Host Address

-

- HSTADDRP6: USB Host Address

-

- HSTADDRP7: USB Host Address

-

#### UOTGHS Host Address 3 Register

Name: UOTGHS_HSTADDR3

Access: read-write

Address: 0x400AC42C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | HSTADDRP9
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | HSTADDRP8

- HSTADDRP8: USB Host Address

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

- HSTADDRP9: USB Host Address

-

#### UOTGHS Host Pipe Configuration Register (n = 0)

Name: UOTGHS_HSTPIPCFG[0:9]

Access: read-write

Address: 0x400AC500

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
INTFRQ
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | PINGEN | PEPNUM
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | PTYPE | - | AUTOSW | PTOKEN
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | PSIZE | PBK | ALLOC | -

- ALLOC: Pipe Memory Allocate

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

- PBK: Pipe Banks

  Value | Name | Description
  --- | --- | ---
  0x0 | 1_BANK | Single-bank pipe
  0x1 | 2_BANK | Double-bank pipe
  0x2 | 3_BANK | Triple-bank pipe

- PSIZE: Pipe Size

  Value | Name | Description
  --- | --- | ---
  0x0 | 8_BYTE | 8 bytes
  0x1 | 16_BYTE | 16 bytes
  0x2 | 32_BYTE | 32 bytes
  0x3 | 64_BYTE | 64 bytes
  0x4 | 128_BYTE | 128 bytes
  0x5 | 256_BYTE | 256 bytes
  0x6 | 512_BYTE | 512 bytes
  0x7 | 1024_BYTE | 1024 bytes

- PTOKEN: Pipe Token

  Value | Name | Description
  --- | --- | ---
  0x0 | SETUP | SETUP
  0x1 | IN | IN
  0x2 | OUT | OUT

- AUTOSW: Automatic Switch

  Value | Name | Description
  --- | --- | ---
  0 | - | The automatic bank switching is disabled.
  1 | - | The automatic bank switching is enabled.

- PTYPE: Pipe Type

  Value | Name | Description
  --- | --- | ---
  0x0 | CTRL | Control
  0x1 | ISO | Isochronous
  0x2 | BLK | Bulk
  0x3 | INTRPT | Interrupt

- PEPNUM: Pipe Endpoint Number

-

- PINGEN: Ping Enable

-

- INTFRQ: Pipe Interrupt Request Frequency

-

- BINTERVAL: bInterval parameter for the Bulk-Out/Ping transaction

-

#### UOTGHS Host Pipe Status Register (n = 0)

Name: UOTGHS_HSTPIPISR[0:9]

Access: read-only

Address: 0x400AC530

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | PBYCT
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
PBYCT | - | CFGOK | - | RWALL
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CURRBK | NBUSYBK | - | - | DTSEQ
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
SHORTPACKETI | RXSTALLDI | OVERFI | NAKEDI | PERRI | TXSTPI | TXOUTI | RXINI

- RXINI: Received IN Data Interrupt

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

- TXOUTI: Transmitted OUT Data Interrupt

-

- TXSTPI: Transmitted SETUP Interrupt

-

- UNDERFI: Underflow Interrupt

-

- PERRI: Pipe Error Interrupt

-

- NAKEDI: NAKed Interrupt

-

- OVERFI: Overflow Interrupt

-

- RXSTALLDI: Received STALLed Interrupt

-

- CRCERRI: CRC Error Interrupt

-

- SHORTPACKETI: Short Packet Interrupt

-

- DTSEQ: Data Toggle Sequence

  Value | Name | Description
  --- | --- | ---
  0 | DATA0 | Data0 toggle sequence
  1 | DATA1 | Data1 toggle sequence

- NBUSYBK: Number of Busy Banks

  Value | Name | Description
  --- | --- | ---
  0x0 | 0_BUSY | 0 busy bank (all banks free)
  0x1 | 1_BUSY | 1 busy bank
  0x2 | 2_BUSY | 2 busy banks
  0x3 | 3_BUSY | 3 busy banks

- CURRBK: Current Bank

  Value | Name | Description
  --- | --- | ---
  0x0 | BANK0 | Current bank is bank0
  0x1 | BANK1 | Current bank is bank1
  0x2 | BANK2 | Current bank is bank2

- RWALL: Read-write Allowed

-

- CFGOK: Configuration OK Status

-

- PBYCT: Pipe Byte Count

-

#### UOTGHS Host Pipe Clear Register (n = 0)

Name: UOTGHS_HSTPIPICR[0:9]

Access: write-only

Address: 0x400AC560

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
SHORTPACKETIC | RXSTALLDIC | OVERFIC | NAKEDIC | - | TXSTPIC | TXOUTIC | RXINIC

- RXINIC: Received IN Data Interrupt Clear

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

- TXOUTIC: Transmitted OUT Data Interrupt Clear

-

- TXSTPIC: Transmitted SETUP Interrupt Clear

-

- UNDERFIC: Underflow Interrupt Clear

-

- NAKEDIC: NAKed Interrupt Clear

-

- OVERFIC: Overflow Interrupt Clear

-

- RXSTALLDIC: Received STALLed Interrupt Clear

-

- CRCERRIC: CRC Error Interrupt Clear

-

- SHORTPACKETIC: Short Packet Interrupt Clear

-

#### UOTGHS Host Pipe Set Register (n = 0)

Name: UOTGHS_HSTPIPIFR[0:9]

Access: write-only

Address: 0x400AC590

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | NBUSYBKS | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
SHORTPACKETIS | RXSTALLDIS | OVERFIS | NAKEDIS | PERRIS | TXSTPIS | TXOUTIS | RXINIS

- RXINIS: Received IN Data Interrupt Set

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

- TXOUTIS: Transmitted OUT Data Interrupt Set

-

- TXSTPIS: Transmitted SETUP Interrupt Set

-

- UNDERFIS: Underflow Interrupt Set

-

- PERRIS: Pipe Error Interrupt Set

-

- NAKEDIS: NAKed Interrupt Set

-

- OVERFIS: Overflow Interrupt Set

-

- RXSTALLDIS: Received STALLed Interrupt Set

-

- CRCERRIS: CRC Error Interrupt Set

-

- SHORTPACKETIS: Short Packet Interrupt Set

-

- NBUSYBKS: Number of Busy Banks Set

-

#### UOTGHS Host Pipe Mask Register (n = 0)

Name: UOTGHS_HSTPIPIMR[0:9]

Access: read-only

Address: 0x400AC5C0

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | RSTDT | PFREEZE | PDISHDMA
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | FIFOCON | - | NBUSYBKE | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
SHORTPACKETIE | RXSTALLDE | OVERFIE | NAKEDE | PERRE | TXSTPE | TXOUTE | RXINE

- RXINE: Received IN Data Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

- TXOUTE: Transmitted OUT Data Interrupt Enable

-

- TXSTPE: Transmitted SETUP Interrupt Enable

-

- UNDERFIE: Underflow Interrupt Enable

-

- PERRE: Pipe Error Interrupt Enable

-

- NAKEDE: NAKed Interrupt Enable

-

- OVERFIE: Overflow Interrupt Enable

-

- RXSTALLDE: Received STALLed Interrupt Enable

-

- CRCERRE: CRC Error Interrupt Enable

-

- SHORTPACKETIE: Short Packet Interrupt Enable

-

- NBUSYBKE: Number of Busy Banks Interrupt Enable

-

- FIFOCON: FIFO Control

-

- PDISHDMA: Pipe Interrupts Disable HDMA Request Enable

-

- PFREEZE: Pipe Freeze

-

- RSTDT: Reset Data Toggle

-

#### UOTGHS Host Pipe Enable Register (n = 0)

Name: UOTGHS_HSTPIPIER[0:9]

Access: write-only

Address: 0x400AC5F0

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | RSTDTS | PFREEZES | PDISHDMAS
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | NBUSYBKES | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
SHORTPACKETIES | RXSTALLDES | OVERFIES | NAKEDES | PERRES | TXSTPES | TXOUTES | RXINES

- RXINES: Received IN Data Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

- TXOUTES: Transmitted OUT Data Interrupt Enable

-

- TXSTPES: Transmitted SETUP Interrupt Enable

-

- UNDERFIES: Underflow Interrupt Enable

-

- PERRES: Pipe Error Interrupt Enable

-

- NAKEDES: NAKed Interrupt Enable

-

- OVERFIES: Overflow Interrupt Enable

-

- RXSTALLDES: Received STALLed Interrupt Enable

-

- CRCERRES: CRC Error Interrupt Enable

-

- SHORTPACKETIES: Short Packet Interrupt Enable

-

- NBUSYBKES: Number of Busy Banks Enable

-

- PDISHDMAS: Pipe Interrupts Disable HDMA Request Enable

-

- PFREEZES: Pipe Freeze Enable

-

- RSTDTS: Reset Data Toggle Enable

-

#### UOTGHS Host Pipe Disable Register (n = 0)

Name: UOTGHS_HSTPIPIDR[0:9]

Access: write-only

Address: 0x400AC620

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | PFREEZEC | PDISHDMAC
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | FIFOCONC | - | NBUSYBKEC | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
SHORTPACKETIEC | RXSTALLDEC | OVERFIEC | NAKEDEC | PERREC | TXSTPEC | TXOUTEC | RXINEC

- RXINEC: Received IN Data Interrupt Disable

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

- TXOUTEC: Transmitted OUT Data Interrupt Disable

-

- TXSTPEC: Transmitted SETUP Interrupt Disable

-

- UNDERFIEC: Underflow Interrupt Disable

-

- PERREC: Pipe Error Interrupt Disable

-

- NAKEDEC: NAKed Interrupt Disable

-

- OVERFIEC: Overflow Interrupt Disable

-

- RXSTALLDEC: Received STALLed Interrupt Disable

-

- CRCERREC: CRC Error Interrupt Disable

-

- SHORTPACKETIEC: Short Packet Interrupt Disable

-

- NBUSYBKEC: Number of Busy Banks Disable

-

- FIFOCONC: FIFO Control Disable

-

- PDISHDMAC: Pipe Interrupts Disable HDMA Request Disable

-

- PFREEZEC: Pipe Freeze Disable

-

#### UOTGHS Host Pipe IN Request Register (n = 0)

Name: UOTGHS_HSTPIPINRQ[0:9]

Access: read-write

Address: 0x400AC650

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | INMODE
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
INRQ

- INRQ: IN Request Number before Freeze

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

- INMODE: IN Request Mode

-

#### UOTGHS Host Pipe Error Register (n = 0)

Name: UOTGHS_HSTPIPERR[0:9]

Access: read-write

Address: 0x400AC680

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | COUNTER | CRC16 | TIMEOUT | PID | DATAPID | DATATGL

- DATATGL: Data Toggle Error

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

- DATAPID: Data PID Error

-

- PID: PID Error

-

- TIMEOUT: Time-Out Error

-

- CRC16: CRC16 Error

-

- COUNTER: Error Counter

-

#### UOTGHS Host DMA Channel Next Descriptor Address Register (n = 1)

Name: UOTGHS_HSTDMANXTDSC1

Access: read-write

Address: 0x400AC710

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
NXT_DSC_ADD
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NXT_DSC_ADD
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NXT_DSC_ADD
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NXT_DSC_ADD

- NXT_DSC_ADD: Next Descriptor Address

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

#### UOTGHS Host DMA Channel Address Register (n = 1)

Name: UOTGHS_HSTDMAADDRESS1

Access: read-write

Address: 0x400AC714

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
BUFF_ADD
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
BUFF_ADD
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
BUFF_ADD
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
BUFF_ADD

- BUFF_ADD: Buffer Address

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

#### UOTGHS Host DMA Channel Control Register (n = 1)

Name: UOTGHS_HSTDMACONTROL1

Access: read-write

Address: 0x400AC718

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
BUFF_LENGTH
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
BUFF_LENGTH
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
BURST_LCK | DESC_LD_IT | END_BUFFIT | END_TR_IT | END_B_EN | END_TR_EN | LDNXT_DSC | CHANN_ENB

- CHANN_ENB: Channel Enable Command

-

- LDNXT_DSC: Load Next Channel Transfer Descriptor Enable Command

-

- END_TR_EN: End of Transfer Enable (Control)

  Value | Name | Description
  --- | --- | ---
  0 | - | USB end of transfer is ignored.
  1 | - | UOTGHS device can put an end to the current buffer transfer.

- END_B_EN: End of Buffer Enable Control

  Value | Name | Description
  --- | --- | ---
  0 | - | DMA Buffer End has no impact on USB packet transfer.
  1 | - | the pipe can validate the packet (according to the values programmed in the UOTGHS_HSTPIPCFGx.AUTOSW field, and in the UOTGHS_HSTPIPIMRx.SHORTPACKETIE field) at DMA Buffer End, i.e. when UOTGHS_HSTDMASTATUS.BUFF_COUNT reaches 0.

- END_TR_IT: End of Transfer Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | UOTGHS device initiated buffer transfer completion will not trigger any interrupt at UOTGHS_HSTDMASTATUSx.END_TR_ST rising.
  1 | - | an interrupt is sent after the buffer transfer is complete, if the UOTGHS device has ended the buffer transfer.

- END_BUFFIT: End of Buffer Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | UOTGHS_HSTDMASTATUSx.END_BF_ST rising will not trigger any interrupt.
  1 | - | an interrupt is generated when UOTGHS_HSTDMASTATUSx.BUFF_COUNT reaches zero.

- DESC_LD_IT: Descriptor Loaded Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | UOTGHS_HSTDMASTATUSx.DESC_LDST rising will not trigger any interrupt.
  1 | - | an interrupt is generated when a descriptor has been loaded from the bus.

- BURST_LCK: Burst Lock Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | the DMA never locks the bus access.
  1 | - | USB packets AHB data bursts are locked for maximum optimization of the bus bandwidth usage and maximization of fly-by AHB burst duration.

- BUFF_LENGTH: Buffer Byte Length (Write-only)

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

#### UOTGHS Host DMA Channel Status Register (n = 1)

Name: UOTGHS_HSTDMASTATUS1

Access: read-write

Address: 0x400AC71C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
BUFF_COUNT
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
BUFF_COUNT
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | DESC_LDST | END_BF_ST | END_TR_ST | - | - | CHANN_ACT | CHANN_ENB

- CHANN_ENB: Channel Enable Status

  Value | Name | Description
  --- | --- | ---
  0 | - | if cleared, the DMA channel no longer transfers data, and may load the next descriptor if UOTGHS_HSTDMACONTROLx.LDNXT_DSC bit is set.
  1 | - | if set, the DMA channel is currently enabled and transfers data upon request.

- CHANN_ACT: Channel Active Status

  Value | Name | Description
  --- | --- | ---
  0 | - | the DMA channel is no longer trying to source the packet data.
  1 | - | the DMA channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel.

- END_TR_ST: End of Channel Transfer Status

  Value | Name | Description
  --- | --- | ---
  0 | - | cleared automatically when read by software.
  1 | - | set by hardware when the last packet transfer is complete, if the UOTGHS device has ended the transfer.

- END_BF_ST: End of Channel Buffer Status

  Value | Name | Description
  --- | --- | ---
  0 | - | cleared automatically when read by software.
  1 | - | set by hardware when BUFF_COUNT count-down reaches zero.

- DESC_LDST: Descriptor Loaded Status

  Value | Name | Description
  --- | --- | ---
  0 | - | cleared automatically when read by software.
  1 | - | set by hardware when a descriptor has been loaded from the system bus.

- BUFF_COUNT: Buffer Byte Count

-

#### UOTGHS Host DMA Channel Next Descriptor Address Register (n = 2)

Name: UOTGHS_HSTDMANXTDSC2

Access: read-write

Address: 0x400AC720

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
NXT_DSC_ADD
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NXT_DSC_ADD
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NXT_DSC_ADD
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NXT_DSC_ADD

- NXT_DSC_ADD: Next Descriptor Address

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

#### UOTGHS Host DMA Channel Address Register (n = 2)

Name: UOTGHS_HSTDMAADDRESS2

Access: read-write

Address: 0x400AC724

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
BUFF_ADD
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
BUFF_ADD
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
BUFF_ADD
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
BUFF_ADD

- BUFF_ADD: Buffer Address

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

#### UOTGHS Host DMA Channel Control Register (n = 2)

Name: UOTGHS_HSTDMACONTROL2

Access: read-write

Address: 0x400AC728

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
BUFF_LENGTH
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
BUFF_LENGTH
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
BURST_LCK | DESC_LD_IT | END_BUFFIT | END_TR_IT | END_B_EN | END_TR_EN | LDNXT_DSC | CHANN_ENB

- CHANN_ENB: Channel Enable Command

-

- LDNXT_DSC: Load Next Channel Transfer Descriptor Enable Command

-

- END_TR_EN: End of Transfer Enable (Control)

  Value | Name | Description
  --- | --- | ---
  0 | - | USB end of transfer is ignored.
  1 | - | UOTGHS device can put an end to the current buffer transfer.

- END_B_EN: End of Buffer Enable Control

  Value | Name | Description
  --- | --- | ---
  0 | - | DMA Buffer End has no impact on USB packet transfer.
  1 | - | the pipe can validate the packet (according to the values programmed in the UOTGHS_HSTPIPCFGx.AUTOSW field, and in the UOTGHS_HSTPIPIMRx.SHORTPACKETIE field) at DMA Buffer End, i.e. when UOTGHS_HSTDMASTATUS.BUFF_COUNT reaches 0.

- END_TR_IT: End of Transfer Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | UOTGHS device initiated buffer transfer completion will not trigger any interrupt at UOTGHS_HSTDMASTATUSx.END_TR_ST rising.
  1 | - | an interrupt is sent after the buffer transfer is complete, if the UOTGHS device has ended the buffer transfer.

- END_BUFFIT: End of Buffer Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | UOTGHS_HSTDMASTATUSx.END_BF_ST rising will not trigger any interrupt.
  1 | - | an interrupt is generated when UOTGHS_HSTDMASTATUSx.BUFF_COUNT reaches zero.

- DESC_LD_IT: Descriptor Loaded Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | UOTGHS_HSTDMASTATUSx.DESC_LDST rising will not trigger any interrupt.
  1 | - | an interrupt is generated when a descriptor has been loaded from the bus.

- BURST_LCK: Burst Lock Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | the DMA never locks the bus access.
  1 | - | USB packets AHB data bursts are locked for maximum optimization of the bus bandwidth usage and maximization of fly-by AHB burst duration.

- BUFF_LENGTH: Buffer Byte Length (Write-only)

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

#### UOTGHS Host DMA Channel Status Register (n = 2)

Name: UOTGHS_HSTDMASTATUS2

Access: read-write

Address: 0x400AC72C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
BUFF_COUNT
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
BUFF_COUNT
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | DESC_LDST | END_BF_ST | END_TR_ST | - | - | CHANN_ACT | CHANN_ENB

- CHANN_ENB: Channel Enable Status

  Value | Name | Description
  --- | --- | ---
  0 | - | if cleared, the DMA channel no longer transfers data, and may load the next descriptor if UOTGHS_HSTDMACONTROLx.LDNXT_DSC bit is set.
  1 | - | if set, the DMA channel is currently enabled and transfers data upon request.

- CHANN_ACT: Channel Active Status

  Value | Name | Description
  --- | --- | ---
  0 | - | the DMA channel is no longer trying to source the packet data.
  1 | - | the DMA channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel.

- END_TR_ST: End of Channel Transfer Status

  Value | Name | Description
  --- | --- | ---
  0 | - | cleared automatically when read by software.
  1 | - | set by hardware when the last packet transfer is complete, if the UOTGHS device has ended the transfer.

- END_BF_ST: End of Channel Buffer Status

  Value | Name | Description
  --- | --- | ---
  0 | - | cleared automatically when read by software.
  1 | - | set by hardware when BUFF_COUNT count-down reaches zero.

- DESC_LDST: Descriptor Loaded Status

  Value | Name | Description
  --- | --- | ---
  0 | - | cleared automatically when read by software.
  1 | - | set by hardware when a descriptor has been loaded from the system bus.

- BUFF_COUNT: Buffer Byte Count

-

#### UOTGHS Host DMA Channel Next Descriptor Address Register (n = 3)

Name: UOTGHS_HSTDMANXTDSC3

Access: read-write

Address: 0x400AC730

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
NXT_DSC_ADD
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NXT_DSC_ADD
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NXT_DSC_ADD
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NXT_DSC_ADD

- NXT_DSC_ADD: Next Descriptor Address

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

#### UOTGHS Host DMA Channel Address Register (n = 3)

Name: UOTGHS_HSTDMAADDRESS3

Access: read-write

Address: 0x400AC734

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
BUFF_ADD
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
BUFF_ADD
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
BUFF_ADD
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
BUFF_ADD

- BUFF_ADD: Buffer Address

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

#### UOTGHS Host DMA Channel Control Register (n = 3)

Name: UOTGHS_HSTDMACONTROL3

Access: read-write

Address: 0x400AC738

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
BUFF_LENGTH
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
BUFF_LENGTH
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
BURST_LCK | DESC_LD_IT | END_BUFFIT | END_TR_IT | END_B_EN | END_TR_EN | LDNXT_DSC | CHANN_ENB

- CHANN_ENB: Channel Enable Command

-

- LDNXT_DSC: Load Next Channel Transfer Descriptor Enable Command

-

- END_TR_EN: End of Transfer Enable (Control)

  Value | Name | Description
  --- | --- | ---
  0 | - | USB end of transfer is ignored.
  1 | - | UOTGHS device can put an end to the current buffer transfer.

- END_B_EN: End of Buffer Enable Control

  Value | Name | Description
  --- | --- | ---
  0 | - | DMA Buffer End has no impact on USB packet transfer.
  1 | - | the pipe can validate the packet (according to the values programmed in the UOTGHS_HSTPIPCFGx.AUTOSW field, and in the UOTGHS_HSTPIPIMRx.SHORTPACKETIE field) at DMA Buffer End, i.e. when UOTGHS_HSTDMASTATUS.BUFF_COUNT reaches 0.

- END_TR_IT: End of Transfer Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | UOTGHS device initiated buffer transfer completion will not trigger any interrupt at UOTGHS_HSTDMASTATUSx.END_TR_ST rising.
  1 | - | an interrupt is sent after the buffer transfer is complete, if the UOTGHS device has ended the buffer transfer.

- END_BUFFIT: End of Buffer Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | UOTGHS_HSTDMASTATUSx.END_BF_ST rising will not trigger any interrupt.
  1 | - | an interrupt is generated when UOTGHS_HSTDMASTATUSx.BUFF_COUNT reaches zero.

- DESC_LD_IT: Descriptor Loaded Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | UOTGHS_HSTDMASTATUSx.DESC_LDST rising will not trigger any interrupt.
  1 | - | an interrupt is generated when a descriptor has been loaded from the bus.

- BURST_LCK: Burst Lock Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | the DMA never locks the bus access.
  1 | - | USB packets AHB data bursts are locked for maximum optimization of the bus bandwidth usage and maximization of fly-by AHB burst duration.

- BUFF_LENGTH: Buffer Byte Length (Write-only)

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

#### UOTGHS Host DMA Channel Status Register (n = 3)

Name: UOTGHS_HSTDMASTATUS3

Access: read-write

Address: 0x400AC73C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
BUFF_COUNT
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
BUFF_COUNT
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | DESC_LDST | END_BF_ST | END_TR_ST | - | - | CHANN_ACT | CHANN_ENB

- CHANN_ENB: Channel Enable Status

  Value | Name | Description
  --- | --- | ---
  0 | - | if cleared, the DMA channel no longer transfers data, and may load the next descriptor if UOTGHS_HSTDMACONTROLx.LDNXT_DSC bit is set.
  1 | - | if set, the DMA channel is currently enabled and transfers data upon request.

- CHANN_ACT: Channel Active Status

  Value | Name | Description
  --- | --- | ---
  0 | - | the DMA channel is no longer trying to source the packet data.
  1 | - | the DMA channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel.

- END_TR_ST: End of Channel Transfer Status

  Value | Name | Description
  --- | --- | ---
  0 | - | cleared automatically when read by software.
  1 | - | set by hardware when the last packet transfer is complete, if the UOTGHS device has ended the transfer.

- END_BF_ST: End of Channel Buffer Status

  Value | Name | Description
  --- | --- | ---
  0 | - | cleared automatically when read by software.
  1 | - | set by hardware when BUFF_COUNT count-down reaches zero.

- DESC_LDST: Descriptor Loaded Status

  Value | Name | Description
  --- | --- | ---
  0 | - | cleared automatically when read by software.
  1 | - | set by hardware when a descriptor has been loaded from the system bus.

- BUFF_COUNT: Buffer Byte Count

-

#### UOTGHS Host DMA Channel Next Descriptor Address Register (n = 4)

Name: UOTGHS_HSTDMANXTDSC4

Access: read-write

Address: 0x400AC740

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
NXT_DSC_ADD
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NXT_DSC_ADD
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NXT_DSC_ADD
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NXT_DSC_ADD

- NXT_DSC_ADD: Next Descriptor Address

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

#### UOTGHS Host DMA Channel Address Register (n = 4)

Name: UOTGHS_HSTDMAADDRESS4

Access: read-write

Address: 0x400AC744

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
BUFF_ADD
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
BUFF_ADD
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
BUFF_ADD
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
BUFF_ADD

- BUFF_ADD: Buffer Address

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

#### UOTGHS Host DMA Channel Control Register (n = 4)

Name: UOTGHS_HSTDMACONTROL4

Access: read-write

Address: 0x400AC748

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
BUFF_LENGTH
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
BUFF_LENGTH
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
BURST_LCK | DESC_LD_IT | END_BUFFIT | END_TR_IT | END_B_EN | END_TR_EN | LDNXT_DSC | CHANN_ENB

- CHANN_ENB: Channel Enable Command

-

- LDNXT_DSC: Load Next Channel Transfer Descriptor Enable Command

-

- END_TR_EN: End of Transfer Enable (Control)

  Value | Name | Description
  --- | --- | ---
  0 | - | USB end of transfer is ignored.
  1 | - | UOTGHS device can put an end to the current buffer transfer.

- END_B_EN: End of Buffer Enable Control

  Value | Name | Description
  --- | --- | ---
  0 | - | DMA Buffer End has no impact on USB packet transfer.
  1 | - | the pipe can validate the packet (according to the values programmed in the UOTGHS_HSTPIPCFGx.AUTOSW field, and in the UOTGHS_HSTPIPIMRx.SHORTPACKETIE field) at DMA Buffer End, i.e. when UOTGHS_HSTDMASTATUS.BUFF_COUNT reaches 0.

- END_TR_IT: End of Transfer Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | UOTGHS device initiated buffer transfer completion will not trigger any interrupt at UOTGHS_HSTDMASTATUSx.END_TR_ST rising.
  1 | - | an interrupt is sent after the buffer transfer is complete, if the UOTGHS device has ended the buffer transfer.

- END_BUFFIT: End of Buffer Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | UOTGHS_HSTDMASTATUSx.END_BF_ST rising will not trigger any interrupt.
  1 | - | an interrupt is generated when UOTGHS_HSTDMASTATUSx.BUFF_COUNT reaches zero.

- DESC_LD_IT: Descriptor Loaded Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | UOTGHS_HSTDMASTATUSx.DESC_LDST rising will not trigger any interrupt.
  1 | - | an interrupt is generated when a descriptor has been loaded from the bus.

- BURST_LCK: Burst Lock Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | the DMA never locks the bus access.
  1 | - | USB packets AHB data bursts are locked for maximum optimization of the bus bandwidth usage and maximization of fly-by AHB burst duration.

- BUFF_LENGTH: Buffer Byte Length (Write-only)

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

#### UOTGHS Host DMA Channel Status Register (n = 4)

Name: UOTGHS_HSTDMASTATUS4

Access: read-write

Address: 0x400AC74C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
BUFF_COUNT
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
BUFF_COUNT
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | DESC_LDST | END_BF_ST | END_TR_ST | - | - | CHANN_ACT | CHANN_ENB

- CHANN_ENB: Channel Enable Status

  Value | Name | Description
  --- | --- | ---
  0 | - | if cleared, the DMA channel no longer transfers data, and may load the next descriptor if UOTGHS_HSTDMACONTROLx.LDNXT_DSC bit is set.
  1 | - | if set, the DMA channel is currently enabled and transfers data upon request.

- CHANN_ACT: Channel Active Status

  Value | Name | Description
  --- | --- | ---
  0 | - | the DMA channel is no longer trying to source the packet data.
  1 | - | the DMA channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel.

- END_TR_ST: End of Channel Transfer Status

  Value | Name | Description
  --- | --- | ---
  0 | - | cleared automatically when read by software.
  1 | - | set by hardware when the last packet transfer is complete, if the UOTGHS device has ended the transfer.

- END_BF_ST: End of Channel Buffer Status

  Value | Name | Description
  --- | --- | ---
  0 | - | cleared automatically when read by software.
  1 | - | set by hardware when BUFF_COUNT count-down reaches zero.

- DESC_LDST: Descriptor Loaded Status

  Value | Name | Description
  --- | --- | ---
  0 | - | cleared automatically when read by software.
  1 | - | set by hardware when a descriptor has been loaded from the system bus.

- BUFF_COUNT: Buffer Byte Count

-

#### UOTGHS Host DMA Channel Next Descriptor Address Register (n = 5)

Name: UOTGHS_HSTDMANXTDSC5

Access: read-write

Address: 0x400AC750

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
NXT_DSC_ADD
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NXT_DSC_ADD
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NXT_DSC_ADD
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NXT_DSC_ADD

- NXT_DSC_ADD: Next Descriptor Address

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

#### UOTGHS Host DMA Channel Address Register (n = 5)

Name: UOTGHS_HSTDMAADDRESS5

Access: read-write

Address: 0x400AC754

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
BUFF_ADD
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
BUFF_ADD
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
BUFF_ADD
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
BUFF_ADD

- BUFF_ADD: Buffer Address

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

#### UOTGHS Host DMA Channel Control Register (n = 5)

Name: UOTGHS_HSTDMACONTROL5

Access: read-write

Address: 0x400AC758

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
BUFF_LENGTH
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
BUFF_LENGTH
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
BURST_LCK | DESC_LD_IT | END_BUFFIT | END_TR_IT | END_B_EN | END_TR_EN | LDNXT_DSC | CHANN_ENB

- CHANN_ENB: Channel Enable Command

-

- LDNXT_DSC: Load Next Channel Transfer Descriptor Enable Command

-

- END_TR_EN: End of Transfer Enable (Control)

  Value | Name | Description
  --- | --- | ---
  0 | - | USB end of transfer is ignored.
  1 | - | UOTGHS device can put an end to the current buffer transfer.

- END_B_EN: End of Buffer Enable Control

  Value | Name | Description
  --- | --- | ---
  0 | - | DMA Buffer End has no impact on USB packet transfer.
  1 | - | the pipe can validate the packet (according to the values programmed in the UOTGHS_HSTPIPCFGx.AUTOSW field, and in the UOTGHS_HSTPIPIMRx.SHORTPACKETIE field) at DMA Buffer End, i.e. when UOTGHS_HSTDMASTATUS.BUFF_COUNT reaches 0.

- END_TR_IT: End of Transfer Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | UOTGHS device initiated buffer transfer completion will not trigger any interrupt at UOTGHS_HSTDMASTATUSx.END_TR_ST rising.
  1 | - | an interrupt is sent after the buffer transfer is complete, if the UOTGHS device has ended the buffer transfer.

- END_BUFFIT: End of Buffer Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | UOTGHS_HSTDMASTATUSx.END_BF_ST rising will not trigger any interrupt.
  1 | - | an interrupt is generated when UOTGHS_HSTDMASTATUSx.BUFF_COUNT reaches zero.

- DESC_LD_IT: Descriptor Loaded Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | UOTGHS_HSTDMASTATUSx.DESC_LDST rising will not trigger any interrupt.
  1 | - | an interrupt is generated when a descriptor has been loaded from the bus.

- BURST_LCK: Burst Lock Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | the DMA never locks the bus access.
  1 | - | USB packets AHB data bursts are locked for maximum optimization of the bus bandwidth usage and maximization of fly-by AHB burst duration.

- BUFF_LENGTH: Buffer Byte Length (Write-only)

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

#### UOTGHS Host DMA Channel Status Register (n = 5)

Name: UOTGHS_HSTDMASTATUS5

Access: read-write

Address: 0x400AC75C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
BUFF_COUNT
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
BUFF_COUNT
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | DESC_LDST | END_BF_ST | END_TR_ST | - | - | CHANN_ACT | CHANN_ENB

- CHANN_ENB: Channel Enable Status

  Value | Name | Description
  --- | --- | ---
  0 | - | if cleared, the DMA channel no longer transfers data, and may load the next descriptor if UOTGHS_HSTDMACONTROLx.LDNXT_DSC bit is set.
  1 | - | if set, the DMA channel is currently enabled and transfers data upon request.

- CHANN_ACT: Channel Active Status

  Value | Name | Description
  --- | --- | ---
  0 | - | the DMA channel is no longer trying to source the packet data.
  1 | - | the DMA channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel.

- END_TR_ST: End of Channel Transfer Status

  Value | Name | Description
  --- | --- | ---
  0 | - | cleared automatically when read by software.
  1 | - | set by hardware when the last packet transfer is complete, if the UOTGHS device has ended the transfer.

- END_BF_ST: End of Channel Buffer Status

  Value | Name | Description
  --- | --- | ---
  0 | - | cleared automatically when read by software.
  1 | - | set by hardware when BUFF_COUNT count-down reaches zero.

- DESC_LDST: Descriptor Loaded Status

  Value | Name | Description
  --- | --- | ---
  0 | - | cleared automatically when read by software.
  1 | - | set by hardware when a descriptor has been loaded from the system bus.

- BUFF_COUNT: Buffer Byte Count

-

#### UOTGHS Host DMA Channel Next Descriptor Address Register (n = 6)

Name: UOTGHS_HSTDMANXTDSC6

Access: read-write

Address: 0x400AC760

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
NXT_DSC_ADD
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NXT_DSC_ADD
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NXT_DSC_ADD
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NXT_DSC_ADD

- NXT_DSC_ADD: Next Descriptor Address

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

#### UOTGHS Host DMA Channel Address Register (n = 6)

Name: UOTGHS_HSTDMAADDRESS6

Access: read-write

Address: 0x400AC764

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
BUFF_ADD
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
BUFF_ADD
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
BUFF_ADD
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
BUFF_ADD

- BUFF_ADD: Buffer Address

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

#### UOTGHS Host DMA Channel Control Register (n = 6)

Name: UOTGHS_HSTDMACONTROL6

Access: read-write

Address: 0x400AC768

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
BUFF_LENGTH
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
BUFF_LENGTH
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
BURST_LCK | DESC_LD_IT | END_BUFFIT | END_TR_IT | END_B_EN | END_TR_EN | LDNXT_DSC | CHANN_ENB

- CHANN_ENB: Channel Enable Command

-

- LDNXT_DSC: Load Next Channel Transfer Descriptor Enable Command

-

- END_TR_EN: End of Transfer Enable (Control)

  Value | Name | Description
  --- | --- | ---
  0 | - | USB end of transfer is ignored.
  1 | - | UOTGHS device can put an end to the current buffer transfer.

- END_B_EN: End of Buffer Enable Control

  Value | Name | Description
  --- | --- | ---
  0 | - | DMA Buffer End has no impact on USB packet transfer.
  1 | - | the pipe can validate the packet (according to the values programmed in the UOTGHS_HSTPIPCFGx.AUTOSW field, and in the UOTGHS_HSTPIPIMRx.SHORTPACKETIE field) at DMA Buffer End, i.e. when UOTGHS_HSTDMASTATUS.BUFF_COUNT reaches 0.

- END_TR_IT: End of Transfer Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | UOTGHS device initiated buffer transfer completion will not trigger any interrupt at UOTGHS_HSTDMASTATUSx.END_TR_ST rising.
  1 | - | an interrupt is sent after the buffer transfer is complete, if the UOTGHS device has ended the buffer transfer.

- END_BUFFIT: End of Buffer Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | UOTGHS_HSTDMASTATUSx.END_BF_ST rising will not trigger any interrupt.
  1 | - | an interrupt is generated when UOTGHS_HSTDMASTATUSx.BUFF_COUNT reaches zero.

- DESC_LD_IT: Descriptor Loaded Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | UOTGHS_HSTDMASTATUSx.DESC_LDST rising will not trigger any interrupt.
  1 | - | an interrupt is generated when a descriptor has been loaded from the bus.

- BURST_LCK: Burst Lock Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | the DMA never locks the bus access.
  1 | - | USB packets AHB data bursts are locked for maximum optimization of the bus bandwidth usage and maximization of fly-by AHB burst duration.

- BUFF_LENGTH: Buffer Byte Length (Write-only)

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

#### UOTGHS Host DMA Channel Status Register (n = 6)

Name: UOTGHS_HSTDMASTATUS6

Access: read-write

Address: 0x400AC76C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
BUFF_COUNT
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
BUFF_COUNT
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | DESC_LDST | END_BF_ST | END_TR_ST | - | - | CHANN_ACT | CHANN_ENB

- CHANN_ENB: Channel Enable Status

  Value | Name | Description
  --- | --- | ---
  0 | - | if cleared, the DMA channel no longer transfers data, and may load the next descriptor if UOTGHS_HSTDMACONTROLx.LDNXT_DSC bit is set.
  1 | - | if set, the DMA channel is currently enabled and transfers data upon request.

- CHANN_ACT: Channel Active Status

  Value | Name | Description
  --- | --- | ---
  0 | - | the DMA channel is no longer trying to source the packet data.
  1 | - | the DMA channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel.

- END_TR_ST: End of Channel Transfer Status

  Value | Name | Description
  --- | --- | ---
  0 | - | cleared automatically when read by software.
  1 | - | set by hardware when the last packet transfer is complete, if the UOTGHS device has ended the transfer.

- END_BF_ST: End of Channel Buffer Status

  Value | Name | Description
  --- | --- | ---
  0 | - | cleared automatically when read by software.
  1 | - | set by hardware when BUFF_COUNT count-down reaches zero.

- DESC_LDST: Descriptor Loaded Status

  Value | Name | Description
  --- | --- | ---
  0 | - | cleared automatically when read by software.
  1 | - | set by hardware when a descriptor has been loaded from the system bus.

- BUFF_COUNT: Buffer Byte Count

-

#### UOTGHS Host DMA Channel Next Descriptor Address Register (n = 7)

Name: UOTGHS_HSTDMANXTDSC7

Access: read-write

Address: 0x400AC770

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
NXT_DSC_ADD
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NXT_DSC_ADD
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NXT_DSC_ADD
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NXT_DSC_ADD

- NXT_DSC_ADD: Next Descriptor Address

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

#### UOTGHS Host DMA Channel Address Register (n = 7)

Name: UOTGHS_HSTDMAADDRESS7

Access: read-write

Address: 0x400AC774

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
BUFF_ADD
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
BUFF_ADD
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
BUFF_ADD
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
BUFF_ADD

- BUFF_ADD: Buffer Address

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

#### UOTGHS Host DMA Channel Control Register (n = 7)

Name: UOTGHS_HSTDMACONTROL7

Access: read-write

Address: 0x400AC778

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
BUFF_LENGTH
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
BUFF_LENGTH
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
BURST_LCK | DESC_LD_IT | END_BUFFIT | END_TR_IT | END_B_EN | END_TR_EN | LDNXT_DSC | CHANN_ENB

- CHANN_ENB: Channel Enable Command

-

- LDNXT_DSC: Load Next Channel Transfer Descriptor Enable Command

-

- END_TR_EN: End of Transfer Enable (Control)

  Value | Name | Description
  --- | --- | ---
  0 | - | USB end of transfer is ignored.
  1 | - | UOTGHS device can put an end to the current buffer transfer.

- END_B_EN: End of Buffer Enable Control

  Value | Name | Description
  --- | --- | ---
  0 | - | DMA Buffer End has no impact on USB packet transfer.
  1 | - | the pipe can validate the packet (according to the values programmed in the UOTGHS_HSTPIPCFGx.AUTOSW field, and in the UOTGHS_HSTPIPIMRx.SHORTPACKETIE field) at DMA Buffer End, i.e. when UOTGHS_HSTDMASTATUS.BUFF_COUNT reaches 0.

- END_TR_IT: End of Transfer Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | UOTGHS device initiated buffer transfer completion will not trigger any interrupt at UOTGHS_HSTDMASTATUSx.END_TR_ST rising.
  1 | - | an interrupt is sent after the buffer transfer is complete, if the UOTGHS device has ended the buffer transfer.

- END_BUFFIT: End of Buffer Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | UOTGHS_HSTDMASTATUSx.END_BF_ST rising will not trigger any interrupt.
  1 | - | an interrupt is generated when UOTGHS_HSTDMASTATUSx.BUFF_COUNT reaches zero.

- DESC_LD_IT: Descriptor Loaded Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | UOTGHS_HSTDMASTATUSx.DESC_LDST rising will not trigger any interrupt.
  1 | - | an interrupt is generated when a descriptor has been loaded from the bus.

- BURST_LCK: Burst Lock Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | the DMA never locks the bus access.
  1 | - | USB packets AHB data bursts are locked for maximum optimization of the bus bandwidth usage and maximization of fly-by AHB burst duration.

- BUFF_LENGTH: Buffer Byte Length (Write-only)

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

#### UOTGHS Host DMA Channel Status Register (n = 7)

Name: UOTGHS_HSTDMASTATUS7

Access: read-write

Address: 0x400AC77C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
BUFF_COUNT
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
BUFF_COUNT
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | DESC_LDST | END_BF_ST | END_TR_ST | - | - | CHANN_ACT | CHANN_ENB

- CHANN_ENB: Channel Enable Status

  Value | Name | Description
  --- | --- | ---
  0 | - | if cleared, the DMA channel no longer transfers data, and may load the next descriptor if UOTGHS_HSTDMACONTROLx.LDNXT_DSC bit is set.
  1 | - | if set, the DMA channel is currently enabled and transfers data upon request.

- CHANN_ACT: Channel Active Status

  Value | Name | Description
  --- | --- | ---
  0 | - | the DMA channel is no longer trying to source the packet data.
  1 | - | the DMA channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel.

- END_TR_ST: End of Channel Transfer Status

  Value | Name | Description
  --- | --- | ---
  0 | - | cleared automatically when read by software.
  1 | - | set by hardware when the last packet transfer is complete, if the UOTGHS device has ended the transfer.

- END_BF_ST: End of Channel Buffer Status

  Value | Name | Description
  --- | --- | ---
  0 | - | cleared automatically when read by software.
  1 | - | set by hardware when BUFF_COUNT count-down reaches zero.

- DESC_LDST: Descriptor Loaded Status

  Value | Name | Description
  --- | --- | ---
  0 | - | cleared automatically when read by software.
  1 | - | set by hardware when a descriptor has been loaded from the system bus.

- BUFF_COUNT: Buffer Byte Count

-

#### UOTGHS General Control Register

Name: UOTGHS_CTRL

Access: read-write

Address: 0x400AC800

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | UIMOD | UIDE
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | UNLOCK | TIMPAGE | - | - | TIMVALUE
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
USBE | FRZCLK | VBUSPO | OTGPADE | HNPREQ | SRPREQ | SRPSEL | VBUSHWC
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
STOE | HNPERRE | ROLEEXE | BCERRE | VBERRE | SRPE | VBUSTE | IDTE

- IDTE: ID Transition Interrupt Enable

-

- VBUSTE: VBus Transition Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | The VBus Transition Interrupt (UOTGHS_SR.VBUSTI) is disabled.
  1 | - | The VBus Transition Interrupt (UOTGHS_SR.VBUSTI) is enabled.

- SRPE: SRP Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | The SRP Interrupt (UOTGHS_SR.SRPI) is disabled.
  1 | - | The SRP Interrupt (UOTGHS_SR.SRPI) is enabled.

- VBERRE: VBus Error Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | The VBus Error Interrupt (UOTGHS_SR.VBERRI) is disabled.
  1 | - | The VBus Error Interrupt (UOTGHS_SR.VBERRI) is enabled.

- BCERRE: B-Connection Error Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | The B-Connection Error Interrupt (UOTGHS_SR.BCERRI) is disabled.
  1 | - | The B-Connection Error Interrupt (UOTGHS_SR.BCERRI) is enabled.

- ROLEEXE: Role Exchange Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | The Role Exchange Interrupt (UOTGHS_SR.ROLEEXI) is disabled.
  1 | - | The Role Exchange Interrupt (UOTGHS_SR.ROLEEXI) is enabled.

- HNPERRE: HNP Error Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | The HNP Error Interrupt (UOTGHS_SR.HNPERRI) is disabled.
  1 | - | The HNP Error Interrupt (UOTGHS_SR.HNPERRI) is enabled.

- STOE: Suspend Time-Out Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | The Suspend Time-Out Interrupt (UOTGHS_SR.STOI) is disabled.
  1 | - | The Suspend Time-Out Interrupt (UOTGHS_SR.STOI) is enabled.

- VBUSHWC: VBus Hardware Control

  Value | Name | Description
  --- | --- | ---
  0 | - | The hardware control over the UOTGVBOF output pin is enabled. The UOTGHS resets the UOTGVBOF output pin when a VBUS problem occurs.
  1 | - | The hardware control over the UOTGVBOF output pin is disabled.

- SRPSEL: SRP Selection

  Value | Name | Description
  --- | --- | ---
  0 | - | Data line pulsing is selected as an SRP method.
  1 | - | VBus pulsing is selected as an SRP method.

- SRPREQ: SRP Request

-

- HNPREQ: HNP Request

-

- OTGPADE: OTG Pad Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | The OTG pad is disabled.
  1 | - | The OTG pad is enabled.

- VBUSPO: VBus Polarity Off

  Value | Name | Description
  --- | --- | ---
  0 | - | The UOTGVBOF output signal is in its default mode (active high).
  1 | - | The UOTGVBOF output signal is inverted (active low).

- FRZCLK: Freeze USB Clock

  Value | Name | Description
  --- | --- | ---
  0 | - | The clock inputs are enabled.
  1 | - | The clock inputs are disabled (the resume detection is still active).This reduces the power consumption. Unless explicitly stated, all registers then become read-only.

- USBE: UOTGHS Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | The UOTGHS is disabled.
  1 | - | The UOTGHS is enabled.

- TIMVALUE: Timer Value

-

- TIMPAGE: Timer Page

-

- UNLOCK: Timer Access Unlock

  Value | Name | Description
  --- | --- | ---
  0 | - | The TIMPAGE and TIMVALUE fields are locked.
  1 | - | The TIMPAGE and TIMVALUE fields are unlocked.

- UIDE: UOTGID Pin Enable

  Value | Name | Description
  --- | --- | ---
  0 | UIMOD | The USB mode (device/host) is selected from the UIMOD bit.
  1 | UOTGID | The USB mode (device/host) is selected from the UOTGID input pin.

- UIMOD: UOTGHS Mode

  Value | Name | Description
  --- | --- | ---
  0 | Host | The module is in USB host mode.
  1 | Device | The module is in USB device mode.

#### UOTGHS General Status Register

Name: UOTGHS_SR

Access: read-only

Address: 0x400AC804

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | CLKUSABLE | SPEED | VBUS | ID | VBUSRQ | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
STOI | HNPERRI | ROLEEXI | BCERRI | VBERRI | SRPI | VBUSTI | IDTI

- IDTI: ID Transition Interrupt

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

- VBUSTI: VBus Transition Interrupt

-

- SRPI: SRP Interrupt

-

- VBERRI: VBus Error Interrupt

-

- BCERRI: B-Connection Error Interrupt

-

- ROLEEXI: Role Exchange Interrupt

-

- HNPERRI: HNP Error Interrupt

-

- STOI: Suspend Time-Out Interrupt

-

- VBUSRQ: VBus Request

  Value | Name | Description
  --- | --- | ---
  0 | - | The UOTGVBOF output pin is driven low to disable the VBUS power supply generation.
  1 | - | The UOTGVBOF output pin is driven high to enable the VBUS power supply generation.

- ID: UOTGID Pin State

-

- VBUS: VBus Level

-

- SPEED: Speed Status

  Value | Name | Description
  --- | --- | ---
  0x0 | FULL_SPEED | Full-Speed mode
  0x1 | HIGH_SPEED | High-Speed mode
  0x2 | LOW_SPEED | Low-Speed mode

- CLKUSABLE: UTMI Clock Usable

-

#### UOTGHS General Status Clear Register

Name: UOTGHS_SCR

Access: write-only

Address: 0x400AC808

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | VBUSRQC | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
STOIC | HNPERRIC | ROLEEXIC | BCERRIC | VBERRIC | SRPIC | VBUSTIC | IDTIC

- IDTIC: ID Transition Interrupt Clear

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

- VBUSTIC: VBus Transition Interrupt Clear

-

- SRPIC: SRP Interrupt Clear

-

- VBERRIC: VBus Error Interrupt Clear

-

- BCERRIC: B-Connection Error Interrupt Clear

-

- ROLEEXIC: Role Exchange Interrupt Clear

-

- HNPERRIC: HNP Error Interrupt Clear

-

- STOIC: Suspend Time-Out Interrupt Clear

-

- VBUSRQC: VBus Request Clear

-

#### UOTGHS General Status Set Register

Name: UOTGHS_SFR

Access: write-only

Address: 0x400AC80C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | VBUSRQS | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
STOIS | HNPERRIS | ROLEEXIS | BCERRIS | VBERRIS | SRPIS | VBUSTIS | IDTIS

- IDTIS: ID Transition Interrupt Set

  Value | Name | Description
  --- | --- | ---
  0x74CBB1 | - | 0
  0x1608940C365 | - | 8
  0x151ED2399749 | - | 16
  0x1C7847EB8CF1 | - | 24

- VBUSTIS: VBus Transition Interrupt Set

-

- SRPIS: SRP Interrupt Set

-

- VBERRIS: VBus Error Interrupt Set

-

- BCERRIS: B-Connection Error Interrupt Set

-

- ROLEEXIS: Role Exchange Interrupt Set

-

- HNPERRIS: HNP Error Interrupt Set

-

- STOIS: Suspend Time-Out Interrupt Set

-

- VBUSRQS: VBus Request Set

-

#### UOTGHS General Finite State Machine Register

Name: UOTGHS_FSM

Access: read-only

Address: 0x400AC82C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | DRDSTATE

- DRDSTATE

  Value | Name | Description
  --- | --- | ---
  0x0 | A_IDLESTATE | This is the start state for A-devices (when the ID pin is 0)
  0x1 | A_WAIT_VRISE | In this state, the A-device waits for the voltage on VBus to rise above the A-device VBus Valid threshold (4.4 V).
  0x2 | A_WAIT_BCON | In this state, the A-device waits for the B-device to signal a connection.
  0x3 | A_HOST | In this state, the A-device that operates in Host mode is operational.
  0x4 | A_SUSPEND | The A-device operating as a host is in the suspend mode.
  0x5 | A_PERIPHERAL | The A-device operates as a peripheral.
  0x6 | A_WAIT_VFALL | In this state, the A-device waits for the voltage on VBus to drop below the A-device Session Valid threshold (1.4 V).
  0x7 | A_VBUS_ERR | In this state, the A-device waits for recovery of the over-current condition that caused it to enter this state.
  0x8 | A_WAIT_DISCHARGE | In this state, the A-device waits for the data USB line to discharge (100 us).
  0x9 | B_IDLE | This is the start state for B-device (when the ID pin is 1).
  0xA | B_PERIPHERAL | In this state, the B-device acts as the peripheral.
  0xB | B_WAIT_BEGIN_HNP | In this state, the B-device is in suspend mode and waits until 3 ms before initiating the HNP protocol if requested.
  0xC | B_WAIT_DISCHARGE | In this state, the B-device waits for the data USB line to discharge (100 us) before becoming Host.
  0xD | B_WAIT_ACON | In this state, the B-device waits for the A-device to signal a connect before becoming B-Host.
  0xE | B_HOST | In this state, the B-device acts as the Host.
  0xF | B_SRP_INIT | In this state, the B-device attempts to start a session using the SRP protocol.