# SAM3XA SMC

## Static Memory Controller (SMC) User Interface

### Registers

Register Mapping
Address | Register | Name | Access | Reset
--- | --- | --- | --- | ---
0x400E0000 | SMC NFC Configuration Register | SMC_CFG | read-write | 0x00000000
0x400E0004 | SMC NFC Control Register | SMC_CTRL | write-only | 0x00000000
0x400E0008 | SMC NFC Status Register | SMC_SR | read-only | 0x00000000
0x400E000C | SMC NFC Interrupt Enable Register | SMC_IER | write-only | 0x00000000
0x400E0010 | SMC NFC Interrupt Disable Register | SMC_IDR | write-only | 0x00000000
0x400E0014 | SMC NFC Interrupt Mask Register | SMC_IMR | read-only | 0x00000000
0x400E0018 | SMC NFC Address Cycle Zero Register | SMC_ADDR | read-write | 0x00000000
0x400E001C | SMC Bank Address Register | SMC_BANK | read-write | 0x00000000
0x400E0020 | SMC ECC Control Register | SMC_ECC_CTRL | write-only | 0x00000000
0x400E0024 | SMC ECC Mode Register | SMC_ECC_MD | read-write | 0x00000000
0x400E0028 | SMC ECC Status 1 Register | SMC_ECC_SR1 | read-only | 0x00000000
0x400E002C | SMC ECC Parity 0 Register | SMC_ECC_PR0 | read-only | 0x00000000
0x400E0030 | SMC ECC parity 1 Register | SMC_ECC_PR1 | read-only | 0x00000000
0x400E0034 | SMC ECC status 2 Register | SMC_ECC_SR2 | read-only | 0x00000000
0x400E0038 | SMC ECC parity 2 Register | SMC_ECC_PR2 | read-only | 0x00000000
0x400E003C | SMC ECC parity 3 Register | SMC_ECC_PR3 | read-only | 0x00000000
0x400E0040 | SMC ECC parity 4 Register | SMC_ECC_PR4 | read-only | 0x00000000
0x400E0044 | SMC ECC parity 5 Register | SMC_ECC_PR5 | read-only | 0x00000000
0x400E0048 | SMC ECC parity 6 Register | SMC_ECC_PR6 | read-only | 0x00000000
0x400E004C | SMC ECC parity 7 Register | SMC_ECC_PR7 | read-only | 0x00000000
0x400E0050 | SMC ECC parity 8 Register | SMC_ECC_PR8 | read-only | 0x00000000
0x400E0054 | SMC ECC parity 9 Register | SMC_ECC_PR9 | read-only | 0x00000000
0x400E0058 | SMC ECC parity 10 Register | SMC_ECC_PR10 | read-only | 0x00000000
0x400E005C | SMC ECC parity 11 Register | SMC_ECC_PR11 | read-only | 0x00000000
0x400E0060 | SMC ECC parity 12 Register | SMC_ECC_PR12 | read-only | 0x00000000
0x400E0064 | SMC ECC parity 13 Register | SMC_ECC_PR13 | read-only | 0x00000000
0x400E0068 | SMC ECC parity 14 Register | SMC_ECC_PR14 | read-only | 0x00000000
0x400E006C | SMC ECC parity 15 Register | SMC_ECC_PR15 | read-only | 0x00000000
0x400E0070 | SMC Setup Register (CS_number = 0) | SMC_SETUP0 | read-write | 0x01010101
0x400E0074 | SMC Pulse Register (CS_number = 0) | SMC_PULSE0 | read-write | 0x01010101
0x400E0078 | SMC Cycle Register (CS_number = 0) | SMC_CYCLE0 | read-write | 0x00030003
0x400E007C | SMC Timings Register (CS_number = 0) | SMC_TIMINGS0 | read-write | 0x00000000
0x400E0080 | SMC Mode Register (CS_number = 0) | SMC_MODE0 | read-write | 0x10000003
0x400E0084 | SMC Setup Register (CS_number = 1) | SMC_SETUP1 | read-write | 0x01010101
0x400E0088 | SMC Pulse Register (CS_number = 1) | SMC_PULSE1 | read-write | 0x01010101
0x400E008C | SMC Cycle Register (CS_number = 1) | SMC_CYCLE1 | read-write | 0x00030003
0x400E0090 | SMC Timings Register (CS_number = 1) | SMC_TIMINGS1 | read-write | 0x00000000
0x400E0094 | SMC Mode Register (CS_number = 1) | SMC_MODE1 | read-write | 0x10000003
0x400E0098 | SMC Setup Register (CS_number = 2) | SMC_SETUP2 | read-write | 0x01010101
0x400E009C | SMC Pulse Register (CS_number = 2) | SMC_PULSE2 | read-write | 0x01010101
0x400E00A0 | SMC Cycle Register (CS_number = 2) | SMC_CYCLE2 | read-write | 0x00030003
0x400E00A4 | SMC Timings Register (CS_number = 2) | SMC_TIMINGS2 | read-write | 0x00000000
0x400E00A8 | SMC Mode Register (CS_number = 2) | SMC_MODE2 | read-write | 0x10000003
0x400E00AC | SMC Setup Register (CS_number = 3) | SMC_SETUP3 | read-write | 0x01010101
0x400E00B0 | SMC Pulse Register (CS_number = 3) | SMC_PULSE3 | read-write | 0x01010101
0x400E00B4 | SMC Cycle Register (CS_number = 3) | SMC_CYCLE3 | read-write | 0x00030003
0x400E00B8 | SMC Timings Register (CS_number = 3) | SMC_TIMINGS3 | read-write | 0x00000000
0x400E00BC | SMC Mode Register (CS_number = 3) | SMC_MODE3 | read-write | 0x10000003
0x400E00C0 | SMC Setup Register (CS_number = 4) | SMC_SETUP4 | read-write | 0x01010101
0x400E00C4 | SMC Pulse Register (CS_number = 4) | SMC_PULSE4 | read-write | 0x01010101
0x400E00C8 | SMC Cycle Register (CS_number = 4) | SMC_CYCLE4 | read-write | 0x00030003
0x400E00CC | SMC Timings Register (CS_number = 4) | SMC_TIMINGS4 | read-write | 0x00000000
0x400E00D0 | SMC Mode Register (CS_number = 4) | SMC_MODE4 | read-write | 0x10000003
0x400E00D4 | SMC Setup Register (CS_number = 5) | SMC_SETUP5 | read-write | 0x01010101
0x400E00D8 | SMC Pulse Register (CS_number = 5) | SMC_PULSE5 | read-write | 0x01010101
0x400E00DC | SMC Cycle Register (CS_number = 5) | SMC_CYCLE5 | read-write | 0x00030003
0x400E00E0 | SMC Timings Register (CS_number = 5) | SMC_TIMINGS5 | read-write | 0x00000000
0x400E00E4 | SMC Mode Register (CS_number = 5) | SMC_MODE5 | read-write | 0x10000003
0x400E00E8 | SMC Setup Register (CS_number = 6) | SMC_SETUP6 | read-write | 0x01010101
0x400E00EC | SMC Pulse Register (CS_number = 6) | SMC_PULSE6 | read-write | 0x01010101
0x400E00F0 | SMC Cycle Register (CS_number = 6) | SMC_CYCLE6 | read-write | 0x00030003
0x400E00F4 | SMC Timings Register (CS_number = 6) | SMC_TIMINGS6 | read-write | 0x00000000
0x400E00F8 | SMC Mode Register (CS_number = 6) | SMC_MODE6 | read-write | 0x10000003
0x400E00FC | SMC Setup Register (CS_number = 7) | SMC_SETUP7 | read-write | 0x01010101
0x400E0100 | SMC Pulse Register (CS_number = 7) | SMC_PULSE7 | read-write | 0x01010101
0x400E0104 | SMC Cycle Register (CS_number = 7) | SMC_CYCLE7 | read-write | 0x00030003
0x400E0108 | SMC Timings Register (CS_number = 7) | SMC_TIMINGS7 | read-write | 0x00000000
0x400E010C | SMC Mode Register (CS_number = 7) | SMC_MODE7 | read-write | 0x10000003
0x400E0110 | SMC OCMS Register | SMC_OCMS | read-write | 0x00000000
0x400E0114 | SMC OCMS KEY1 Register | SMC_KEY1 | write-only | 0x00000000
0x400E0118 | SMC OCMS KEY2 Register | SMC_KEY2 | write-only | 0x00000000
0x400E01E4 | Write Protection Control Register | SMC_WPCR | write-only | 0x00000000
0x400E01E8 | Write Protection Status Register | SMC_WPSR | read-only | 0x00000000

### Register Fields

#### SMC SMC NFC Configuration Register

Name: SMC_CFG

Access: read-write

Address: 0x400E0000

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | DTOMUL | DTOCYC
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | RBEDGE | EDGECTRL | - | - | RSPARE | WSPARE
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | PAGESIZE

- PAGESIZE

  Value | Name | Description
  --- | --- | ---
  0x0 | PS512_16 | Main area 512 Bytes + Spare area 16 Bytes = 528 Bytes
  0x1 | PS1024_32 | Main area 1024 Bytes + Spare area 32 Bytes = 1056 Bytes
  0x2 | PS2048_64 | Main area 2048 Bytes + Spare area 64 Bytes = 2112 Bytes
  0x3 | PS4096_128 | Main area 4096 Bytes + Spare area 128 Bytes = 4224 Bytes

- WSPARE: Write Spare Area

  Value | Name | Description
  --- | --- | ---
  0 | - | The NFC skips the spare area in write mode.
  1 | - | The NFC writes both main area and spare area in write mode.

- RSPARE: Read Spare Area

  Value | Name | Description
  --- | --- | ---
  0 | - | The NFC skips the spare area in read mode.
  1 | - | The NFC reads both main area and spare area in read mode.

- EDGECTRL: Rising/Falling Edge Detection Control

  Value | Name | Description
  --- | --- | ---
  0 | - | Rising edge is detected.
  1 | - | Falling edge is detected.

- RBEDGE: Ready/Busy Signal Edge Detection

  Value | Name | Description
  --- | --- | ---
  0 | - | When set to zero, RB_EDGE fields indicate the level of the Ready/Busy lines.
  1 | - | When set to one, RB_EDGE fields indicate only transition on Ready/Busy lines.

- DTOCYC: Data Timeout Cycle Number

-

- DTOMUL: Data Timeout Multiplier

  Value | Name | Description
  --- | --- | ---
  0x0 | X1 | DTOCYC
  0x1 | X16 | DTOCYC x 16
  0x2 | X128 | DTOCYC x 128
  0x3 | X256 | DTOCYC x 256
  0x4 | X1024 | DTOCYC x 1024
  0x5 | X4096 | DTOCYC x 4096
  0x6 | X65536 | DTOCYC x 65536
  0x7 | X1048576 | DTOCYC x 1048576

#### SMC SMC NFC Control Register

Name: SMC_CTRL

Access: write-only

Address: 0x400E0004

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | NFCDIS | NFCEN

- NFCEN: NAND Flash Controller Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | no effect.
  1 | - | Enable the NAND Flash controller.

- NFCDIS: NAND Flash Controller Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | no effect
  1 | - | Disable the NAND Flash controller.

#### SMC SMC NFC Status Register

Name: SMC_SR

Access: read-only

Address: 0x400E0008

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | RB_EDGE0
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NFCASE | AWB | UNDEF | DTOE | - | - | CMDDONE | XFRDONE
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | NFCSID | NFCWR | - | - | NFCBUSY
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | RB_FALL | RB_RISE | - | - | - | SMCSTS

- SMCSTS: NAND Flash Controller status (this field cannot be reset)

  Value | Name | Description
  --- | --- | ---
  0 | - | NAND Flash Controller is disabled.
  1 | - | NAND Flash Controller is enabled.

- RB_RISE: Selected Ready Busy Rising Edge Detected

-

- RB_FALL: Selected Ready Busy Falling Edge Detected

-

- NFCBUSY: NFC Busy (this field cannot be reset)

-

- NFCWR: NFC Write/Read Operation (this field cannot be reset)

-

- NFCSID: NFC Chip Select ID (this field cannot be reset)

-

- XFRDONE: NFC Data Transfer Terminated

-

- CMDDONE: Command Done

-

- DTOE: Data Timeout Error

-

- UNDEF: Undefined Area Error

-

- AWB: Accessing While Busy

-

- NFCASE: NFC Access Size Error

-

- RB_EDGE0: Ready/Busy Line 0 Edge Detected

-

#### SMC SMC NFC Interrupt Enable Register

Name: SMC_IER

Access: write-only

Address: 0x400E000C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | RB_EDGE0
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NFCASE | AWB | UNDEF | DTOE | - | - | CMDDONE | XFRDONE
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | RB_FALL | RB_RISE | - | - | - | -

- RB_RISE: Ready Busy Rising Edge Detection Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Interrupt source is enabled.

- RB_FALL: Ready Busy Falling Edge Detection Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Interrupt source is enabled.

- XFRDONE: Transfer Done Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Interrupt source is enabled.

- CMDDONE: Command Done Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Interrupt source is enabled.

- DTOE: Data Timeout Error Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Interrupt source is enabled.

- UNDEF: Undefined Area Access Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Interrupt source is enabled.

- AWB: Accessing While Busy Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Interrupt source is enabled.

- NFCASE: NFC Access Size Error Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Interrupt source is enabled.

- RB_EDGE0: Ready/Busy Line 0 Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Interrupt source is enabled.

#### SMC SMC NFC Interrupt Disable Register

Name: SMC_IDR

Access: write-only

Address: 0x400E0010

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | RB_EDGE0
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NFCASE | AWB | UNDEF | DTOE | - | - | CMDDONE | XFRDONE
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | RB_FALL | RB_RISE | - | - | - | -

- RB_RISE: Ready Busy Rising Edge Detection Interrupt Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Interrupt source is disabled.

- RB_FALL: Ready Busy Falling Edge Detection Interrupt Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Interrupt source is disabled.

- XFRDONE: Transfer Done Interrupt Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Interrupt source is disabled.

- CMDDONE: Command Done Interrupt Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Interrupt source is disabled.

- DTOE: Data Timeout Error Interrupt Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Interrupt source is disabled.

- UNDEF: Undefined Area Access Interrupt Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Interrupt source is disabled.

- AWB: Accessing While Busy Interrupt Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Interrupt source is disabled.

- NFCASE: NFC Access Size Error Interrupt Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Interrupt source is disabled.

- RB_EDGE0: Ready/Busy Line 0 Interrupt Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Interrupt source is disabled.

#### SMC SMC NFC Interrupt Mask Register

Name: SMC_IMR

Access: read-only

Address: 0x400E0014

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | RB_EDGE0
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NFCASE | AWB | UNDEF | DTOE | - | - | CMDDONE | XFRDONE
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | RB_FALL | RB_RISE | - | - | - | -

- RB_RISE: Ready Busy Rising Edge Detection Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | Interrupt source is disabled.
  1 | - | Interrupt source is enabled.

- RB_FALL: Ready Busy Falling Edge Detection Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | Interrupt source is disabled.
  1 | - | Interrupt source is enabled.

- XFRDONE: Transfer Done Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | Interrupt source is disabled.
  1 | - | Interrupt source is enabled.

- CMDDONE: Command Done Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | Interrupt source is disabled.
  1 | - | Interrupt source is enabled.

- DTOE: Data Timeout Error Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | Interrupt source is disabled.
  1 | - | Interrupt source is enabled.

- UNDEF: Undefined Area Access Interrupt Mask5

  Value | Name | Description
  --- | --- | ---
  0 | - | Interrupt source is disabled.
  1 | - | Interrupt source is enabled.

- AWB: Accessing While Busy Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | Interrupt source is disabled.
  1 | - | Interrupt source is enabled.

- NFCASE: NFC Access Size Error Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | Interrupt source is disabled.
  1 | - | Interrupt source is enabled.

- RB_EDGE0: Ready/Busy Line 0 Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | Interrupt source is disabled.
  1 | - | Interrupt source is enabled.

#### SMC SMC NFC Address Cycle Zero Register

Name: SMC_ADDR

Access: read-write

Address: 0x400E0018

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
ADDR_CYCLE0

- ADDR_CYCLE0: NAND Flash Array Address cycle 0

-

#### SMC SMC Bank Address Register

Name: SMC_BANK

Access: read-write

Address: 0x400E001C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | BANK

- BANK: Bank Identifier

-

#### SMC SMC ECC Control Register

Name: SMC_ECC_CTRL

Access: write-only

Address: 0x400E0020

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | SWRST | RST

- RST: Reset ECC

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Reset ECC parity registers.

- SWRST: Software Reset

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Reset all registers.

#### SMC SMC ECC Mode Register

Name: SMC_ECC_MD

Access: read-write

Address: 0x400E0024

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | TYPCORREC | - | - | ECC_PAGESIZE

- ECC_PAGESIZE: ECC Page Size

  Value | Name | Description
  --- | --- | ---
  0x0 | PS512_16 | Main area 512 Bytes + Spare area 16 Bytes = 528 Bytes
  0x1 | PS1024_32 | Main area 1024 Bytes + Spare area 32 Bytes = 1056 Bytes
  0x2 | PS2048_64 | Main area 2048 Bytes + Spare area 64 Bytes = 2112 Bytes
  0x3 | PS4096_128 | Main area 4096 Bytes + Spare area 128 Bytes = 4224 Bytes

- TYPCORREC: Type of Correction

  Value | Name | Description
  --- | --- | ---
  0x0 | CPAGE | 1 bit correction for a page of 512/1024/2048/4096 Bytes (for 8 or 16-bit NAND Flash)
  0x1 | C256B | 1 bit correction for 256 Bytes of data for a page of 512/2048/4096 bytes (for 8-bit NAND Flash only)
  0x2 | C512B | 1 bit correction for 512 Bytes of data for a page of 512/2048/4096 bytes (for 8-bit NAND Flash only)

#### SMC SMC ECC Status 1 Register

Name: SMC_ECC_SR1

Access: read-only

Address: 0x400E0028

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | ECCERR7 | RECERR7 | - | ECCERR6 | RECERR6
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | ECCERR5 | RECERR5 | - | ECCERR4 | RECERR4
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | MULERR3 | ECCERR3 | RECERR3 | - | MULERR2 | ECCERR2 | RECERR2
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | MULERR1 | ECCERR1 | RECERR1 | - | ECCERR0 | RECERR0

- RECERR0: Recoverable Error

  Value | Name | Description
  --- | --- | ---
  0 | - | No Errors Detected.
  1 | - | Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise multiple uncorrected errors were detected.

- ECCERR0: ECC Error

  Value | Name | Description
  --- | --- | ---
  0 | - | No Errors Detected.
  1 | - | A single bit error occurred in the ECC bytes.

- RECERR1: Recoverable Error in the page between the 256th and the 511th bytes or the 512nd and the 1023rd bytes

  Value | Name | Description
  --- | --- | ---
  0 | - | No Errors Detected.
  1 | - | Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise multiple uncorrected errors were detected.

- ECCERR1: ECC Error in the page between the 256th and the 511th bytes or between the 512nd and the 1023rd bytes

  Value | Name | Description
  --- | --- | ---
  0 | - | No Errors Detected.
  1 | - | A single bit error occurred in the ECC bytes.

- MULERR1: Multiple Error in the page between the 256th and the 511th bytes or between the 512nd and the 1023rd bytes

  Value | Name | Description
  --- | --- | ---
  0 | - | No Multiple Errors Detected.
  1 | - | Multiple Errors Detected.

- RECERR2: Recoverable Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes

  Value | Name | Description
  --- | --- | ---
  0 | - | No Errors Detected.
  1 | - | Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise, multiple uncorrected errors were detected.

- ECCERR2: ECC Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes

  Value | Name | Description
  --- | --- | ---
  0 | - | No Errors Detected.
  1 | - | A single bit error occurred in the ECC bytes.

- MULERR2: Multiple Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes

  Value | Name | Description
  --- | --- | ---
  0 | - | No Multiple Errors Detected.
  1 | - | Multiple Errors Detected.

- RECERR3: Recoverable Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes

  Value | Name | Description
  --- | --- | ---
  0 | - | No Errors Detected.
  1 | - | Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise multiple uncorrected errors were detected.

- ECCERR3: ECC Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes

  Value | Name | Description
  --- | --- | ---
  0 | - | No Errors Detected.
  1 | - | A single bit error occurred in the ECC bytes.

- MULERR3: Multiple Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes

  Value | Name | Description
  --- | --- | ---
  0 | - | No Multiple Errors Detected.
  1 | - | Multiple Errors Detected.

- RECERR4: Recoverable Error in the page between the 1024th and the 1279th bytes or between the 2048th and the 2559th bytes

  Value | Name | Description
  --- | --- | ---
  0 | - | No Errors Detected.
  1 | - | Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise multiple uncorrected errors were detected.

- ECCERR4: ECC Error in the page between the 1024th and the 1279th bytes or between the 2048th and the 2559th bytes

  Value | Name | Description
  --- | --- | ---
  0 | - | No Errors Detected.
  1 | - | A single bit error occurred in the ECC bytes.

- RECERR5: Recoverable Error in the page between the 1280th and the 1535th bytes or between the 2560th and the 3071st bytes

  Value | Name | Description
  --- | --- | ---
  0 | - | No Errors Detected.
  1 | - | Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise multiple uncorrected errors were detected

- ECCERR5: ECC Error in the page between the 1280th and the 1535th bytes or between the 2560th and the 3071st bytes

  Value | Name | Description
  --- | --- | ---
  0 | - | No Errors Detected.
  1 | - | A single bit error occurred in the ECC bytes.

- RECERR6: Recoverable Error in the page between the 1536th and the 1791st bytes or between the 3072nd and the 3583rd bytes

  Value | Name | Description
  --- | --- | ---
  0 | - | No Errors Detected.
  1 | - | Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise multiple uncorrected errors were detected.

- ECCERR6: ECC Error in the page between the 1536th and the 1791st bytes or between the 3072nd and the 3583rd bytes

  Value | Name | Description
  --- | --- | ---
  0 | - | No Errors Detected.
  1 | - | A single bit error occurred in the ECC bytes.

- RECERR7: Recoverable Error in the page between the 1792nd and the 2047th bytes or between the 3584th and the 4095th bytes

  Value | Name | Description
  --- | --- | ---
  0 | - | No Errors Detected.
  1 | - | Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise, multiple uncorrected errors were detected.

- ECCERR7: ECC Error in the page between the 1792nd and the 2047th bytes or between the 3584th and the 4095th bytes

  Value | Name | Description
  --- | --- | ---
  0 | - | No Errors Detected.
  1 | - | A single bit error occurred in the ECC bytes.

#### SMC SMC ECC Parity 0 Register

Name: SMC_ECC_PR0

Access: read-only

Address: 0x400E002C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
WORDADDR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
WORDADDR | BITADDR

- BITADDR: Bit Address

-

- WORDADDR: Word Address

-

Alternate: W9BIT

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NPARITY
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NPARITY | WORDADDR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
WORDADDR | BITADDR

- BITADDR: Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes

-

- WORDADDR: Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes

-

- NPARITY: Parity N

-

Alternate: W8BIT

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | NPARITY
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NPARITY | - | WORDADDR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
WORDADDR | BITADDR

- BITADDR: Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes

-

- WORDADDR: Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes

-

- NPARITY: Parity N

-

#### SMC SMC ECC parity 1 Register

Name: SMC_ECC_PR1

Access: read-only

Address: 0x400E0030

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NPARITY
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NPARITY

- NPARITY: Parity N

-

Alternate: W9BIT

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NPARITY
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NPARITY | WORDADDR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
WORDADDR | BITADDR

- BITADDR: Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes

-

- WORDADDR: Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes

-

- NPARITY: Parity N

-

Alternate: W8BIT

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | NPARITY
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NPARITY | - | WORDADDR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
WORDADDR | BITADDR

- BITADDR: Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes

-

- WORDADDR: Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes

-

- NPARITY: Parity N

-

#### SMC SMC ECC status 2 Register

Name: SMC_ECC_SR2

Access: read-only

Address: 0x400E0034

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | ECCERR15 | RECERR15 | - | ECCERR14 | RECERR14
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | ECCERR13 | RECERR13 | - | ECCERR12 | RECERR12
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | MULERR11 | ECCERR11 | RECERR11 | - | MULERR10 | ECCERR10 | RECERR10
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | MULERR9 | ECCERR9 | RECERR9 | - | ECCERR8 | RECERR8

- RECERR8: Recoverable Error in the page between the 2048th and the 2303rd bytes

  Value | Name | Description
  --- | --- | ---
  0 | - | No Errors Detected.
  1 | - | Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise multiple uncorrected errors were detected

- ECCERR8: ECC Error in the page between the 2048th and the 2303rd bytes

  Value | Name | Description
  --- | --- | ---
  0 | - | No Errors Detected.
  1 | - | A single bit error occurred in the ECC bytes.

- RECERR9: Recoverable Error in the page between the 2304th and the 2559th bytes

  Value | Name | Description
  --- | --- | ---
  0 | - | No Errors Detected.
  1 | - | Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise multiple uncorrected errors were detected.

- ECCERR9: ECC Error in the page between the 2304th and the 2559th bytes

  Value | Name | Description
  --- | --- | ---
  0 | - | No Errors Detected.
  1 | - | A single bit error occurred in the ECC bytes.

- MULERR9: Multiple Error in the page between the 2304th and the 2559th bytes

  Value | Name | Description
  --- | --- | ---
  0 | - | No Multiple Errors Detected.
  1 | - | Multiple Errors Detected.

- RECERR10: Recoverable Error in the page between the 2560th and the 2815th bytes

  Value | Name | Description
  --- | --- | ---
  0 | - | No Errors Detected.
  1 | - | Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise, multiple uncorrected errors were detected.

- ECCERR10: ECC Error in the page between the 2560th and the 2815th bytes

  Value | Name | Description
  --- | --- | ---
  0 | - | No Errors Detected.
  1 | - | A single bit error occurred in the ECC bytes.

- MULERR10: Multiple Error in the page between the 2560th and the 2815th bytes

  Value | Name | Description
  --- | --- | ---
  0 | - | No Multiple Errors Detected.
  1 | - | Multiple Errors Detected.

- RECERR11: Recoverable Error in the page between the 2816th and the 3071st bytes

  Value | Name | Description
  --- | --- | ---
  0 | - | No Errors Detected.
  1 | - | Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise, multiple uncorrected errors were detected

- ECCERR11: ECC Error in the page between the 2816th and the 3071st bytes

  Value | Name | Description
  --- | --- | ---
  0 | - | No Errors Detected.
  1 | - | A single bit error occurred in the ECC bytes.

- MULERR11: Multiple Error in the page between the 2816th and the 3071st bytes

  Value | Name | Description
  --- | --- | ---
  0 | - | No Multiple Errors Detected.
  1 | - | Multiple Errors Detected.

- RECERR12: Recoverable Error in the page between the 3072nd and the 3327th bytes

  Value | Name | Description
  --- | --- | ---
  0 | - | No Errors Detected
  1 | - | Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise multiple uncorrected errors were detected

- ECCERR12: ECC Error in the page between the 3072nd and the 3327th bytes

  Value | Name | Description
  --- | --- | ---
  0 | - | No Errors Detected
  1 | - | A single bit error occurred in the ECC bytes.

- RECERR13: Recoverable Error in the page between the 3328th and the 3583rd bytes

  Value | Name | Description
  --- | --- | ---
  0 | - | No Errors Detected.
  1 | - | Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise multiple uncorrected errors were detected.

- ECCERR13: ECC Error in the page between the 3328th and the 3583rd bytes

  Value | Name | Description
  --- | --- | ---
  0 | - | No Errors Detected.
  1 | - | A single bit error occurred in the ECC bytes.

- RECERR14: Recoverable Error in the page between the 3584th and the 3839th bytes

  Value | Name | Description
  --- | --- | ---
  0 | - | No Errors Detected.
  1 | - | Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise, multiple uncorrected errors were detected.

- ECCERR14: ECC Error in the page between the 3584th and the 3839th bytes

  Value | Name | Description
  --- | --- | ---
  0 | - | No Errors Detected.
  1 | - | A single bit error occurred in the ECC bytes.

- RECERR15: Recoverable Error in the page between the 3840th and the 4095th bytes

  Value | Name | Description
  --- | --- | ---
  0 | - | No Errors Detected.
  1 | - | Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise, multiple uncorrected errors were detected.

- ECCERR15: ECC Error in the page between the 3840th and the 4095th bytes

  Value | Name | Description
  --- | --- | ---
  0 | - | No Errors Detected.
  1 | - | A single bit error occurred in the ECC bytes.

#### SMC SMC ECC parity 2 Register

Name: SMC_ECC_PR2

Access: read-only

Address: 0x400E0038

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NPARITY
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NPARITY | WORDADDR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
WORDADDR | BITADDR

- BITADDR: Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes

-

- WORDADDR: Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes

-

- NPARITY: Parity N

-

Alternate: W8BIT

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | NPARITY
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NPARITY | - | WORDADDR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
WORDADDR | BITADDR

- BITADDR: Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes

-

- WORDADDR: Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes

-

- NPARITY: Parity N

-

#### SMC SMC ECC parity 3 Register

Name: SMC_ECC_PR3

Access: read-only

Address: 0x400E003C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NPARITY
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NPARITY | WORDADDR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
WORDADDR | BITADDR

- BITADDR: Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes

-

- WORDADDR: Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes

-

- NPARITY: Parity N

-

Alternate: W8BIT

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | NPARITY
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NPARITY | - | WORDADDR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
WORDADDR | BITADDR

- BITADDR: Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes

-

- WORDADDR: Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes

-

- NPARITY: Parity N

-

#### SMC SMC ECC parity 4 Register

Name: SMC_ECC_PR4

Access: read-only

Address: 0x400E0040

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NPARITY
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NPARITY | WORDADDR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
WORDADDR | BITADDR

- BITADDR: Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes

-

- WORDADDR: Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes

-

- NPARITY: Parity N

-

Alternate: W8BIT

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | NPARITY
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NPARITY | - | WORDADDR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
WORDADDR | BITADDR

- BITADDR: Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes

-

- WORDADDR: Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes

-

- NPARITY: Parity N

-

#### SMC SMC ECC parity 5 Register

Name: SMC_ECC_PR5

Access: read-only

Address: 0x400E0044

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NPARITY
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NPARITY | WORDADDR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
WORDADDR | BITADDR

- BITADDR: Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes

-

- WORDADDR: Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes

-

- NPARITY: Parity N

-

Alternate: W8BIT

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | NPARITY
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NPARITY | - | WORDADDR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
WORDADDR | BITADDR

- BITADDR: Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes

-

- WORDADDR: Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes

-

- NPARITY: Parity N

-

#### SMC SMC ECC parity 6 Register

Name: SMC_ECC_PR6

Access: read-only

Address: 0x400E0048

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NPARITY
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NPARITY | WORDADDR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
WORDADDR | BITADDR

- BITADDR: Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes

-

- WORDADDR: Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes

-

- NPARITY: Parity N

-

Alternate: W8BIT

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | NPARITY
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NPARITY | - | WORDADDR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
WORDADDR | BITADDR

- BITADDR: Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes

-

- WORDADDR: Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes

-

- NPARITY: Parity N

-

#### SMC SMC ECC parity 7 Register

Name: SMC_ECC_PR7

Access: read-only

Address: 0x400E004C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NPARITY
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NPARITY | WORDADDR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
WORDADDR | BITADDR

- BITADDR: Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes

-

- WORDADDR: Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes

-

- NPARITY: Parity N

-

Alternate: W8BIT

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | NPARITY
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NPARITY | - | WORDADDR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
WORDADDR | BITADDR

- BITADDR: Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes

-

- WORDADDR: Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes

-

- NPARITY: Parity N

-

#### SMC SMC ECC parity 8 Register

Name: SMC_ECC_PR8

Access: read-only

Address: 0x400E0050

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | NPARITY
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NPARITY | - | WORDADDR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
WORDADDR | BITADDR

- BITADDR: Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes

-

- WORDADDR: Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes

-

- NPARITY: Parity N

-

#### SMC SMC ECC parity 9 Register

Name: SMC_ECC_PR9

Access: read-only

Address: 0x400E0054

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | NPARITY
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NPARITY | - | WORDADDR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
WORDADDR | BITADDR

- BITADDR: Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes

-

- WORDADDR: Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes

-

- NPARITY: Parity N

-

#### SMC SMC ECC parity 10 Register

Name: SMC_ECC_PR10

Access: read-only

Address: 0x400E0058

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | NPARITY
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NPARITY | - | WORDADDR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
WORDADDR | BITADDR

- BITADDR: Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes

-

- WORDADDR: Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes

-

- NPARITY: Parity N

-

#### SMC SMC ECC parity 11 Register

Name: SMC_ECC_PR11

Access: read-only

Address: 0x400E005C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | NPARITY
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NPARITY | - | WORDADDR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
WORDADDR | BITADDR

- BITADDR: Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes

-

- WORDADDR: Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes

-

- NPARITY: Parity N

-

#### SMC SMC ECC parity 12 Register

Name: SMC_ECC_PR12

Access: read-only

Address: 0x400E0060

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | NPARITY
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NPARITY | - | WORDADDR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
WORDADDR | BITADDR

- BITADDR: Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes

-

- WORDADDR: Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes

-

- NPARITY: Parity N

-

#### SMC SMC ECC parity 13 Register

Name: SMC_ECC_PR13

Access: read-only

Address: 0x400E0064

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | NPARITY
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NPARITY | - | WORDADDR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
WORDADDR | BITADDR

- BITADDR: Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes

-

- WORDADDR: Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes

-

- NPARITY: Parity N

-

#### SMC SMC ECC parity 14 Register

Name: SMC_ECC_PR14

Access: read-only

Address: 0x400E0068

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | NPARITY
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NPARITY | - | WORDADDR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
WORDADDR | BITADDR

- BITADDR: Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes

-

- WORDADDR: Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes

-

- NPARITY: Parity N

-

#### SMC SMC ECC parity 15 Register

Name: SMC_ECC_PR15

Access: read-only

Address: 0x400E006C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | NPARITY
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NPARITY | - | WORDADDR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
WORDADDR | BITADDR

- BITADDR: Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes

-

- WORDADDR: Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes

-

- NPARITY: Parity N

-

#### SMC SMC Setup Register (CS_number = 0)

Name: SMC_SETUP0

Access: read-write

Address: 0x400E0070

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | NCS_RD_SETUP
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | NRD_SETUP
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | NCS_WR_SETUP
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | NWE_SETUP

- NWE_SETUP: NWE Setup Length

-

- NCS_WR_SETUP: NCS Setup Length in Write Access

-

- NRD_SETUP: NRD Setup Length

-

- NCS_RD_SETUP: NCS Setup Length in Read Access

-

#### SMC SMC Pulse Register (CS_number = 0)

Name: SMC_PULSE0

Access: read-write

Address: 0x400E0074

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | NCS_RD_PULSE
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | NRD_PULSE
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | NCS_WR_PULSE
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | NWE_PULSE

- NWE_PULSE: NWE Pulse Length

-

- NCS_WR_PULSE: NCS Pulse Length in WRITE Access

-

- NRD_PULSE: NRD Pulse Length

-

- NCS_RD_PULSE: NCS Pulse Length in READ Access

-

#### SMC SMC Cycle Register (CS_number = 0)

Name: SMC_CYCLE0

Access: read-write

Address: 0x400E0078

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | NRD_CYCLE
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NRD_CYCLE
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | NWE_CYCLE
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NWE_CYCLE

- NWE_CYCLE: Total Write Cycle Length

-

- NRD_CYCLE: Total Read Cycle Length

-

#### SMC SMC Timings Register (CS_number = 0)

Name: SMC_TIMINGS0

Access: read-write

Address: 0x400E007C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
NFSEL | RBNSEL | TWB
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | TRR
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | OCMS | TAR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TADL | TCLR

- TCLR: CLE to REN Low Delay

-

- TADL: ALE to Data Start

-

- TAR: ALE to REN Low Delay

-

- OCMS: Off Chip Memory Scrambling Enable

-

- TRR: Ready to REN Low Delay

-

- TWB: WEN High to REN to Busy

-

- RBNSEL: Ready/Busy Line Selection

-

- NFSEL: NAND Flash Selection

-

#### SMC SMC Mode Register (CS_number = 0)

Name: SMC_MODE0

Access: read-write

Address: 0x400E0080

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | TDF_MODE | TDF_CYCLES
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | DBW | - | - | - | BAT
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | EXNW_MODE | - | - | WRITE_MODE | READ_MODE

- READ_MODE

  Value | Name | Description
  --- | --- | ---
  0 | NCS_CTRL | The Read operation is controlled by the NCS signal.
  1 | NRD_CTRL | The Read operation is controlled by the NRD signal.

- WRITE_MODE

  Value | Name | Description
  --- | --- | ---
  0 | NCS_CTRL | The Write operation is controller by the NCS signal.
  1 | NWE_CTRL | The Write operation is controlled by the NWE signal.

- EXNW_MODE: NWAIT Mode

  Value | Name | Description
  --- | --- | ---
  0x0 | DISABLED | Disabled
  0x2 | FROZEN | Frozen Mode
  0x3 | READY | Ready Mode

- BAT: Byte Access Type

  Value | Name | Description
  --- | --- | ---
  0 | - | Byte select access type:
  1 | - | Byte write access type:

- DBW: Data Bus Width

  Value | Name | Description
  --- | --- | ---
  0 | BIT_8 | 8-bit bus
  1 | BIT_16 | 16-bit bus

- TDF_CYCLES: Data Float Time

-

- TDF_MODE: TDF Optimization

  Value | Name | Description
  --- | --- | ---
  0 | - | TDF optimization is disabled.
  1 | - | TDF optimization is enabled.

#### SMC SMC Setup Register (CS_number = 1)

Name: SMC_SETUP1

Access: read-write

Address: 0x400E0084

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | NCS_RD_SETUP
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | NRD_SETUP
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | NCS_WR_SETUP
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | NWE_SETUP

- NWE_SETUP: NWE Setup Length

-

- NCS_WR_SETUP: NCS Setup Length in Write Access

-

- NRD_SETUP: NRD Setup Length

-

- NCS_RD_SETUP: NCS Setup Length in Read Access

-

#### SMC SMC Pulse Register (CS_number = 1)

Name: SMC_PULSE1

Access: read-write

Address: 0x400E0088

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | NCS_RD_PULSE
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | NRD_PULSE
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | NCS_WR_PULSE
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | NWE_PULSE

- NWE_PULSE: NWE Pulse Length

-

- NCS_WR_PULSE: NCS Pulse Length in WRITE Access

-

- NRD_PULSE: NRD Pulse Length

-

- NCS_RD_PULSE: NCS Pulse Length in READ Access

-

#### SMC SMC Cycle Register (CS_number = 1)

Name: SMC_CYCLE1

Access: read-write

Address: 0x400E008C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | NRD_CYCLE
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NRD_CYCLE
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | NWE_CYCLE
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NWE_CYCLE

- NWE_CYCLE: Total Write Cycle Length

-

- NRD_CYCLE: Total Read Cycle Length

-

#### SMC SMC Timings Register (CS_number = 1)

Name: SMC_TIMINGS1

Access: read-write

Address: 0x400E0090

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
NFSEL | RBNSEL | TWB
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | TRR
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | OCMS | TAR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TADL | TCLR

- TCLR: CLE to REN Low Delay

-

- TADL: ALE to Data Start

-

- TAR: ALE to REN Low Delay

-

- OCMS: Off Chip Memory Scrambling Enable

-

- TRR: Ready to REN Low Delay

-

- TWB: WEN High to REN to Busy

-

- RBNSEL: Ready/Busy Line Selection

-

- NFSEL: NAND Flash Selection

-

#### SMC SMC Mode Register (CS_number = 1)

Name: SMC_MODE1

Access: read-write

Address: 0x400E0094

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | TDF_MODE | TDF_CYCLES
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | DBW | - | - | - | BAT
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | EXNW_MODE | - | - | WRITE_MODE | READ_MODE

- READ_MODE

  Value | Name | Description
  --- | --- | ---
  0 | NCS_CTRL | The Read operation is controlled by the NCS signal.
  1 | NRD_CTRL | The Read operation is controlled by the NRD signal.

- WRITE_MODE

  Value | Name | Description
  --- | --- | ---
  0 | NCS_CTRL | The Write operation is controller by the NCS signal.
  1 | NWE_CTRL | The Write operation is controlled by the NWE signal.

- EXNW_MODE: NWAIT Mode

  Value | Name | Description
  --- | --- | ---
  0x0 | DISABLED | Disabled
  0x2 | FROZEN | Frozen Mode
  0x3 | READY | Ready Mode

- BAT: Byte Access Type

  Value | Name | Description
  --- | --- | ---
  0 | - | Byte select access type:
  1 | - | Byte write access type:

- DBW: Data Bus Width

  Value | Name | Description
  --- | --- | ---
  0 | BIT_8 | 8-bit bus
  1 | BIT_16 | 16-bit bus

- TDF_CYCLES: Data Float Time

-

- TDF_MODE: TDF Optimization

  Value | Name | Description
  --- | --- | ---
  0 | - | TDF optimization is disabled.
  1 | - | TDF optimization is enabled.

#### SMC SMC Setup Register (CS_number = 2)

Name: SMC_SETUP2

Access: read-write

Address: 0x400E0098

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | NCS_RD_SETUP
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | NRD_SETUP
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | NCS_WR_SETUP
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | NWE_SETUP

- NWE_SETUP: NWE Setup Length

-

- NCS_WR_SETUP: NCS Setup Length in Write Access

-

- NRD_SETUP: NRD Setup Length

-

- NCS_RD_SETUP: NCS Setup Length in Read Access

-

#### SMC SMC Pulse Register (CS_number = 2)

Name: SMC_PULSE2

Access: read-write

Address: 0x400E009C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | NCS_RD_PULSE
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | NRD_PULSE
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | NCS_WR_PULSE
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | NWE_PULSE

- NWE_PULSE: NWE Pulse Length

-

- NCS_WR_PULSE: NCS Pulse Length in WRITE Access

-

- NRD_PULSE: NRD Pulse Length

-

- NCS_RD_PULSE: NCS Pulse Length in READ Access

-

#### SMC SMC Cycle Register (CS_number = 2)

Name: SMC_CYCLE2

Access: read-write

Address: 0x400E00A0

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | NRD_CYCLE
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NRD_CYCLE
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | NWE_CYCLE
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NWE_CYCLE

- NWE_CYCLE: Total Write Cycle Length

-

- NRD_CYCLE: Total Read Cycle Length

-

#### SMC SMC Timings Register (CS_number = 2)

Name: SMC_TIMINGS2

Access: read-write

Address: 0x400E00A4

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
NFSEL | RBNSEL | TWB
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | TRR
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | OCMS | TAR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TADL | TCLR

- TCLR: CLE to REN Low Delay

-

- TADL: ALE to Data Start

-

- TAR: ALE to REN Low Delay

-

- OCMS: Off Chip Memory Scrambling Enable

-

- TRR: Ready to REN Low Delay

-

- TWB: WEN High to REN to Busy

-

- RBNSEL: Ready/Busy Line Selection

-

- NFSEL: NAND Flash Selection

-

#### SMC SMC Mode Register (CS_number = 2)

Name: SMC_MODE2

Access: read-write

Address: 0x400E00A8

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | TDF_MODE | TDF_CYCLES
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | DBW | - | - | - | BAT
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | EXNW_MODE | - | - | WRITE_MODE | READ_MODE

- READ_MODE

  Value | Name | Description
  --- | --- | ---
  0 | NCS_CTRL | The Read operation is controlled by the NCS signal.
  1 | NRD_CTRL | The Read operation is controlled by the NRD signal.

- WRITE_MODE

  Value | Name | Description
  --- | --- | ---
  0 | NCS_CTRL | The Write operation is controller by the NCS signal.
  1 | NWE_CTRL | The Write operation is controlled by the NWE signal.

- EXNW_MODE: NWAIT Mode

  Value | Name | Description
  --- | --- | ---
  0x0 | DISABLED | Disabled
  0x2 | FROZEN | Frozen Mode
  0x3 | READY | Ready Mode

- BAT: Byte Access Type

  Value | Name | Description
  --- | --- | ---
  0 | - | Byte select access type:
  1 | - | Byte write access type:

- DBW: Data Bus Width

  Value | Name | Description
  --- | --- | ---
  0 | BIT_8 | 8-bit bus
  1 | BIT_16 | 16-bit bus

- TDF_CYCLES: Data Float Time

-

- TDF_MODE: TDF Optimization

  Value | Name | Description
  --- | --- | ---
  0 | - | TDF optimization is disabled.
  1 | - | TDF optimization is enabled.

#### SMC SMC Setup Register (CS_number = 3)

Name: SMC_SETUP3

Access: read-write

Address: 0x400E00AC

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | NCS_RD_SETUP
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | NRD_SETUP
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | NCS_WR_SETUP
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | NWE_SETUP

- NWE_SETUP: NWE Setup Length

-

- NCS_WR_SETUP: NCS Setup Length in Write Access

-

- NRD_SETUP: NRD Setup Length

-

- NCS_RD_SETUP: NCS Setup Length in Read Access

-

#### SMC SMC Pulse Register (CS_number = 3)

Name: SMC_PULSE3

Access: read-write

Address: 0x400E00B0

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | NCS_RD_PULSE
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | NRD_PULSE
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | NCS_WR_PULSE
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | NWE_PULSE

- NWE_PULSE: NWE Pulse Length

-

- NCS_WR_PULSE: NCS Pulse Length in WRITE Access

-

- NRD_PULSE: NRD Pulse Length

-

- NCS_RD_PULSE: NCS Pulse Length in READ Access

-

#### SMC SMC Cycle Register (CS_number = 3)

Name: SMC_CYCLE3

Access: read-write

Address: 0x400E00B4

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | NRD_CYCLE
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NRD_CYCLE
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | NWE_CYCLE
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NWE_CYCLE

- NWE_CYCLE: Total Write Cycle Length

-

- NRD_CYCLE: Total Read Cycle Length

-

#### SMC SMC Timings Register (CS_number = 3)

Name: SMC_TIMINGS3

Access: read-write

Address: 0x400E00B8

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
NFSEL | RBNSEL | TWB
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | TRR
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | OCMS | TAR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TADL | TCLR

- TCLR: CLE to REN Low Delay

-

- TADL: ALE to Data Start

-

- TAR: ALE to REN Low Delay

-

- OCMS: Off Chip Memory Scrambling Enable

-

- TRR: Ready to REN Low Delay

-

- TWB: WEN High to REN to Busy

-

- RBNSEL: Ready/Busy Line Selection

-

- NFSEL: NAND Flash Selection

-

#### SMC SMC Mode Register (CS_number = 3)

Name: SMC_MODE3

Access: read-write

Address: 0x400E00BC

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | TDF_MODE | TDF_CYCLES
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | DBW | - | - | - | BAT
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | EXNW_MODE | - | - | WRITE_MODE | READ_MODE

- READ_MODE

  Value | Name | Description
  --- | --- | ---
  0 | NCS_CTRL | The Read operation is controlled by the NCS signal.
  1 | NRD_CTRL | The Read operation is controlled by the NRD signal.

- WRITE_MODE

  Value | Name | Description
  --- | --- | ---
  0 | NCS_CTRL | The Write operation is controller by the NCS signal.
  1 | NWE_CTRL | The Write operation is controlled by the NWE signal.

- EXNW_MODE: NWAIT Mode

  Value | Name | Description
  --- | --- | ---
  0x0 | DISABLED | Disabled
  0x2 | FROZEN | Frozen Mode
  0x3 | READY | Ready Mode

- BAT: Byte Access Type

  Value | Name | Description
  --- | --- | ---
  0 | - | Byte select access type:
  1 | - | Byte write access type:

- DBW: Data Bus Width

  Value | Name | Description
  --- | --- | ---
  0 | BIT_8 | 8-bit bus
  1 | BIT_16 | 16-bit bus

- TDF_CYCLES: Data Float Time

-

- TDF_MODE: TDF Optimization

  Value | Name | Description
  --- | --- | ---
  0 | - | TDF optimization is disabled.
  1 | - | TDF optimization is enabled.

#### SMC SMC Setup Register (CS_number = 4)

Name: SMC_SETUP4

Access: read-write

Address: 0x400E00C0

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | NCS_RD_SETUP
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | NRD_SETUP
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | NCS_WR_SETUP
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | NWE_SETUP

- NWE_SETUP: NWE Setup Length

-

- NCS_WR_SETUP: NCS Setup Length in Write Access

-

- NRD_SETUP: NRD Setup Length

-

- NCS_RD_SETUP: NCS Setup Length in Read Access

-

#### SMC SMC Pulse Register (CS_number = 4)

Name: SMC_PULSE4

Access: read-write

Address: 0x400E00C4

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | NCS_RD_PULSE
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | NRD_PULSE
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | NCS_WR_PULSE
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | NWE_PULSE

- NWE_PULSE: NWE Pulse Length

-

- NCS_WR_PULSE: NCS Pulse Length in WRITE Access

-

- NRD_PULSE: NRD Pulse Length

-

- NCS_RD_PULSE: NCS Pulse Length in READ Access

-

#### SMC SMC Cycle Register (CS_number = 4)

Name: SMC_CYCLE4

Access: read-write

Address: 0x400E00C8

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | NRD_CYCLE
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NRD_CYCLE
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | NWE_CYCLE
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NWE_CYCLE

- NWE_CYCLE: Total Write Cycle Length

-

- NRD_CYCLE: Total Read Cycle Length

-

#### SMC SMC Timings Register (CS_number = 4)

Name: SMC_TIMINGS4

Access: read-write

Address: 0x400E00CC

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
NFSEL | RBNSEL | TWB
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | TRR
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | OCMS | TAR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TADL | TCLR

- TCLR: CLE to REN Low Delay

-

- TADL: ALE to Data Start

-

- TAR: ALE to REN Low Delay

-

- OCMS: Off Chip Memory Scrambling Enable

-

- TRR: Ready to REN Low Delay

-

- TWB: WEN High to REN to Busy

-

- RBNSEL: Ready/Busy Line Selection

-

- NFSEL: NAND Flash Selection

-

#### SMC SMC Mode Register (CS_number = 4)

Name: SMC_MODE4

Access: read-write

Address: 0x400E00D0

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | TDF_MODE | TDF_CYCLES
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | DBW | - | - | - | BAT
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | EXNW_MODE | - | - | WRITE_MODE | READ_MODE

- READ_MODE

  Value | Name | Description
  --- | --- | ---
  0 | NCS_CTRL | The Read operation is controlled by the NCS signal.
  1 | NRD_CTRL | The Read operation is controlled by the NRD signal.

- WRITE_MODE

  Value | Name | Description
  --- | --- | ---
  0 | NCS_CTRL | The Write operation is controller by the NCS signal.
  1 | NWE_CTRL | The Write operation is controlled by the NWE signal.

- EXNW_MODE: NWAIT Mode

  Value | Name | Description
  --- | --- | ---
  0x0 | DISABLED | Disabled
  0x2 | FROZEN | Frozen Mode
  0x3 | READY | Ready Mode

- BAT: Byte Access Type

  Value | Name | Description
  --- | --- | ---
  0 | - | Byte select access type:
  1 | - | Byte write access type:

- DBW: Data Bus Width

  Value | Name | Description
  --- | --- | ---
  0 | BIT_8 | 8-bit bus
  1 | BIT_16 | 16-bit bus

- TDF_CYCLES: Data Float Time

-

- TDF_MODE: TDF Optimization

  Value | Name | Description
  --- | --- | ---
  0 | - | TDF optimization is disabled.
  1 | - | TDF optimization is enabled.

#### SMC SMC Setup Register (CS_number = 5)

Name: SMC_SETUP5

Access: read-write

Address: 0x400E00D4

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | NCS_RD_SETUP
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | NRD_SETUP
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | NCS_WR_SETUP
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | NWE_SETUP

- NWE_SETUP: NWE Setup Length

-

- NCS_WR_SETUP: NCS Setup Length in Write Access

-

- NRD_SETUP: NRD Setup Length

-

- NCS_RD_SETUP: NCS Setup Length in Read Access

-

#### SMC SMC Pulse Register (CS_number = 5)

Name: SMC_PULSE5

Access: read-write

Address: 0x400E00D8

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | NCS_RD_PULSE
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | NRD_PULSE
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | NCS_WR_PULSE
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | NWE_PULSE

- NWE_PULSE: NWE Pulse Length

-

- NCS_WR_PULSE: NCS Pulse Length in WRITE Access

-

- NRD_PULSE: NRD Pulse Length

-

- NCS_RD_PULSE: NCS Pulse Length in READ Access

-

#### SMC SMC Cycle Register (CS_number = 5)

Name: SMC_CYCLE5

Access: read-write

Address: 0x400E00DC

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | NRD_CYCLE
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NRD_CYCLE
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | NWE_CYCLE
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NWE_CYCLE

- NWE_CYCLE: Total Write Cycle Length

-

- NRD_CYCLE: Total Read Cycle Length

-

#### SMC SMC Timings Register (CS_number = 5)

Name: SMC_TIMINGS5

Access: read-write

Address: 0x400E00E0

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
NFSEL | RBNSEL | TWB
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | TRR
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | OCMS | TAR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TADL | TCLR

- TCLR: CLE to REN Low Delay

-

- TADL: ALE to Data Start

-

- TAR: ALE to REN Low Delay

-

- OCMS: Off Chip Memory Scrambling Enable

-

- TRR: Ready to REN Low Delay

-

- TWB: WEN High to REN to Busy

-

- RBNSEL: Ready/Busy Line Selection

-

- NFSEL: NAND Flash Selection

-

#### SMC SMC Mode Register (CS_number = 5)

Name: SMC_MODE5

Access: read-write

Address: 0x400E00E4

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | TDF_MODE | TDF_CYCLES
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | DBW | - | - | - | BAT
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | EXNW_MODE | - | - | WRITE_MODE | READ_MODE

- READ_MODE

  Value | Name | Description
  --- | --- | ---
  0 | NCS_CTRL | The Read operation is controlled by the NCS signal.
  1 | NRD_CTRL | The Read operation is controlled by the NRD signal.

- WRITE_MODE

  Value | Name | Description
  --- | --- | ---
  0 | NCS_CTRL | The Write operation is controller by the NCS signal.
  1 | NWE_CTRL | The Write operation is controlled by the NWE signal.

- EXNW_MODE: NWAIT Mode

  Value | Name | Description
  --- | --- | ---
  0x0 | DISABLED | Disabled
  0x2 | FROZEN | Frozen Mode
  0x3 | READY | Ready Mode

- BAT: Byte Access Type

  Value | Name | Description
  --- | --- | ---
  0 | - | Byte select access type:
  1 | - | Byte write access type:

- DBW: Data Bus Width

  Value | Name | Description
  --- | --- | ---
  0 | BIT_8 | 8-bit bus
  1 | BIT_16 | 16-bit bus

- TDF_CYCLES: Data Float Time

-

- TDF_MODE: TDF Optimization

  Value | Name | Description
  --- | --- | ---
  0 | - | TDF optimization is disabled.
  1 | - | TDF optimization is enabled.

#### SMC SMC Setup Register (CS_number = 6)

Name: SMC_SETUP6

Access: read-write

Address: 0x400E00E8

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | NCS_RD_SETUP
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | NRD_SETUP
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | NCS_WR_SETUP
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | NWE_SETUP

- NWE_SETUP: NWE Setup Length

-

- NCS_WR_SETUP: NCS Setup Length in Write Access

-

- NRD_SETUP: NRD Setup Length

-

- NCS_RD_SETUP: NCS Setup Length in Read Access

-

#### SMC SMC Pulse Register (CS_number = 6)

Name: SMC_PULSE6

Access: read-write

Address: 0x400E00EC

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | NCS_RD_PULSE
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | NRD_PULSE
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | NCS_WR_PULSE
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | NWE_PULSE

- NWE_PULSE: NWE Pulse Length

-

- NCS_WR_PULSE: NCS Pulse Length in WRITE Access

-

- NRD_PULSE: NRD Pulse Length

-

- NCS_RD_PULSE: NCS Pulse Length in READ Access

-

#### SMC SMC Cycle Register (CS_number = 6)

Name: SMC_CYCLE6

Access: read-write

Address: 0x400E00F0

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | NRD_CYCLE
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NRD_CYCLE
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | NWE_CYCLE
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NWE_CYCLE

- NWE_CYCLE: Total Write Cycle Length

-

- NRD_CYCLE: Total Read Cycle Length

-

#### SMC SMC Timings Register (CS_number = 6)

Name: SMC_TIMINGS6

Access: read-write

Address: 0x400E00F4

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
NFSEL | RBNSEL | TWB
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | TRR
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | OCMS | TAR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TADL | TCLR

- TCLR: CLE to REN Low Delay

-

- TADL: ALE to Data Start

-

- TAR: ALE to REN Low Delay

-

- OCMS: Off Chip Memory Scrambling Enable

-

- TRR: Ready to REN Low Delay

-

- TWB: WEN High to REN to Busy

-

- RBNSEL: Ready/Busy Line Selection

-

- NFSEL: NAND Flash Selection

-

#### SMC SMC Mode Register (CS_number = 6)

Name: SMC_MODE6

Access: read-write

Address: 0x400E00F8

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | TDF_MODE | TDF_CYCLES
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | DBW | - | - | - | BAT
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | EXNW_MODE | - | - | WRITE_MODE | READ_MODE

- READ_MODE

  Value | Name | Description
  --- | --- | ---
  0 | NCS_CTRL | The Read operation is controlled by the NCS signal.
  1 | NRD_CTRL | The Read operation is controlled by the NRD signal.

- WRITE_MODE

  Value | Name | Description
  --- | --- | ---
  0 | NCS_CTRL | The Write operation is controller by the NCS signal.
  1 | NWE_CTRL | The Write operation is controlled by the NWE signal.

- EXNW_MODE: NWAIT Mode

  Value | Name | Description
  --- | --- | ---
  0x0 | DISABLED | Disabled
  0x2 | FROZEN | Frozen Mode
  0x3 | READY | Ready Mode

- BAT: Byte Access Type

  Value | Name | Description
  --- | --- | ---
  0 | - | Byte select access type:
  1 | - | Byte write access type:

- DBW: Data Bus Width

  Value | Name | Description
  --- | --- | ---
  0 | BIT_8 | 8-bit bus
  1 | BIT_16 | 16-bit bus

- TDF_CYCLES: Data Float Time

-

- TDF_MODE: TDF Optimization

  Value | Name | Description
  --- | --- | ---
  0 | - | TDF optimization is disabled.
  1 | - | TDF optimization is enabled.

#### SMC SMC Setup Register (CS_number = 7)

Name: SMC_SETUP7

Access: read-write

Address: 0x400E00FC

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | NCS_RD_SETUP
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | NRD_SETUP
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | NCS_WR_SETUP
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | NWE_SETUP

- NWE_SETUP: NWE Setup Length

-

- NCS_WR_SETUP: NCS Setup Length in Write Access

-

- NRD_SETUP: NRD Setup Length

-

- NCS_RD_SETUP: NCS Setup Length in Read Access

-

#### SMC SMC Pulse Register (CS_number = 7)

Name: SMC_PULSE7

Access: read-write

Address: 0x400E0100

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | NCS_RD_PULSE
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | NRD_PULSE
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | NCS_WR_PULSE
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | NWE_PULSE

- NWE_PULSE: NWE Pulse Length

-

- NCS_WR_PULSE: NCS Pulse Length in WRITE Access

-

- NRD_PULSE: NRD Pulse Length

-

- NCS_RD_PULSE: NCS Pulse Length in READ Access

-

#### SMC SMC Cycle Register (CS_number = 7)

Name: SMC_CYCLE7

Access: read-write

Address: 0x400E0104

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | NRD_CYCLE
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NRD_CYCLE
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | NWE_CYCLE
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NWE_CYCLE

- NWE_CYCLE: Total Write Cycle Length

-

- NRD_CYCLE: Total Read Cycle Length

-

#### SMC SMC Timings Register (CS_number = 7)

Name: SMC_TIMINGS7

Access: read-write

Address: 0x400E0108

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
NFSEL | RBNSEL | TWB
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | TRR
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | OCMS | TAR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TADL | TCLR

- TCLR: CLE to REN Low Delay

-

- TADL: ALE to Data Start

-

- TAR: ALE to REN Low Delay

-

- OCMS: Off Chip Memory Scrambling Enable

-

- TRR: Ready to REN Low Delay

-

- TWB: WEN High to REN to Busy

-

- RBNSEL: Ready/Busy Line Selection

-

- NFSEL: NAND Flash Selection

-

#### SMC SMC Mode Register (CS_number = 7)

Name: SMC_MODE7

Access: read-write

Address: 0x400E010C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | TDF_MODE | TDF_CYCLES
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | DBW | - | - | - | BAT
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | EXNW_MODE | - | - | WRITE_MODE | READ_MODE

- READ_MODE

  Value | Name | Description
  --- | --- | ---
  0 | NCS_CTRL | The Read operation is controlled by the NCS signal.
  1 | NRD_CTRL | The Read operation is controlled by the NRD signal.

- WRITE_MODE

  Value | Name | Description
  --- | --- | ---
  0 | NCS_CTRL | The Write operation is controller by the NCS signal.
  1 | NWE_CTRL | The Write operation is controlled by the NWE signal.

- EXNW_MODE: NWAIT Mode

  Value | Name | Description
  --- | --- | ---
  0x0 | DISABLED | Disabled
  0x2 | FROZEN | Frozen Mode
  0x3 | READY | Ready Mode

- BAT: Byte Access Type

  Value | Name | Description
  --- | --- | ---
  0 | - | Byte select access type:
  1 | - | Byte write access type:

- DBW: Data Bus Width

  Value | Name | Description
  --- | --- | ---
  0 | BIT_8 | 8-bit bus
  1 | BIT_16 | 16-bit bus

- TDF_CYCLES: Data Float Time

-

- TDF_MODE: TDF Optimization

  Value | Name | Description
  --- | --- | ---
  0 | - | TDF optimization is disabled.
  1 | - | TDF optimization is enabled.

#### SMC SMC OCMS Register

Name: SMC_OCMS

Access: read-write

Address: 0x400E0110

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | SRSE | SMSE

- SMSE: Static Memory Controller Scrambling Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | Disable "Off Chip" Scrambling for SMC access.
  1 | - | Enable "Off Chip" Scrambling for SMC access. (If OCMS field is set to 1 in the relevant SMC_TIMINGS register.)

- SRSE: SRAM Scrambling Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | Disable SRAM Scrambling for SRAM access.
  1 | - | Enable SRAM Scrambling for SRAM access. (If OCMS field is set to 1 in the relevant SMC_TIMINGS register.)

#### SMC SMC OCMS KEY1 Register

Name: SMC_KEY1

Access: write-only

Address: 0x400E0114

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
KEY1
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
KEY1
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
KEY1
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
KEY1

- KEY1: Off Chip Memory Scrambling (OCMS) Key Part 1

-

#### SMC SMC OCMS KEY2 Register

Name: SMC_KEY2

Access: write-only

Address: 0x400E0118

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
KEY2
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
KEY2
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
KEY2
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
KEY2

- KEY2: Off Chip Memory Scrambling (OCMS) Key Part 2

-

#### SMC Write Protection Control Register

Name: SMC_WPCR

Access: write-only

Address: 0x400E01E4

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
WP_KEY
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
WP_KEY
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
WP_KEY
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | WP_EN

- WP_EN: Write Protection Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | Disables the Write Protection if WP_KEY corresponds.
  1 | - | Enables the Write Protection if WP_KEY corresponds.

- WP_KEY: Write Protection KEY password

-

#### SMC Write Protection Status Register

Name: SMC_WPSR

Access: read-only

Address: 0x400E01E8

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
WP_VSRC
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
WP_VSRC
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | WP_VS

- WP_VS: Write Protection Violation Status

  Value | Name | Description
  --- | --- | ---
  0 | - | No Write Protect Violation has occurred since the last read of the SMC_WPSR register.
  1 | - | A Write Protect Violation has occurred since the last read of the SMC_WPSR register. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WP_VSRC.

- WP_VSRC: Write Protection Violation Source

-