# SAM3XA MATRIX

## AHB Bus Matrix (MATRIX) User Interface

### Registers

Register Mapping
Address | Register | Name | Access | Reset
--- | --- | --- | --- | ---
0x400E0400 | Master Configuration Register | MATRIX_MCFG[6] | read-write | 0x0
0x400E0440 | Slave Configuration Register | MATRIX_SCFG[9] | read-write | 0x000100100005001000000010000000100000001000000010000000100000001000000010
0x400E0480 | Priority Register A for Slave 0 | MATRIX_PRAS0 | read-write | 0x00000000
0x400E0488 | Priority Register A for Slave 1 | MATRIX_PRAS1 | read-write | 0x00000000
0x400E0490 | Priority Register A for Slave 2 | MATRIX_PRAS2 | read-write | 0x00000000
0x400E0498 | Priority Register A for Slave 3 | MATRIX_PRAS3 | read-write | 0x00000000
0x400E04A0 | Priority Register A for Slave 4 | MATRIX_PRAS4 | read-write | 0x00000000
0x400E04A8 | Priority Register A for Slave 5 | MATRIX_PRAS5 | read-write | 0x00000000
0x400E04B0 | Priority Register A for Slave 6 | MATRIX_PRAS6 | read-write | 0x00000000
0x400E04B8 | Priority Register A for Slave 7 | MATRIX_PRAS7 | read-write | 0x00000000
0x400E04C0 | Priority Register A for Slave 8 | MATRIX_PRAS8 | read-write | 0x00000000
0x400E0500 | Master Remap Control Register | MATRIX_MRCR | read-write | 0x00000000
0x400E0514 | System I/O Configuration register | MATRIX_SYSIO | read-write | 0x00000000
0x400E05E4 | Write Protect Mode Register | MATRIX_WPMR | read-write | 0x00000000
0x400E05E8 | Write Protect Status Register | MATRIX_WPSR | read-only | 0x00000000

### Register Fields

#### MATRIX Master Configuration Register

Name: MATRIX_MCFG[0:5]

Access: read-write

Address: 0x400E0400

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | ULBT

- ULBT: Undefined Length Burst Type

  Value | Name | Description
  --- | --- | ---
  0x0 | - | Infinite Length Burst
  0x1 | - | Single Access
  0x2 | - | Four Beat Burst
  0x3 | - | Eight Beat Burst
  0x4 | - | Sixteen Beat Burst

#### MATRIX Slave Configuration Register

Name: MATRIX_SCFG[0:8]

Access: read-write

Address: 0x400E0440

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | ARBT
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | FIXED_DEFMSTR | DEFMSTR_TYPE
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
SLOT_CYCLE

- SLOT_CYCLE: Maximum Number of Allowed Cycles for a Burst

-

- DEFMSTR_TYPE: Default Master Type

  Value | Name | Description
  --- | --- | ---
  0x0 | - | No Default Master
  0x1 | - | Last Default Master
  0x2 | - | Fixed Default Master

- FIXED_DEFMSTR: Fixed Default Master

-

- ARBT: Arbitration Type

  Value | Name | Description
  --- | --- | ---
  0x0 | - | Round-Robin Arbitration
  0x1 | - | Fixed Priority Arbitration
  0x2 | - | Reserved
  0x3 | - | Reserved

#### MATRIX Priority Register A for Slave 0

Name: MATRIX_PRAS0

Access: read-write

Address: 0x400E0480

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | M5PR | - | - | M4PR
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | M3PR | - | - | M2PR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | M1PR | - | - | M0PR

- M0PR: Master 0 Priority

-

- M1PR: Master 1 Priority

-

- M2PR: Master 2 Priority

-

- M3PR: Master 3 Priority

-

- M4PR: Master 4 Priority

-

- M5PR: Master 5 Priority

-

#### MATRIX Priority Register A for Slave 1

Name: MATRIX_PRAS1

Access: read-write

Address: 0x400E0488

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | M5PR | - | - | M4PR
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | M3PR | - | - | M2PR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | M1PR | - | - | M0PR

- M0PR: Master 0 Priority

-

- M1PR: Master 1 Priority

-

- M2PR: Master 2 Priority

-

- M3PR: Master 3 Priority

-

- M4PR: Master 4 Priority

-

- M5PR: Master 5 Priority

-

#### MATRIX Priority Register A for Slave 2

Name: MATRIX_PRAS2

Access: read-write

Address: 0x400E0490

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | M5PR | - | - | M4PR
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | M3PR | - | - | M2PR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | M1PR | - | - | M0PR

- M0PR: Master 0 Priority

-

- M1PR: Master 1 Priority

-

- M2PR: Master 2 Priority

-

- M3PR: Master 3 Priority

-

- M4PR: Master 4 Priority

-

- M5PR: Master 5 Priority

-

#### MATRIX Priority Register A for Slave 3

Name: MATRIX_PRAS3

Access: read-write

Address: 0x400E0498

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | M5PR | - | - | M4PR
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | M3PR | - | - | M2PR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | M1PR | - | - | M0PR

- M0PR: Master 0 Priority

-

- M1PR: Master 1 Priority

-

- M2PR: Master 2 Priority

-

- M3PR: Master 3 Priority

-

- M4PR: Master 4 Priority

-

- M5PR: Master 5 Priority

-

#### MATRIX Priority Register A for Slave 4

Name: MATRIX_PRAS4

Access: read-write

Address: 0x400E04A0

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | M5PR | - | - | M4PR
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | M3PR | - | - | M2PR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | M1PR | - | - | M0PR

- M0PR: Master 0 Priority

-

- M1PR: Master 1 Priority

-

- M2PR: Master 2 Priority

-

- M3PR: Master 3 Priority

-

- M4PR: Master 4 Priority

-

- M5PR: Master 5 Priority

-

#### MATRIX Priority Register A for Slave 5

Name: MATRIX_PRAS5

Access: read-write

Address: 0x400E04A8

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | M5PR | - | - | M4PR
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | M3PR | - | - | M2PR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | M1PR | - | - | M0PR

- M0PR: Master 0 Priority

-

- M1PR: Master 1 Priority

-

- M2PR: Master 2 Priority

-

- M3PR: Master 3 Priority

-

- M4PR: Master 4 Priority

-

- M5PR: Master 5 Priority

-

#### MATRIX Priority Register A for Slave 6

Name: MATRIX_PRAS6

Access: read-write

Address: 0x400E04B0

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | M5PR | - | - | M4PR
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | M3PR | - | - | M2PR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | M1PR | - | - | M0PR

- M0PR: Master 0 Priority

-

- M1PR: Master 1 Priority

-

- M2PR: Master 2 Priority

-

- M3PR: Master 3 Priority

-

- M4PR: Master 4 Priority

-

- M5PR: Master 5 Priority

-

#### MATRIX Priority Register A for Slave 7

Name: MATRIX_PRAS7

Access: read-write

Address: 0x400E04B8

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | M5PR | - | - | M4PR
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | M3PR | - | - | M2PR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | M1PR | - | - | M0PR

- M0PR: Master 0 Priority

-

- M1PR: Master 1 Priority

-

- M2PR: Master 2 Priority

-

- M3PR: Master 3 Priority

-

- M4PR: Master 4 Priority

-

- M5PR: Master 5 Priority

-

#### MATRIX Priority Register A for Slave 8

Name: MATRIX_PRAS8

Access: read-write

Address: 0x400E04C0

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | M5PR | - | - | M4PR
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | M3PR | - | - | M2PR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | M1PR | - | - | M0PR

- M0PR: Master 0 Priority

-

- M1PR: Master 1 Priority

-

- M2PR: Master 2 Priority

-

- M3PR: Master 3 Priority

-

- M4PR: Master 4 Priority

-

- M5PR: Master 5 Priority

-

#### MATRIX Master Remap Control Register

Name: MATRIX_MRCR

Access: read-write

Address: 0x400E0500

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | RCB5 | RCB4 | RCB3 | RCB2 | RCB1 | RCB0

- RCB0: Remap Command Bit for AHB Master 0

  Value | Name | Description
  --- | --- | ---
  0 | - | Disable remapped address decoding for the selected Master
  1 | - | Enable remapped address decoding for the selected Master

- RCB1: Remap Command Bit for AHB Master 1

  Value | Name | Description
  --- | --- | ---
  0 | - | Disable remapped address decoding for the selected Master
  1 | - | Enable remapped address decoding for the selected Master

- RCB2: Remap Command Bit for AHB Master 2

  Value | Name | Description
  --- | --- | ---
  0 | - | Disable remapped address decoding for the selected Master
  1 | - | Enable remapped address decoding for the selected Master

- RCB3: Remap Command Bit for AHB Master 3

  Value | Name | Description
  --- | --- | ---
  0 | - | Disable remapped address decoding for the selected Master
  1 | - | Enable remapped address decoding for the selected Master

- RCB4: Remap Command Bit for AHB Master 4

  Value | Name | Description
  --- | --- | ---
  0 | - | Disable remapped address decoding for the selected Master
  1 | - | Enable remapped address decoding for the selected Master

- RCB5: Remap Command Bit for AHB Master 5

  Value | Name | Description
  --- | --- | ---
  0 | - | Disable remapped address decoding for the selected Master
  1 | - | Enable remapped address decoding for the selected Master

#### MATRIX System I/O Configuration register

Name: MATRIX_SYSIO

Access: read-write

Address: 0x400E0514

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | SYSIO12 | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | -

- SYSIO12: PC0 or ERASE Assignment

  Value | Name | Description
  --- | --- | ---
  0 | - | PC0 function selected.

#### MATRIX Write Protect Mode Register

Name: MATRIX_WPMR

Access: read-write

Address: 0x400E05E4

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
WPKEY
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
WPKEY
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
WPKEY
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | WPEN

- WPEN: Write Protect ENable

  Value | Name | Description
  --- | --- | ---
  0 | - | Disables the Write Protect if WPKEY corresponds to 0x4D4154 ("MAT" in ASCII).
  1 | - | Enables the Write Protect if WPKEY corresponds to 0x4D4154 ("MAT" in ASCII).

- WPKEY: Write Protect KEY (Write-only)

-

#### MATRIX Write Protect Status Register

Name: MATRIX_WPSR

Access: read-only

Address: 0x400E05E8

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
WPVSRC
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
WPVSRC
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | WPVS

- WPVS: Write Protect Violation Status

  Value | Name | Description
  --- | --- | ---
  0 | - | No Write Protect Violation has occurred since the last write of MATRIX_WPMR.
  1 | - | At least one Write Protect Violation has occurred since the last write of MATRIX_WPMR.

- WPVSRC: Write Protect Violation Source

-