# SAM3XA WDT

## Watchdog Timer (WDT) User Interface

### Registers

Register Mapping
Address | Register | Name | Access | Reset
--- | --- | --- | --- | ---
0x400E1A50 | Control Register | WDT_CR | write-only | -
0x400E1A54 | Mode Register | WDT_MR | read-write | 0x3FFF2FFF
0x400E1A58 | Status Register | WDT_SR | read-only | 0x00000000

### Register Fields

#### WDT Control Register

Name: WDT_CR

Access: write-only

Address: 0x400E1A50

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
KEY
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | WDRSTT

- WDRSTT: Watchdog Restart

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Restarts the Watchdog.

- KEY: Password

-

#### WDT Mode Register

Name: WDT_MR

Access: read-write

Address: 0x400E1A54

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | WDIDLEHLT | WDDBGHLT | WDD
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
WDD
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
WDDIS | WDRPROC | WDRSTEN | WDFIEN | WDV
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
WDV

- WDV: Watchdog Counter Value

-

- WDFIEN: Watchdog Fault Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | A Watchdog fault (underflow or error) has no effect on interrupt.
  1 | - | A Watchdog fault (underflow or error) asserts interrupt.

- WDRSTEN: Watchdog Reset Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | A Watchdog fault (underflow or error) has no effect on the resets.
  1 | - | A Watchdog fault (underflow or error) triggers a Watchdog reset.

- WDRPROC: Watchdog Reset Processor

  Value | Name | Description
  --- | --- | ---
  0 | - | If WDRSTEN is 1, a Watchdog fault (underflow or error) activates all resets.
  1 | - | If WDRSTEN is 1, a Watchdog fault (underflow or error) activates the processor reset.

- WDDIS: Watchdog Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | Enables the Watchdog Timer.
  1 | - | Disables the Watchdog Timer.

- WDD: Watchdog Delta Value

-

- WDDBGHLT: Watchdog Debug Halt

  Value | Name | Description
  --- | --- | ---
  0 | - | The Watchdog runs when the processor is in debug state.
  1 | - | The Watchdog stops when the processor is in debug state.

- WDIDLEHLT: Watchdog Idle Halt

  Value | Name | Description
  --- | --- | ---
  0 | - | The Watchdog runs when the system is in idle mode.
  1 | - | The Watchdog stops when the system is in idle state.

#### WDT Status Register

Name: WDT_SR

Access: read-only

Address: 0x400E1A58

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | WDERR | WDUNF

- WDUNF: Watchdog Underflow

  Value | Name | Description
  --- | --- | ---
  0 | - | No Watchdog underflow occurred since the last read of WDT_SR.
  1 | - | At least one Watchdog underflow occurred since the last read of WDT_SR.

- WDERR: Watchdog Error

  Value | Name | Description
  --- | --- | ---
  0 | - | No Watchdog error occurred since the last read of WDT_SR.
  1 | - | At least one Watchdog error occurred since the last read of WDT_SR.