# SAM3XA SPI0

## Serial Peripheral Interface (SPI0) User Interface

### Registers

Register Mapping
Address | Register | Name | Access | Reset
--- | --- | --- | --- | ---
0x40008000 | Control Register | SPI0_CR | write-only | -
0x40008004 | Mode Register | SPI0_MR | read-write | 0x00000000
0x40008008 | Receive Data Register | SPI0_RDR | read-only | 0x00000000
0x4000800C | Transmit Data Register | SPI0_TDR | write-only | -
0x40008010 | Status Register | SPI0_SR | read-only | 0x000000F0
0x40008014 | Interrupt Enable Register | SPI0_IER | write-only | -
0x40008018 | Interrupt Disable Register | SPI0_IDR | write-only | -
0x4000801C | Interrupt Mask Register | SPI0_IMR | read-only | 0x00000000
0x40008030 | Chip Select Register | SPI0_CSR[4] | read-write | 0x0
0x400080E4 | Write Protection Control Register | SPI0_WPMR | read-write | 0x00000000
0x400080E8 | Write Protection Status Register | SPI0_WPSR | read-only | 0x00000000

### Register Fields

#### SPI0 Control Register

Name: SPI0_CR

Access: write-only

Address: 0x40008000

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | LASTXFER
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
SWRST | - | - | - | - | - | SPIDIS | SPIEN

- SPIEN: SPI Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the SPI to transfer and receive data.

- SPIDIS: SPI Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the SPI.

- SWRST: SPI Software Reset

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Reset the SPI. A software-triggered hardware reset of the SPI interface is performed.

- LASTXFER: Last Transfer

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | The current NPCS will be deasserted after the character written in TD has been transferred. When CSAAT is set, this allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD transfer has completed.

#### SPI0 Mode Register

Name: SPI0_MR

Access: read-write

Address: 0x40008004

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
DLYBCS
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | PCS
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
LLB | - | WDRBT | MODFDIS | - | PCSDEC | PS | MSTR

- MSTR: Master/Slave Mode

  Value | Name | Description
  --- | --- | ---
  0 | - | SPI is in Slave mode.
  1 | - | SPI is in Master mode.

- PS: Peripheral Select

  Value | Name | Description
  --- | --- | ---
  0 | - | Fixed Peripheral Select.
  1 | - | Variable Peripheral Select.

- PCSDEC: Chip Select Decode

  Value | Name | Description
  --- | --- | ---
  0 | - | The chip selects are directly connected to a peripheral device.
  1 | - | The four chip select lines are connected to a 4- to 16-bit decoder.

- MODFDIS: Mode Fault Detection

  Value | Name | Description
  --- | --- | ---
  0 | - | Mode fault detection is enabled.
  1 | - | Mode fault detection is disabled.

- WDRBT: Wait Data Read Before Transfer

  Value | Name | Description
  --- | --- | ---
  0 | - | No Effect. In master mode, a transfer can be initiated whatever the state of the Receive Data Register is.
  1 | - | In Master Mode, a transfer can start only if the Receive Data Register is empty, i.e. does not contain any unread data. This mode prevents overrun error in reception.

- LLB: Local Loopback Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | Local loopback path disabled.
  1 | - | Local loopback path enabled

- PCS: Peripheral Chip Select

-

- DLYBCS: Delay Between Chip Selects

-

#### SPI0 Receive Data Register

Name: SPI0_RDR

Access: read-only

Address: 0x40008008

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | PCS
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RD
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RD

- RD: Receive Data

-

- PCS: Peripheral Chip Select

-

#### SPI0 Transmit Data Register

Name: SPI0_TDR

Access: write-only

Address: 0x4000800C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | LASTXFER
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | PCS
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TD
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TD

- TD: Transmit Data

-

- PCS: Peripheral Chip Select

-

- LASTXFER: Last Transfer

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | The current NPCS will be deasserted after the character written in TD has been transferred. When CSAAT is set, this allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD transfer has completed.

#### SPI0 Status Register

Name: SPI0_SR

Access: read-only

Address: 0x40008010

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | SPIENS
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | UNDES | TXEMPTY | NSSR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | OVRES | MODF | TDRE | RDRF

- RDRF: Receive Data Register Full

  Value | Name | Description
  --- | --- | ---
  0 | - | No data has been received since the last read of SPI_RDR
  1 | - | Data has been received and the received data has been transferred from the serializer to SPI_RDR since the last read of SPI_RDR.

- TDRE: Transmit Data Register Empty

  Value | Name | Description
  --- | --- | ---
  0 | - | Data has been written to SPI_TDR and not yet transferred to the serializer.
  1 | - | The last data written in the Transmit Data Register has been transferred to the serializer.

- MODF: Mode Fault Error

  Value | Name | Description
  --- | --- | ---
  0 | - | No Mode Fault has been detected since the last read of SPI_SR.
  1 | - | A Mode Fault occurred since the last read of the SPI_SR.

- OVRES: Overrun Error Status

  Value | Name | Description
  --- | --- | ---
  0 | - | No overrun has been detected since the last read of SPI_SR.
  1 | - | An overrun has occurred since the last read of SPI_SR.

- NSSR: NSS Rising

  Value | Name | Description
  --- | --- | ---
  0 | - | No rising edge detected on NSS pin since last read.
  1 | - | A rising edge occurred on NSS pin since last read.

- TXEMPTY: Transmission Registers Empty

  Value | Name | Description
  --- | --- | ---
  0 | - | As soon as data is written in SPI_TDR.
  1 | - | SPI_TDR and internal shifter are empty. If a transfer delay has been defined, TXEMPTY is set after the completion of such delay.

- UNDES: Underrun Error Status (Slave Mode Only)

  Value | Name | Description
  --- | --- | ---
  0 | - | No underrun has been detected since the last read of SPI_SR.
  1 | - | A transfer begins whereas no data has been loaded in the Transmit Data Register.

- SPIENS: SPI Enable Status

  Value | Name | Description
  --- | --- | ---
  0 | - | SPI is disabled.
  1 | - | SPI is enabled.

#### SPI0 Interrupt Enable Register

Name: SPI0_IER

Access: write-only

Address: 0x40008014

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | UNDES | TXEMPTY | NSSR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | OVRES | MODF | TDRE | RDRF

- RDRF: Receive Data Register Full Interrupt Enable

-

- TDRE: SPI Transmit Data Register Empty Interrupt Enable

-

- MODF: Mode Fault Error Interrupt Enable

-

- OVRES: Overrun Error Interrupt Enable

-

- NSSR: NSS Rising Interrupt Enable

-

- TXEMPTY: Transmission Registers Empty Enable

-

- UNDES: Underrun Error Interrupt Enable

-

#### SPI0 Interrupt Disable Register

Name: SPI0_IDR

Access: write-only

Address: 0x40008018

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | UNDES | TXEMPTY | NSSR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | OVRES | MODF | TDRE | RDRF

- RDRF: Receive Data Register Full Interrupt Disable

-

- TDRE: SPI Transmit Data Register Empty Interrupt Disable

-

- MODF: Mode Fault Error Interrupt Disable

-

- OVRES: Overrun Error Interrupt Disable

-

- NSSR: NSS Rising Interrupt Disable

-

- TXEMPTY: Transmission Registers Empty Disable

-

- UNDES: Underrun Error Interrupt Disable

-

#### SPI0 Interrupt Mask Register

Name: SPI0_IMR

Access: read-only

Address: 0x4000801C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | UNDES | TXEMPTY | NSSR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | OVRES | MODF | TDRE | RDRF

- RDRF: Receive Data Register Full Interrupt Mask

-

- TDRE: SPI Transmit Data Register Empty Interrupt Mask

-

- MODF: Mode Fault Error Interrupt Mask

-

- OVRES: Overrun Error Interrupt Mask

-

- NSSR: NSS Rising Interrupt Mask

-

- TXEMPTY: Transmission Registers Empty Mask

-

- UNDES: Underrun Error Interrupt Mask

-

#### SPI0 Chip Select Register

Name: SPI0_CSR[0:3]

Access: read-write

Address: 0x40008030

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
DLYBCT
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
DLYBS
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
SCBR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
BITS | CSAAT | CSNAAT | NCPHA | CPOL

- CPOL: Clock Polarity

  Value | Name | Description
  --- | --- | ---
  0 | - | The inactive state value of SPCK is logic level zero.
  1 | - | The inactive state value of SPCK is logic level one.

- NCPHA: Clock Phase

  Value | Name | Description
  --- | --- | ---
  0 | - | Data is changed on the leading edge of SPCK and captured on the following edge of SPCK.
  1 | - | Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.

- CSNAAT: Chip Select Not Active After Transfer (Ignored if CSAAT = 1)

  Value | Name | Description
  --- | --- | ---
  0 | - | The Peripheral Chip Select does not rise between two transfers if the SPI_TDR is reloaded before the end of the first transfer and if the two transfers occur on the same Chip Select.
  1 | - | The Peripheral Chip Select rises systematically after each transfer performed on the same slave. It remains active after the end of transfer for a minimal duration of:

- CSAAT: Chip Select Not Active After Transfer (Ignored if CSAAT = 1)

  Value | Name | Description
  --- | --- | ---
  0 | - | The Peripheral Chip Select does not rise between two transfers if the SPI_TDR is reloaded before the end of the first transfer and if the two transfers occur on the same Chip Select.
  1 | - | The Peripheral Chip Select rises systematically after each transfer performed on the same slave. It remains active after the end of transfer for a minimal duration of:

- BITS: Bits Per Transfer

  Value | Name | Description
  --- | --- | ---
  0x0 | 8_BIT | 8 bits for transfer
  0x1 | 9_BIT | 9 bits for transfer
  0x2 | 10_BIT | 10 bits for transfer
  0x3 | 11_BIT | 11 bits for transfer
  0x4 | 12_BIT | 12 bits for transfer
  0x5 | 13_BIT | 13 bits for transfer
  0x6 | 14_BIT | 14 bits for transfer
  0x7 | 15_BIT | 15 bits for transfer
  0x8 | 16_BIT | 16 bits for transfer

- SCBR: Serial Clock Baud Rate

-

- DLYBS: Delay Before SPCK

-

- DLYBCT: Delay Between Consecutive Transfers

-

#### SPI0 Write Protection Control Register

Name: SPI0_WPMR

Access: read-write

Address: 0x400080E4

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
WPKEY
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
WPKEY
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
WPKEY
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | WPEN

- WPEN: Write Protection Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | The Write Protection is Disabled
  1 | - | The Write Protection is Enabled

- WPKEY: Write Protection Key Password

-

#### SPI0 Write Protection Status Register

Name: SPI0_WPSR

Access: read-only

Address: 0x400080E8

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
WPVSRC
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | WPVS

- WPVS: Write Protection Violation Status

  Value | Name | Description
  --- | --- | ---
  0 | - | No Write Protect Violation has occurred since the last read of the SPI_WPSR register.
  1 | - | A Write Protect Violation has occurred since the last read of the SPI_WPSR register. If this violation is an unauthorized

- WPVSRC: Write Protection Violation Source

-