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# arm_add_q15.c

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    00001 /* ----------------------------------------------------------------------
    00002 * Copyright (C) 2010 ARM Limited. All rights reserved.
    00003 *
    00004 * $Date:        15. July 2011
    00005 * $Revision:    V1.0.10
    00006 *
    00007 * Project:      CMSIS DSP Library
    00008 * Title:        arm_add_q15.c
    00009 *
    00010 * Description:  Q15 vector addition
    00011 *
    00012 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
    00013 *
    00014 * Version 1.0.10 2011/7/15
    00015 *    Big Endian support added and Merged M0 and M3/M4 Source code.
    00016 *
    00017 * Version 1.0.3 2010/11/29
    00018 *    Re-organized the CMSIS folders and updated documentation.
    00019 *
    00020 * Version 1.0.2 2010/11/11
    00021 *    Documentation updated.
    00022 *
    00023 * Version 1.0.1 2010/10/05
    00024 *    Production release and review comments incorporated.
    00025 *
    00026 * Version 1.0.0 2010/09/20
    00027 *    Production release and review comments incorporated.
    00028 *
    00029 * Version 0.0.7  2010/06/10
    00030 *    Misra-C changes done
    00031 * -------------------------------------------------------------------- */
    00032
    00033 #include "arm_math.h"
    00034
    00058 void arm_add_q15(
    00059   q15_t * pSrcA,
    00060   q15_t * pSrcB,
    00061   q15_t * pDst,
    00062   uint32_t blockSize)
    00063 {
    00064   uint32_t blkCnt;                               /* loop counter */
    00065
    00066 #ifndef ARM_MATH_CM0
    00067
    00068 /* Run the below code for Cortex-M4 and Cortex-M3 */
    00069
    00070
    00071   /*loop Unrolling */
    00072   blkCnt = blockSize >> 2u;
    00073
    00074   /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
    00075    ** a second loop below computes the remaining 1 to 3 samples. */
    00076   while(blkCnt > 0u)
    00077   {
    00078     /* C = A + B */
    00079     /* Add and then store the results in the destination buffer. */
    00080     *__SIMD32(pDst)++ = __QADD16(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++);
    00081     *__SIMD32(pDst)++ = __QADD16(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++);
    00082
    00083     /* Decrement the loop counter */
    00084     blkCnt--;
    00085   }
    00086
    00087   /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
    00088    ** No loop unrolling is used. */
    00089   blkCnt = blockSize % 0x4u;
    00090
    00091   while(blkCnt > 0u)
    00092   {
    00093     /* C = A + B */
    00094     /* Add and then store the results in the destination buffer. */
    00095     *pDst++ = (q15_t) __QADD16(*pSrcA++, *pSrcB++);
    00096
    00097     /* Decrement the loop counter */
    00098     blkCnt--;
    00099   }
    00100
    00101 #else
    00102
    00103   /* Run the below code for Cortex-M0 */
    00104
    00105
    00106
    00107   /* Initialize blkCnt with number of samples */
    00108   blkCnt = blockSize;
    00109
    00110   while(blkCnt > 0u)
    00111   {
    00112     /* C = A + B */
    00113     /* Add and then store the results in the destination buffer. */
    00114     *pDst++ = (q15_t) __SSAT(((q31_t) * pSrcA++ + *pSrcB++), 16);
    00115
    00116     /* Decrement the loop counter */
    00117     blkCnt--;
    00118   }
    00119
    00120 #endif /* #ifndef ARM_MATH_CM0 */
    00121
    00122
    00123 }
    00124

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