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# arm_add_f32.c

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    00001 /* ----------------------------------------------------------------------
    00002 * Copyright (C) 2010 ARM Limited. All rights reserved.
    00003 *
    00004 * $Date:        15. July 2011
    00005 * $Revision:    V1.0.10
    00006 *
    00007 * Project:      CMSIS DSP Library
    00008 * Title:        arm_add_f32.c
    00009 *
    00010 * Description:  Floating-point vector addition.
    00011 *
    00012 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
    00013 *
    00014 * Version 1.0.10 2011/7/15
    00015 *    Big Endian support added and Merged M0 and M3/M4 Source code.
    00016 *
    00017 * Version 1.0.3 2010/11/29
    00018 *    Re-organized the CMSIS folders and updated documentation.
    00019 *
    00020 * Version 1.0.2 2010/11/11
    00021 *    Documentation updated.
    00022 *
    00023 * Version 1.0.1 2010/10/05
    00024 *    Production release and review comments incorporated.
    00025 *
    00026 * Version 1.0.0 2010/09/20
    00027 *    Production release and review comments incorporated.
    00028 *
    00029 * Version 0.0.7  2010/06/10
    00030 *    Misra-C changes done
    00031 * ---------------------------------------------------------------------------- */
    00032
    00033 #include "arm_math.h"
    00034
    00065 void arm_add_f32(
    00066   float32_t * pSrcA,
    00067   float32_t * pSrcB,
    00068   float32_t * pDst,
    00069   uint32_t blockSize)
    00070 {
    00071   uint32_t blkCnt;                               /* loop counter */
    00072
    00073 #ifndef ARM_MATH_CM0
    00074
    00075 /* Run the below code for Cortex-M4 and Cortex-M3 */
    00076
    00077   /*loop Unrolling */
    00078   blkCnt = blockSize >> 2u;
    00079
    00080   /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
    00081    ** a second loop below computes the remaining 1 to 3 samples. */
    00082   while(blkCnt > 0u)
    00083   {
    00084     /* C = A + B */
    00085     /* Add and then store the results in the destination buffer. */
    00086     *pDst++ = (*pSrcA++) + (*pSrcB++);
    00087     *pDst++ = (*pSrcA++) + (*pSrcB++);
    00088     *pDst++ = (*pSrcA++) + (*pSrcB++);
    00089     *pDst++ = (*pSrcA++) + (*pSrcB++);
    00090
    00091     /* Decrement the loop counter */
    00092     blkCnt--;
    00093   }
    00094
    00095   /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
    00096    ** No loop unrolling is used. */
    00097   blkCnt = blockSize % 0x4u;
    00098
    00099 #else
    00100
    00101   /* Run the below code for Cortex-M0 */
    00102
    00103   /* Initialize blkCnt with number of samples */
    00104   blkCnt = blockSize;
    00105
    00106 #endif /* #ifndef ARM_MATH_CM0 */
    00107
    00108   while(blkCnt > 0u)
    00109   {
    00110     /* C = A + B */
    00111     /* Add and then store the results in the destination buffer. */
    00112     *pDst++ = (*pSrcA++) + (*pSrcB++);
    00113
    00114     /* Decrement the loop counter */
    00115     blkCnt--;
    00116   }
    00117 }
    00118

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