|  |  |  | #include <util/twi.h>
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							|  |  |  | #include <avr/io.h>
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							|  |  |  | #include <stdlib.h>
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							|  |  |  | #include <avr/interrupt.h>
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							|  |  |  | #include <util/twi.h>
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							|  |  |  | #include <stdbool.h>
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							|  |  |  | #include "i2c.h"
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							|  |  |  | 
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							|  |  |  | #ifdef USE_I2C
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							|  |  |  | 
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							|  |  |  | // Limits the amount of we wait for any one i2c transaction.
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							|  |  |  | // Since were running SCL line 100kHz (=> 10μs/bit), and each transactions is
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							|  |  |  | // 9 bits, a single transaction will take around 90μs to complete.
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							|  |  |  | //
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							|  |  |  | // (F_CPU/SCL_CLOCK)  =>  # of μC cycles to transfer a bit
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							|  |  |  | // poll loop takes at least 8 clock cycles to execute
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							|  |  |  | #define I2C_LOOP_TIMEOUT (9+1)*(F_CPU/SCL_CLOCK)/8
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							|  |  |  | 
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							|  |  |  | #define BUFFER_POS_INC() (slave_buffer_pos = (slave_buffer_pos+1)%SLAVE_BUFFER_SIZE)
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							|  |  |  | 
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							|  |  |  | volatile uint8_t i2c_slave_buffer[SLAVE_BUFFER_SIZE]; | 
					
						
							|  |  |  | 
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							|  |  |  | static volatile uint8_t slave_buffer_pos; | 
					
						
							|  |  |  | static volatile bool slave_has_register_set = false; | 
					
						
							|  |  |  | 
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							|  |  |  | // Wait for an i2c operation to finish
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							|  |  |  | inline static | 
					
						
							|  |  |  | void i2c_delay(void) { | 
					
						
							|  |  |  |   uint16_t lim = 0; | 
					
						
							|  |  |  |   while(!(TWCR & (1<<TWINT)) && lim < I2C_LOOP_TIMEOUT) | 
					
						
							|  |  |  |     lim++; | 
					
						
							|  |  |  | 
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							|  |  |  |   // easier way, but will wait slightly longer
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							|  |  |  |   // _delay_us(100);
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							|  |  |  | } | 
					
						
							|  |  |  | 
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							|  |  |  | // Setup twi to run at 100kHz
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							|  |  |  | void i2c_master_init(void) { | 
					
						
							|  |  |  |   // no prescaler
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							|  |  |  |   TWSR = 0; | 
					
						
							|  |  |  |   // Set TWI clock frequency to SCL_CLOCK. Need TWBR>10.
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							|  |  |  |   // Check datasheets for more info.
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							|  |  |  |   TWBR = ((F_CPU/SCL_CLOCK)-16)/2; | 
					
						
							|  |  |  | } | 
					
						
							|  |  |  | 
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							|  |  |  | // Start a transaction with the given i2c slave address. The direction of the
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							|  |  |  | // transfer is set with I2C_READ and I2C_WRITE.
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							|  |  |  | // returns: 0 => success
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							|  |  |  | //          1 => error
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							|  |  |  | uint8_t i2c_master_start(uint8_t address) { | 
					
						
							|  |  |  |   TWCR = (1<<TWINT) | (1<<TWEN) | (1<<TWSTA); | 
					
						
							|  |  |  | 
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							|  |  |  |   i2c_delay(); | 
					
						
							|  |  |  | 
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							|  |  |  |   // check that we started successfully
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							|  |  |  |   if ( (TW_STATUS != TW_START) && (TW_STATUS != TW_REP_START)) | 
					
						
							|  |  |  |     return 1; | 
					
						
							|  |  |  | 
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							|  |  |  |   TWDR = address; | 
					
						
							|  |  |  |   TWCR = (1<<TWINT) | (1<<TWEN); | 
					
						
							|  |  |  | 
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							|  |  |  |   i2c_delay(); | 
					
						
							|  |  |  | 
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							|  |  |  |   if ( (TW_STATUS != TW_MT_SLA_ACK) && (TW_STATUS != TW_MR_SLA_ACK) ) | 
					
						
							|  |  |  |     return 1; // slave did not acknowledge
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							|  |  |  |   else | 
					
						
							|  |  |  |     return 0; // success
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							|  |  |  | } | 
					
						
							|  |  |  | 
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							|  |  |  | 
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							|  |  |  | // Finish the i2c transaction.
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							|  |  |  | void i2c_master_stop(void) { | 
					
						
							|  |  |  |   TWCR = (1<<TWINT) | (1<<TWEN) | (1<<TWSTO); | 
					
						
							|  |  |  | 
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							|  |  |  |   uint16_t lim = 0; | 
					
						
							|  |  |  |   while(!(TWCR & (1<<TWSTO)) && lim < I2C_LOOP_TIMEOUT) | 
					
						
							|  |  |  |     lim++; | 
					
						
							|  |  |  | } | 
					
						
							|  |  |  | 
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							|  |  |  | // Write one byte to the i2c slave.
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							|  |  |  | // returns 0 => slave ACK
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							|  |  |  | //         1 => slave NACK
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							|  |  |  | uint8_t i2c_master_write(uint8_t data) { | 
					
						
							|  |  |  |   TWDR = data; | 
					
						
							|  |  |  |   TWCR = (1<<TWINT) | (1<<TWEN); | 
					
						
							|  |  |  | 
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							|  |  |  |   i2c_delay(); | 
					
						
							|  |  |  | 
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							|  |  |  |   // check if the slave acknowledged us
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							|  |  |  |   return (TW_STATUS == TW_MT_DATA_ACK) ? 0 : 1; | 
					
						
							|  |  |  | } | 
					
						
							|  |  |  | 
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							|  |  |  | // Read one byte from the i2c slave. If ack=1 the slave is acknowledged,
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							|  |  |  | // if ack=0 the acknowledge bit is not set.
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							|  |  |  | // returns: byte read from i2c device
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							|  |  |  | uint8_t i2c_master_read(int ack) { | 
					
						
							|  |  |  |   TWCR = (1<<TWINT) | (1<<TWEN) | (ack<<TWEA); | 
					
						
							|  |  |  | 
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							|  |  |  |   i2c_delay(); | 
					
						
							|  |  |  |   return TWDR; | 
					
						
							|  |  |  | } | 
					
						
							|  |  |  | 
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							|  |  |  | void i2c_reset_state(void) { | 
					
						
							|  |  |  |   TWCR = 0; | 
					
						
							|  |  |  | } | 
					
						
							|  |  |  | 
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							|  |  |  | void i2c_slave_init(uint8_t address) { | 
					
						
							|  |  |  |   TWAR = address << 0; // slave i2c address
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							|  |  |  |   // TWEN  - twi enable
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							|  |  |  |   // TWEA  - enable address acknowledgement
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							|  |  |  |   // TWINT - twi interrupt flag
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							|  |  |  |   // TWIE  - enable the twi interrupt
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							|  |  |  |   TWCR = (1<<TWIE) | (1<<TWEA) | (1<<TWINT) | (1<<TWEN); | 
					
						
							|  |  |  | } | 
					
						
							|  |  |  | 
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							|  |  |  | ISR(TWI_vect); | 
					
						
							|  |  |  | 
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							|  |  |  | ISR(TWI_vect) { | 
					
						
							|  |  |  |   uint8_t ack = 1; | 
					
						
							|  |  |  |   switch(TW_STATUS) { | 
					
						
							|  |  |  |     case TW_SR_SLA_ACK: | 
					
						
							|  |  |  |       // this device has been addressed as a slave receiver
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							|  |  |  |       slave_has_register_set = false; | 
					
						
							|  |  |  |       break; | 
					
						
							|  |  |  | 
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							|  |  |  |     case TW_SR_DATA_ACK: | 
					
						
							|  |  |  |       // this device has received data as a slave receiver
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							|  |  |  |       // The first byte that we receive in this transaction sets the location
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							|  |  |  |       // of the read/write location of the slaves memory that it exposes over
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							|  |  |  |       // i2c.  After that, bytes will be written at slave_buffer_pos, incrementing
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							|  |  |  |       // slave_buffer_pos after each write.
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							|  |  |  |       if(!slave_has_register_set) { | 
					
						
							|  |  |  |         slave_buffer_pos = TWDR; | 
					
						
							|  |  |  |         // don't acknowledge the master if this memory loctaion is out of bounds
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							|  |  |  |         if ( slave_buffer_pos >= SLAVE_BUFFER_SIZE ) { | 
					
						
							|  |  |  |           ack = 0; | 
					
						
							|  |  |  |           slave_buffer_pos = 0; | 
					
						
							|  |  |  |         } | 
					
						
							|  |  |  |         slave_has_register_set = true; | 
					
						
							|  |  |  |       } else { | 
					
						
							|  |  |  |         i2c_slave_buffer[slave_buffer_pos] = TWDR; | 
					
						
							|  |  |  |         BUFFER_POS_INC(); | 
					
						
							|  |  |  |       } | 
					
						
							|  |  |  |       break; | 
					
						
							|  |  |  | 
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							|  |  |  |     case TW_ST_SLA_ACK: | 
					
						
							|  |  |  |     case TW_ST_DATA_ACK: | 
					
						
							|  |  |  |       // master has addressed this device as a slave transmitter and is
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							|  |  |  |       // requesting data.
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							|  |  |  |       TWDR = i2c_slave_buffer[slave_buffer_pos]; | 
					
						
							|  |  |  |       BUFFER_POS_INC(); | 
					
						
							|  |  |  |       break; | 
					
						
							|  |  |  | 
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							|  |  |  |     case TW_BUS_ERROR: // something went wrong, reset twi state
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							|  |  |  |       TWCR = 0; | 
					
						
							|  |  |  |     default: | 
					
						
							|  |  |  |       break; | 
					
						
							|  |  |  |   } | 
					
						
							|  |  |  |   // Reset everything, so we are ready for the next TWI interrupt
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							|  |  |  |   TWCR |= (1<<TWIE) | (1<<TWINT) | (ack<<TWEA) | (1<<TWEN); | 
					
						
							|  |  |  | } | 
					
						
							|  |  |  | #endif
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