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					40 lines
				
				1.1 KiB
			
		
		
			
		
	
	
					40 lines
				
				1.1 KiB
			|   
											11 years ago
										 | mbed fix for Infinity | ||
|  | ===================== | ||
|  | Without linker script patch it doesn't place vector table in final binary. | ||
|  | And clock is configured to 48MHz using internal clock reference and FLL multiplication. | ||
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 | ||
|  | mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/system_MK20D5.c | ||
|  |     Fix SystemInit: clock setup for internal clock. Inifinity has no external Xtal. | ||
|  | 
 | ||
|  | mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/cmsis_nvic.c | ||
|  |     Fix NVIC vector address of firmware 0x1000 instead of 0x0 | ||
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 | ||
|  | mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/TOOLCHAIN_GCC_ARM/MK20D5.ld | ||
|  |     Fix memory map for Infinity bootloader | ||
|  |         Flash starts at 0x1000 | ||
|  |         No flash config bytes sector | ||
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 | ||
|  | USBDevice/USBDevice/USBHAL_KL25Z.cpp | ||
|  |     Fix USB clock setup, see below. | ||
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|  | 2015/01/04  Based on mbed-sdk @2f63fa7d78a26. | ||
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|  | Kinetis USB config | ||
|  | ================== | ||
|  | Clock source: Internal reference clock wth FLL | ||
|  |     SIM_SOPT[USBSRC] = 1(MCGPLLCLK/MCGFLLCLK) | ||
|  |     SIM_SOPT[PLLSEL] = 0(MCGFLLCLK) | ||
|  | 
 | ||
|  | Clock dividor: | ||
|  |     SIM_CLKDIV2[USBDIV] = 0 | ||
|  |     SIM_CLKDIV2[USBFAC] = 0 | ||
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 | ||
|  | Clock enable: | ||
|  |     SIM_SCGC4[USBOTG] = 1 | ||
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