|
|
|
|
@ -46,22 +46,18 @@ void XPROGTarget_EnableTargetPDI(void)
|
|
|
|
|
{
|
|
|
|
|
IsSending = false;
|
|
|
|
|
|
|
|
|
|
#if (ARCH == ARCH_AVR8)
|
|
|
|
|
/* Set Tx and XCK as outputs, Rx as input */
|
|
|
|
|
DDRD |= (1 << 5) | (1 << 3);
|
|
|
|
|
DDRD &= ~(1 << 2);
|
|
|
|
|
|
|
|
|
|
/* Set DATA line high for at least 90ns to disable /RESET functionality */
|
|
|
|
|
PORTD |= (1 << 3);
|
|
|
|
|
Delay_MS(1);
|
|
|
|
|
|
|
|
|
|
/* Set up the synchronous USART for XMEGA communications - 8 data bits, even parity, 2 stop bits */
|
|
|
|
|
UBRR1 = ((F_CPU / 2 / XPROG_HARDWARE_SPEED) - 1);
|
|
|
|
|
UCSR1B = (1 << TXEN1);
|
|
|
|
|
UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);
|
|
|
|
|
#elif (ARCH == ARCH_UC3)
|
|
|
|
|
// TODO: FIXME
|
|
|
|
|
#endif
|
|
|
|
|
/* Set Tx and XCK as outputs, Rx as input */
|
|
|
|
|
DDRD |= (1 << 5) | (1 << 3);
|
|
|
|
|
DDRD &= ~(1 << 2);
|
|
|
|
|
|
|
|
|
|
/* Set DATA line high for at least 90ns to disable /RESET functionality */
|
|
|
|
|
PORTD |= (1 << 3);
|
|
|
|
|
_delay_us(1);
|
|
|
|
|
|
|
|
|
|
/* Set up the synchronous USART for XMEGA communications - 8 data bits, even parity, 2 stop bits */
|
|
|
|
|
UBRR1 = ((F_CPU / 2 / XPROG_HARDWARE_SPEED) - 1);
|
|
|
|
|
UCSR1B = (1 << TXEN1);
|
|
|
|
|
UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);
|
|
|
|
|
|
|
|
|
|
/* Send two IDLEs of 12 bits each to enable PDI interface (need at least 16 idle bits) */
|
|
|
|
|
XPROGTarget_SendIdle();
|
|
|
|
|
@ -73,23 +69,19 @@ void XPROGTarget_EnableTargetTPI(void)
|
|
|
|
|
{
|
|
|
|
|
IsSending = false;
|
|
|
|
|
|
|
|
|
|
#if (ARCH == ARCH_AVR8)
|
|
|
|
|
/* Set /RESET line low for at least 400ns to enable TPI functionality */
|
|
|
|
|
AUX_LINE_DDR |= AUX_LINE_MASK;
|
|
|
|
|
AUX_LINE_PORT &= ~AUX_LINE_MASK;
|
|
|
|
|
Delay_MS(1);
|
|
|
|
|
/* Set /RESET line low for at least 400ns to enable TPI functionality */
|
|
|
|
|
AUX_LINE_DDR |= AUX_LINE_MASK;
|
|
|
|
|
AUX_LINE_PORT &= ~AUX_LINE_MASK;
|
|
|
|
|
_delay_us(1);
|
|
|
|
|
|
|
|
|
|
/* Set Tx and XCK as outputs, Rx as input */
|
|
|
|
|
DDRD |= (1 << 5) | (1 << 3);
|
|
|
|
|
DDRD &= ~(1 << 2);
|
|
|
|
|
/* Set Tx and XCK as outputs, Rx as input */
|
|
|
|
|
DDRD |= (1 << 5) | (1 << 3);
|
|
|
|
|
DDRD &= ~(1 << 2);
|
|
|
|
|
|
|
|
|
|
/* Set up the synchronous USART for TINY communications - 8 data bits, even parity, 2 stop bits */
|
|
|
|
|
UBRR1 = ((F_CPU / 2 / XPROG_HARDWARE_SPEED) - 1);
|
|
|
|
|
UCSR1B = (1 << TXEN1);
|
|
|
|
|
UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);
|
|
|
|
|
#elif (ARCH == ARCH_UC3)
|
|
|
|
|
// TODO: FIXME
|
|
|
|
|
#endif
|
|
|
|
|
/* Set up the synchronous USART for TINY communications - 8 data bits, even parity, 2 stop bits */
|
|
|
|
|
UBRR1 = ((F_CPU / 2 / XPROG_HARDWARE_SPEED) - 1);
|
|
|
|
|
UCSR1B = (1 << TXEN1);
|
|
|
|
|
UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);
|
|
|
|
|
|
|
|
|
|
/* Send two IDLEs of 12 bits each to enable TPI interface (need at least 16 idle bits) */
|
|
|
|
|
XPROGTarget_SendIdle();
|
|
|
|
|
@ -102,18 +94,14 @@ void XPROGTarget_DisableTargetPDI(void)
|
|
|
|
|
/* Switch to Rx mode to ensure that all pending transmissions are complete */
|
|
|
|
|
XPROGTarget_SetRxMode();
|
|
|
|
|
|
|
|
|
|
#if (ARCH == ARCH_AVR8)
|
|
|
|
|
/* Turn off receiver and transmitter of the USART, clear settings */
|
|
|
|
|
UCSR1A = ((1 << TXC1) | (1 << RXC1));
|
|
|
|
|
UCSR1B = 0;
|
|
|
|
|
UCSR1C = 0;
|
|
|
|
|
|
|
|
|
|
/* Tristate all pins */
|
|
|
|
|
DDRD &= ~((1 << 5) | (1 << 3));
|
|
|
|
|
PORTD &= ~((1 << 5) | (1 << 3) | (1 << 2));
|
|
|
|
|
#elif (ARCH == ARCH_UC3)
|
|
|
|
|
// TODO: FIXME
|
|
|
|
|
#endif
|
|
|
|
|
/* Turn off receiver and transmitter of the USART, clear settings */
|
|
|
|
|
UCSR1A = ((1 << TXC1) | (1 << RXC1));
|
|
|
|
|
UCSR1B = 0;
|
|
|
|
|
UCSR1C = 0;
|
|
|
|
|
|
|
|
|
|
/* Tristate all pins */
|
|
|
|
|
DDRD &= ~((1 << 5) | (1 << 3));
|
|
|
|
|
PORTD &= ~((1 << 5) | (1 << 3) | (1 << 2));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/** Disables the target's TPI interface, exits programming mode and starts the target's application. */
|
|
|
|
|
@ -122,22 +110,18 @@ void XPROGTarget_DisableTargetTPI(void)
|
|
|
|
|
/* Switch to Rx mode to ensure that all pending transmissions are complete */
|
|
|
|
|
XPROGTarget_SetRxMode();
|
|
|
|
|
|
|
|
|
|
#if (ARCH == ARCH_AVR8)
|
|
|
|
|
/* Turn off receiver and transmitter of the USART, clear settings */
|
|
|
|
|
UCSR1A |= (1 << TXC1) | (1 << RXC1);
|
|
|
|
|
UCSR1B = 0;
|
|
|
|
|
UCSR1C = 0;
|
|
|
|
|
|
|
|
|
|
/* Set all USART lines as inputs, tristate */
|
|
|
|
|
DDRD &= ~((1 << 5) | (1 << 3));
|
|
|
|
|
PORTD &= ~((1 << 5) | (1 << 3) | (1 << 2));
|
|
|
|
|
|
|
|
|
|
/* Tristate target /RESET line */
|
|
|
|
|
AUX_LINE_DDR &= ~AUX_LINE_MASK;
|
|
|
|
|
AUX_LINE_PORT &= ~AUX_LINE_MASK;
|
|
|
|
|
#elif (ARCH == ARCH_UC3)
|
|
|
|
|
// TODO: FIXME
|
|
|
|
|
#endif
|
|
|
|
|
/* Turn off receiver and transmitter of the USART, clear settings */
|
|
|
|
|
UCSR1A |= (1 << TXC1) | (1 << RXC1);
|
|
|
|
|
UCSR1B = 0;
|
|
|
|
|
UCSR1C = 0;
|
|
|
|
|
|
|
|
|
|
/* Set all USART lines as inputs, tristate */
|
|
|
|
|
DDRD &= ~((1 << 5) | (1 << 3));
|
|
|
|
|
PORTD &= ~((1 << 5) | (1 << 3) | (1 << 2));
|
|
|
|
|
|
|
|
|
|
/* Tristate target /RESET line */
|
|
|
|
|
AUX_LINE_DDR &= ~AUX_LINE_MASK;
|
|
|
|
|
AUX_LINE_PORT &= ~AUX_LINE_MASK;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/** Sends a byte via the USART.
|
|
|
|
|
@ -150,14 +134,10 @@ void XPROGTarget_SendByte(const uint8_t Byte)
|
|
|
|
|
if (!(IsSending))
|
|
|
|
|
XPROGTarget_SetTxMode();
|
|
|
|
|
|
|
|
|
|
#if (ARCH == ARCH_AVR8)
|
|
|
|
|
/* Wait until there is space in the hardware Tx buffer before writing */
|
|
|
|
|
while (!(UCSR1A & (1 << UDRE1)));
|
|
|
|
|
UCSR1A |= (1 << TXC1);
|
|
|
|
|
UDR1 = Byte;
|
|
|
|
|
#elif (ARCH == ARCH_UC3)
|
|
|
|
|
// TODO: FIXME
|
|
|
|
|
#endif
|
|
|
|
|
/* Wait until there is space in the hardware Tx buffer before writing */
|
|
|
|
|
while (!(UCSR1A & (1 << UDRE1)));
|
|
|
|
|
UCSR1A |= (1 << TXC1);
|
|
|
|
|
UDR1 = Byte;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/** Receives a byte via the software USART, blocking until data is received.
|
|
|
|
|
@ -170,15 +150,10 @@ uint8_t XPROGTarget_ReceiveByte(void)
|
|
|
|
|
if (IsSending)
|
|
|
|
|
XPROGTarget_SetRxMode();
|
|
|
|
|
|
|
|
|
|
#if (ARCH == ARCH_AVR8)
|
|
|
|
|
/* Wait until a byte has been received before reading */
|
|
|
|
|
while (!(UCSR1A & (1 << RXC1)) && !(TimeoutExpired));
|
|
|
|
|
/* Wait until a byte has been received before reading */
|
|
|
|
|
while (!(UCSR1A & (1 << RXC1)) && !(TimeoutExpired));
|
|
|
|
|
|
|
|
|
|
return UDR1;
|
|
|
|
|
#elif (ARCH == ARCH_UC3)
|
|
|
|
|
// TODO: FIXME
|
|
|
|
|
return 0;
|
|
|
|
|
#endif
|
|
|
|
|
return UDR1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/** Sends an IDLE via the USART to the attached target, consisting of a full frame of idle bits. */
|
|
|
|
|
@ -188,52 +163,40 @@ void XPROGTarget_SendIdle(void)
|
|
|
|
|
if (!(IsSending))
|
|
|
|
|
XPROGTarget_SetTxMode();
|
|
|
|
|
|
|
|
|
|
#if (ARCH == ARCH_AVR8)
|
|
|
|
|
/* Need to do nothing for a full frame to send an IDLE */
|
|
|
|
|
for (uint8_t i = 0; i < BITS_IN_USART_FRAME; i++)
|
|
|
|
|
{
|
|
|
|
|
/* Wait for a full cycle of the clock */
|
|
|
|
|
while (PIND & (1 << 5));
|
|
|
|
|
while (!(PIND & (1 << 5)));
|
|
|
|
|
}
|
|
|
|
|
#elif (ARCH == ARCH_UC3)
|
|
|
|
|
// TODO: FIXME
|
|
|
|
|
#endif
|
|
|
|
|
/* Need to do nothing for a full frame to send an IDLE */
|
|
|
|
|
for (uint8_t i = 0; i < BITS_IN_USART_FRAME; i++)
|
|
|
|
|
{
|
|
|
|
|
/* Wait for a full cycle of the clock */
|
|
|
|
|
while (PIND & (1 << 5));
|
|
|
|
|
while (!(PIND & (1 << 5)));
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void XPROGTarget_SetTxMode(void)
|
|
|
|
|
{
|
|
|
|
|
#if (ARCH == ARCH_AVR8)
|
|
|
|
|
/* Wait for a full cycle of the clock */
|
|
|
|
|
while (PIND & (1 << 5));
|
|
|
|
|
while (!(PIND & (1 << 5)));
|
|
|
|
|
/* Wait for a full cycle of the clock */
|
|
|
|
|
while (PIND & (1 << 5));
|
|
|
|
|
while (!(PIND & (1 << 5)));
|
|
|
|
|
|
|
|
|
|
PORTD |= (1 << 3);
|
|
|
|
|
DDRD |= (1 << 3);
|
|
|
|
|
PORTD |= (1 << 3);
|
|
|
|
|
DDRD |= (1 << 3);
|
|
|
|
|
|
|
|
|
|
UCSR1B &= ~(1 << RXEN1);
|
|
|
|
|
UCSR1B |= (1 << TXEN1);
|
|
|
|
|
#elif (ARCH == ARCH_UC3)
|
|
|
|
|
// TODO: FIXME
|
|
|
|
|
#endif
|
|
|
|
|
UCSR1B &= ~(1 << RXEN1);
|
|
|
|
|
UCSR1B |= (1 << TXEN1);
|
|
|
|
|
|
|
|
|
|
IsSending = true;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void XPROGTarget_SetRxMode(void)
|
|
|
|
|
{
|
|
|
|
|
#if (ARCH == ARCH_AVR8)
|
|
|
|
|
while (!(UCSR1A & (1 << TXC1)));
|
|
|
|
|
UCSR1A |= (1 << TXC1);
|
|
|
|
|
|
|
|
|
|
UCSR1B &= ~(1 << TXEN1);
|
|
|
|
|
UCSR1B |= (1 << RXEN1);
|
|
|
|
|
|
|
|
|
|
DDRD &= ~(1 << 3);
|
|
|
|
|
PORTD &= ~(1 << 3);
|
|
|
|
|
#elif (ARCH == ARCH_UC3)
|
|
|
|
|
// TODO: FIXME
|
|
|
|
|
#endif
|
|
|
|
|
while (!(UCSR1A & (1 << TXC1)));
|
|
|
|
|
UCSR1A |= (1 << TXC1);
|
|
|
|
|
|
|
|
|
|
UCSR1B &= ~(1 << TXEN1);
|
|
|
|
|
UCSR1B |= (1 << RXEN1);
|
|
|
|
|
|
|
|
|
|
DDRD &= ~(1 << 3);
|
|
|
|
|
PORTD &= ~(1 << 3);
|
|
|
|
|
|
|
|
|
|
IsSending = false;
|
|
|
|
|
}
|
|
|
|
|
|
Dean Camera
15 years ago