From c15eaa5dae5b8913d9401f0ad508494a6b66744a Mon Sep 17 00:00:00 2001 From: Dean Camera Date: Wed, 12 Oct 2011 02:27:22 +0000 Subject: [PATCH] When automatic PLL management mode is enabled on the U4 series AVR8 chips, the PLL is now configured for 48MHz and not a divided 96MHz, to lower power consumption and to keep the system within the datasheet specs for 3.3V operation (thanks to Scott Vitale). --- LUFA/Drivers/USB/Core/AVR8/USBController_AVR8.c | 2 +- LUFA/ManPages/ChangeLog.txt | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/LUFA/Drivers/USB/Core/AVR8/USBController_AVR8.c b/LUFA/Drivers/USB/Core/AVR8/USBController_AVR8.c index 571ab6c8a6..9f688db06e 100644 --- a/LUFA/Drivers/USB/Core/AVR8/USBController_AVR8.c +++ b/LUFA/Drivers/USB/Core/AVR8/USBController_AVR8.c @@ -68,7 +68,7 @@ void USB_Init( if (!(USB_Options & USB_OPT_MANUAL_PLL)) { #if defined(USB_SERIES_4_AVR) - PLLFRQ = ((1 << PLLUSB) | (1 << PDIV3) | (1 << PDIV1)); + PLLFRQ = (1 << PDIV2); #endif } diff --git a/LUFA/ManPages/ChangeLog.txt b/LUFA/ManPages/ChangeLog.txt index 55e12414c6..b3bda78c93 100644 --- a/LUFA/ManPages/ChangeLog.txt +++ b/LUFA/ManPages/ChangeLog.txt @@ -15,7 +15,8 @@ * * Changed: * - Core: - * - None + * - When automatic PLL management mode is enabled on the U4 series AVR8 chips, the PLL is now configured for 48MHz and not + * a divided 96MHz, to lower power consumption and to keep the system within the datasheet specs for 3.3V operation (thanks to Scott Vitale) * - Library Applications: * - None *