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326 lines
12 KiB
326 lines
12 KiB
/*
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LUFA Library
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Copyright (C) Dean Camera, 2009.
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dean [at] fourwalledcubicle [dot] com
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www.fourwalledcubicle.com
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*/
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/*
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Copyright 2009 Dean Camera (dean [at] fourwalledcubicle [dot] com)
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Permission to use, copy, modify, and distribute this software
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and its documentation for any purpose and without fee is hereby
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granted, provided that the above copyright notice appear in all
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copies and that both that the copyright notice and this
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permission notice and warranty disclaimer appear in supporting
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documentation, and that the name of the author not be used in
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advertising or publicity pertaining to distribution of the
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software without specific, written prior permission.
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The author disclaim all warranties with regard to this
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software, including all implied warranties of merchantability
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and fitness. In no event shall the author be liable for any
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special, indirect or consequential damages or any damages
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whatsoever resulting from loss of use, data or profits, whether
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in an action of contract, negligence or other tortious action,
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arising out of or in connection with the use or performance of
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this software.
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*/
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/** \file
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*
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* Target-related functions for the target's NVM module.
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*/
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#define INCLUDE_FROM_NVMTARGET_C
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#include "NVMTarget.h"
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#if defined(ENABLE_PDI_PROTOCOL) || defined(__DOXYGEN__)
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/** Sends the given NVM register address to the target.
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*
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* \param[in] Register NVM register whose absolute address is to be sent
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*/
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void NVMTarget_SendNVMRegAddress(uint8_t Register)
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{
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/* Determine the absolute register address from the NVM base memory address and the NVM register address */
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uint32_t Address = XPROG_Param_NVMBase | Register;
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/* Send the calculated 32-bit address to the target, LSB first */
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PDITarget_SendByte(Address & 0xFF);
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PDITarget_SendByte(Address >> 8);
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PDITarget_SendByte(Address >> 16);
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PDITarget_SendByte(Address >> 24);
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}
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/** Sends the given 32-bit absolute address to the target.
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*
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* \param[in] AbsoluteAddress Absolute address to send to the target
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*/
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void NVMTarget_SendAddress(uint32_t AbsoluteAddress)
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{
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/* Send the given 32-bit address to the target, LSB first */
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PDITarget_SendByte(AbsoluteAddress & 0xFF);
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PDITarget_SendByte(AbsoluteAddress >> 8);
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PDITarget_SendByte(AbsoluteAddress >> 16);
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PDITarget_SendByte(AbsoluteAddress >> 24);
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}
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/** Waits while the target's NVM controller is busy performing an operation, exiting if the
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* timeout period expires.
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*
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* \return Boolean true if the NVM controller became ready within the timeout period, false otherwise
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*/
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bool NVMTarget_WaitWhileNVMControllerBusy(void)
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{
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TCNT0 = 0;
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/* Poll the NVM STATUS register while the NVM controller is busy */
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while (TCNT0 < NVM_BUSY_TIMEOUT_MS)
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{
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/* Send a LDS command to read the NVM STATUS register to check the BUSY flag */
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PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));
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NVMTarget_SendNVMRegAddress(NVM_REG_STATUS);
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/* Check to see if the BUSY flag is still set */
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if (!(PDITarget_ReceiveByte() & (1 << 7)))
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return true;
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}
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return false;
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}
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/** Retrieves the CRC value of the given memory space.
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*
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* \param[in] CRCCommand NVM CRC command to issue to the target
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* \param[out] CRCDest CRC Destination when read from the target
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*
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* \return Boolean true if the command sequence complete successfully
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*/
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bool NVMTarget_GetMemoryCRC(uint8_t CRCCommand, uint32_t* CRCDest)
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{
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/* Wait until the NVM controller is no longer busy */
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if (!(NVMTarget_WaitWhileNVMControllerBusy()))
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return false;
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/* Set the NVM command to the correct CRC read command */
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PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
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NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
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PDITarget_SendByte(CRCCommand);
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/* Set CMDEX bit in NVM CTRLA register to start the CRC generation */
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PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
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NVMTarget_SendNVMRegAddress(NVM_REG_CTRLA);
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PDITarget_SendByte(1 << 0);
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/* Wait until the NVM bus is ready again */
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if (!(PDITarget_WaitWhileNVMBusBusy()))
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return false;
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/* Wait until the NVM controller is no longer busy */
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if (!(NVMTarget_WaitWhileNVMControllerBusy()))
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return false;
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*CRCDest = 0;
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/* Read the first generated CRC byte value */
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PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));
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NVMTarget_SendNVMRegAddress(NVM_REG_DAT0);
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*CRCDest = PDITarget_ReceiveByte();
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/* Read the second generated CRC byte value */
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PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));
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NVMTarget_SendNVMRegAddress(NVM_REG_DAT1);
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*CRCDest |= ((uint16_t)PDITarget_ReceiveByte() << 8);
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/* Read the third generated CRC byte value */
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PDITarget_SendByte(PDI_CMD_LDS | (PDI_DATSIZE_4BYTES << 2));
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NVMTarget_SendNVMRegAddress(NVM_REG_DAT2);
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*CRCDest |= ((uint32_t)PDITarget_ReceiveByte() << 16);
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return true;
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}
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/** Reads memory from the target's memory spaces.
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*
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* \param[in] ReadAddress Start address to read from within the target's address space
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* \param[out] ReadBuffer Buffer to store read data into
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* \param[in] ReadSize Number of bytes to read
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*
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* \return Boolean true if the command sequence complete successfully
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*/
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bool NVMTarget_ReadMemory(uint32_t ReadAddress, uint8_t* ReadBuffer, uint16_t ReadSize)
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{
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/* Wait until the NVM controller is no longer busy */
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if (!(NVMTarget_WaitWhileNVMControllerBusy()))
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return false;
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/* Send the READNVM command to the NVM controller for reading of an arbitrary location */
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PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
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NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
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PDITarget_SendByte(NVM_CMD_READNVM);
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/* Load the PDI pointer register with the start address we want to read from */
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PDITarget_SendByte(PDI_CMD_ST | (PDI_POINTER_DIRECT << 2) | PDI_DATSIZE_4BYTES);
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NVMTarget_SendAddress(ReadAddress);
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/* Send the REPEAT command with the specified number of bytes to read */
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PDITarget_SendByte(PDI_CMD_REPEAT | PDI_DATSIZE_1BYTE);
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PDITarget_SendByte(ReadSize - 1);
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/* Send a LD command with indirect access and postincrement to read out the bytes */
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PDITarget_SendByte(PDI_CMD_LD | (PDI_POINTER_INDIRECT_PI << 2) | PDI_DATSIZE_1BYTE);
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for (uint16_t i = 0; i < ReadSize; i++)
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*(ReadBuffer++) = PDITarget_ReceiveByte();
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return true;
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}
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/** Writes byte addressed memory to the target's memory spaces.
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*
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* \param[in] WriteCommand Command to send to the device to write each memory byte
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* \param[in] WriteAddress Start address to write to within the target's address space
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* \param[in] WriteBuffer Buffer to source data from
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*
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* \return Boolean true if the command sequence complete successfully
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*/
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bool NVMTarget_WriteByteMemory(uint8_t WriteCommand, uint32_t WriteAddress, uint8_t* WriteBuffer)
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{
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/* Wait until the NVM controller is no longer busy */
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if (!(NVMTarget_WaitWhileNVMControllerBusy()))
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return false;
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/* Send the memory write command to the target */
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PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
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NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
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PDITarget_SendByte(WriteCommand);
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/* Send new memory byte to the memory to the target */
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PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
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NVMTarget_SendAddress(WriteAddress++);
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PDITarget_SendByte(*(WriteBuffer++));
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return true;
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}
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/** Writes page addressed memory to the target's memory spaces.
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*
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* \param[in] WriteBuffCommand Command to send to the device to write a byte to the memory page buffer
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* \param[in] EraseBuffCommand Command to send to the device to erase the memory page buffer
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* \param[in] WritePageCommand Command to send to the device to write the page buffer to the destination memory
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* \param[in] PageMode Bitfield indicating what operations need to be executed on the specified page
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* \param[in] WriteAddress Start address to write the page data to within the target's address space
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* \param[in] WriteBuffer Buffer to source data from
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* \param[in] WriteSize Number of bytes to write
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*
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* \return Boolean true if the command sequence complete successfully
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*/
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bool NVMTarget_WritePageMemory(uint8_t WriteBuffCommand, uint8_t EraseBuffCommand, uint8_t WritePageCommand,
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uint8_t PageMode, uint32_t WriteAddress, uint8_t* WriteBuffer, uint16_t WriteSize)
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{
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if (PageMode & XPRG_PAGEMODE_ERASE)
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{
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/* Wait until the NVM controller is no longer busy */
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if (!(NVMTarget_WaitWhileNVMControllerBusy()))
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return false;
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/* Send the memory buffer erase command to the target */
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PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
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NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
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PDITarget_SendByte(EraseBuffCommand);
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/* Set CMDEX bit in NVM CTRLA register to start the buffer erase */
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PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
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NVMTarget_SendNVMRegAddress(NVM_REG_CTRLA);
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PDITarget_SendByte(1 << 0);
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}
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if (WriteSize)
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{
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/* Wait until the NVM controller is no longer busy */
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if (!(NVMTarget_WaitWhileNVMControllerBusy()))
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return false;
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/* Send the memory buffer write command to the target */
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PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
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NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
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PDITarget_SendByte(WriteBuffCommand);
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/* Load the PDI pointer register with the start address we want to write to */
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PDITarget_SendByte(PDI_CMD_ST | (PDI_POINTER_DIRECT << 2) | PDI_DATSIZE_4BYTES);
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NVMTarget_SendAddress(WriteAddress);
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/* Send the REPEAT command with the specified number of bytes to write */
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PDITarget_SendByte(PDI_CMD_REPEAT | PDI_DATSIZE_1BYTE);
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PDITarget_SendByte(WriteSize - 1);
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/* Send a ST command with indirect access and postincrement to write the bytes */
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PDITarget_SendByte(PDI_CMD_ST | (PDI_POINTER_INDIRECT_PI << 2) | PDI_DATSIZE_1BYTE);
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for (uint16_t i = 0; i < WriteSize; i++)
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PDITarget_SendByte(*(WriteBuffer++));
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}
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if (PageMode & XPRG_PAGEMODE_WRITE)
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{
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/* Wait until the NVM controller is no longer busy */
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if (!(NVMTarget_WaitWhileNVMControllerBusy()))
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return false;
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/* Send the memory write command to the target */
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PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
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NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
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PDITarget_SendByte(WritePageCommand);
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/* Send the address of the first page location to write the memory page */
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PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
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NVMTarget_SendAddress(WriteAddress);
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PDITarget_SendByte(0x00);
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}
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return true;
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}
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/** Erases a specific memory space of the target.
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*
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* \param[in] EraseCommand NVM erase command to send to the device
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* \param[in] Address Address inside the memory space to erase
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*
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* \return Boolean true if the command sequence complete successfully
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*/
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bool NVMTarget_EraseMemory(uint8_t EraseCommand, uint32_t Address)
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{
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/* Wait until the NVM controller is no longer busy */
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if (!(NVMTarget_WaitWhileNVMControllerBusy()))
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return false;
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/* Send the memory erase command to the target */
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PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
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NVMTarget_SendNVMRegAddress(NVM_REG_CMD);
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PDITarget_SendByte(EraseCommand);
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/* Chip erase is handled separately, since it's procedure is different to other erase types */
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if (EraseCommand == NVM_CMD_CHIPERASE)
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{
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/* Set CMDEX bit in NVM CTRLA register to start the chip erase */
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PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
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NVMTarget_SendNVMRegAddress(NVM_REG_CTRLA);
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PDITarget_SendByte(1 << 0);
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}
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else
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{
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/* Other erase modes just need us to address a byte within the target memory space */
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PDITarget_SendByte(PDI_CMD_STS | (PDI_DATSIZE_4BYTES << 2));
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NVMTarget_SendAddress(Address);
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PDITarget_SendByte(0x00);
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}
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/* Wait until the NVM bus is ready again */
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if (!(PDITarget_WaitWhileNVMBusBusy()))
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return false;
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return true;
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}
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#endif
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