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286 lines
7.5 KiB
286 lines
7.5 KiB
3 years ago
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// See LICENSE for license details
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#ifndef ENTRY_S
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#define ENTRY_S
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#include "riscv_encoding.h"
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#include "riscv_bits.h"
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#include "n200_eclic.h"
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#include "n200_timer.h"
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###############################################
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###############################################
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# Disable Interrupt
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#
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.macro DISABLE_MIE
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csrc CSR_MSTATUS, MSTATUS_MIE
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.endm
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###############################################
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###############################################
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#Save caller registers
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.macro SAVE_CONTEXT
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#ifdef __riscv_flen
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#if (__riscv_flen==64 )
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addi sp, sp, -20*REGBYTES - 20*FPREGBYTES
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#else
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addi sp, sp, -20*REGBYTES
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#endif
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#else
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addi sp, sp, -20*REGBYTES
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#endif
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STORE x1, 0*REGBYTES(sp)
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STORE x4, 1*REGBYTES(sp)
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STORE x5, 2*REGBYTES(sp)
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STORE x6, 3*REGBYTES(sp)
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STORE x7, 4*REGBYTES(sp)
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STORE x10, 5*REGBYTES(sp)
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STORE x11, 6*REGBYTES(sp)
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STORE x12, 7*REGBYTES(sp)
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STORE x13, 8*REGBYTES(sp)
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STORE x14, 9*REGBYTES(sp)
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STORE x15, 10*REGBYTES(sp)
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#ifndef __riscv_32e
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STORE x16, 11*REGBYTES(sp)
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STORE x17, 12*REGBYTES(sp)
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STORE x28, 13*REGBYTES(sp)
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STORE x29, 14*REGBYTES(sp)
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STORE x30, 15*REGBYTES(sp)
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STORE x31, 16*REGBYTES(sp)
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#endif
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#ifdef __riscv_flen
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#if (__riscv_flen == 64)
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FPSTORE f0, (20*REGBYTES + 0*FPREGBYTES)(sp)
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FPSTORE f1, (20*REGBYTES + 1*FPREGBYTES)(sp)
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FPSTORE f2, (20*REGBYTES + 2*FPREGBYTES)(sp)
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FPSTORE f3, (20*REGBYTES + 3*FPREGBYTES)(sp)
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FPSTORE f4, (20*REGBYTES + 4*FPREGBYTES)(sp)
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FPSTORE f5, (20*REGBYTES + 5*FPREGBYTES)(sp)
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FPSTORE f6, (20*REGBYTES + 6*FPREGBYTES)(sp)
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FPSTORE f7, (20*REGBYTES + 7*FPREGBYTES)(sp)
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FPSTORE f10, (20*REGBYTES + 8*FPREGBYTES)(sp)
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FPSTORE f11, (20*REGBYTES + 9*FPREGBYTES)(sp)
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FPSTORE f12, (20*REGBYTES + 10*FPREGBYTES)(sp)
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FPSTORE f13, (20*REGBYTES + 11*FPREGBYTES)(sp)
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FPSTORE f14, (20*REGBYTES + 12*FPREGBYTES)(sp)
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FPSTORE f15, (20*REGBYTES + 13*FPREGBYTES)(sp)
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FPSTORE f16, (20*REGBYTES + 14*FPREGBYTES)(sp)
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FPSTORE f17, (20*REGBYTES + 15*FPREGBYTES)(sp)
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FPSTORE f28, (20*REGBYTES + 16*FPREGBYTES)(sp)
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FPSTORE f29, (20*REGBYTES + 17*FPREGBYTES)(sp)
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FPSTORE f30, (20*REGBYTES + 18*FPREGBYTES)(sp)
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FPSTORE f31, (20*REGBYTES + 19*FPREGBYTES)(sp)
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#endif
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#endif
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.endm
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###############################################
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###############################################
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#restore caller registers
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.macro RESTORE_CONTEXT
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LOAD x1, 0*REGBYTES(sp)
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LOAD x4, 1*REGBYTES(sp)
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LOAD x5, 2*REGBYTES(sp)
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LOAD x6, 3*REGBYTES(sp)
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LOAD x7, 4*REGBYTES(sp)
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LOAD x10, 5*REGBYTES(sp)
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LOAD x11, 6*REGBYTES(sp)
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LOAD x12, 7*REGBYTES(sp)
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LOAD x13, 8*REGBYTES(sp)
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LOAD x14, 9*REGBYTES(sp)
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LOAD x15, 10*REGBYTES(sp)
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#ifndef __riscv_32e
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LOAD x16, 11*REGBYTES(sp)
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LOAD x17, 12*REGBYTES(sp)
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LOAD x28, 13*REGBYTES(sp)
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LOAD x29, 14*REGBYTES(sp)
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LOAD x30, 15*REGBYTES(sp)
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LOAD x31, 16*REGBYTES(sp)
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#endif
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#ifdef __riscv_flen
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#if (__riscv_flen==64)
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/* Restore fp caller registers */
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FPLOAD f0, (20*REGBYTES + 0*FPREGBYTES)(sp)
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FPLOAD f1, (20*REGBYTES + 1*FPREGBYTES)(sp)
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FPLOAD f2, (20*REGBYTES + 2*FPREGBYTES)(sp)
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FPLOAD f3, (20*REGBYTES + 3*FPREGBYTES)(sp)
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FPLOAD f4, (20*REGBYTES + 4*FPREGBYTES)(sp)
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FPLOAD f5, (20*REGBYTES + 5*FPREGBYTES)(sp)
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FPLOAD f6, (20*REGBYTES + 6*FPREGBYTES)(sp)
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FPLOAD f7, (20*REGBYTES + 7*FPREGBYTES)(sp)
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FPLOAD f10, (20*REGBYTES + 8*FPREGBYTES)(sp)
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FPLOAD f11, (20*REGBYTES + 9*FPREGBYTES)(sp)
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FPLOAD f12, (20*REGBYTES + 10*FPREGBYTES)(sp)
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FPLOAD f13, (20*REGBYTES + 11*FPREGBYTES)(sp)
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FPLOAD f14, (20*REGBYTES + 12*FPREGBYTES)(sp)
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FPLOAD f15, (20*REGBYTES + 13*FPREGBYTES)(sp)
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FPLOAD f16, (20*REGBYTES + 14*FPREGBYTES)(sp)
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FPLOAD f17, (20*REGBYTES + 15*FPREGBYTES)(sp)
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FPLOAD f28, (20*REGBYTES + 16*FPREGBYTES)(sp)
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FPLOAD f29, (20*REGBYTES + 17*FPREGBYTES)(sp)
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FPLOAD f30, (20*REGBYTES + 18*FPREGBYTES)(sp)
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FPLOAD f31, (20*REGBYTES + 19*FPREGBYTES)(sp)
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#endif
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#endif
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#ifdef __riscv_flen
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#if(__riscv_flen == 64 )
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addi sp, sp, 20*REGBYTES + 20*FPREGBYTES
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#else
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addi sp, sp, 20*REGBYTES
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#endif
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#else
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// De-allocate the stack space
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addi sp, sp, 20*REGBYTES
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#endif
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.endm
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###############################################
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###############################################
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#restore caller registers
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.macro RESTORE_CONTEXT_EXCPT_X5
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LOAD x1, 0*REGBYTES(sp)
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LOAD x6, 2*REGBYTES(sp)
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LOAD x7, 3*REGBYTES(sp)
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LOAD x10, 4*REGBYTES(sp)
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LOAD x11, 5*REGBYTES(sp)
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LOAD x12, 6*REGBYTES(sp)
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LOAD x13, 7*REGBYTES(sp)
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LOAD x14, 8*REGBYTES(sp)
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LOAD x15, 9*REGBYTES(sp)
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#ifndef __riscv_32e
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LOAD x16, 10*REGBYTES(sp)
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LOAD x17, 11*REGBYTES(sp)
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LOAD x28, 12*REGBYTES(sp)
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LOAD x29, 13*REGBYTES(sp)
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LOAD x30, 14*REGBYTES(sp)
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LOAD x31, 15*REGBYTES(sp)
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#endif
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.endm
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###############################################
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###############################################
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#restore caller registers
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.macro RESTORE_CONTEXT_ONLY_X5
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LOAD x5, 1*REGBYTES(sp)
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.endm
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###############################################
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###############################################
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# Save the mepc and mstatus
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#
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.macro SAVE_EPC_STATUS
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csrr x5, CSR_MEPC
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STORE x5, 16*REGBYTES(sp)
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csrr x5, CSR_MSTATUS
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STORE x5, 17*REGBYTES(sp)
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csrr x5, CSR_MSUBM
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STORE x5, 18*REGBYTES(sp)
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.endm
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###############################################
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###############################################
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# Restore the mepc and mstatus
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#
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.macro RESTORE_EPC_STATUS
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LOAD x5, 16*REGBYTES(sp)
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csrw CSR_MEPC, x5
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LOAD x5, 17*REGBYTES(sp)
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csrw CSR_MSTATUS, x5
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LOAD x5, 18*REGBYTES(sp)
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csrw CSR_MSUBM, x5
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.endm
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###############################################
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###############################################
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// Trap entry point
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//
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.section .text.trap
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.align 6// In CLIC mode, the trap entry must be 64bytes aligned
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.global trap_entry
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.weak trap_entry
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trap_entry:
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// Allocate the stack space
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// addi sp, sp, -19*REGBYTES
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// Save the caller saving registers (context)
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SAVE_CONTEXT
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// Save the MEPC/Mstatus/Msubm reg
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SAVE_EPC_STATUS
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// Set the function argument
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csrr a0, mcause
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mv a1, sp
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// Call the function
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call handle_trap
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// Restore the MEPC/Mstatus/Msubm reg
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RESTORE_EPC_STATUS
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// Restore the caller saving registers (context)
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RESTORE_CONTEXT
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// De-allocate the stack space
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// addi sp, sp, 19*REGBYTES
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// Return to regular code
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mret
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###############################################
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###############################################
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// IRQ entry point
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//
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.section .text.irq
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.align 2
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.global irq_entry
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.weak irq_entry
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irq_entry: // -------------> This label will be set to MTVT2 register
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// Allocate the stack space
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SAVE_CONTEXT// Save 16 regs
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//------This special CSR read operation, which is actually use mcause as operand to directly store it to memory
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csrrwi x0, CSR_PUSHMCAUSE, 17
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//------This special CSR read operation, which is actually use mepc as operand to directly store it to memory
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csrrwi x0, CSR_PUSHMEPC, 18
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//------This special CSR read operation, which is actually use Msubm as operand to directly store it to memory
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csrrwi x0, CSR_PUSHMSUBM, 19
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service_loop:
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//------This special CSR read/write operation, which is actually Claim the CLIC to find its pending highest
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// ID, if the ID is not 0, then automatically enable the mstatus.MIE, and jump to its vector-entry-label, and
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// update the link register
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csrrw ra, CSR_JALMNXTI, ra
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//RESTORE_CONTEXT_EXCPT_X5
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#---- Critical section with interrupts disabled -----------------------
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DISABLE_MIE # Disable interrupts
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LOAD x5, 19*REGBYTES(sp)
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csrw CSR_MSUBM, x5
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LOAD x5, 18*REGBYTES(sp)
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csrw CSR_MEPC, x5
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LOAD x5, 17*REGBYTES(sp)
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csrw CSR_MCAUSE, x5
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RESTORE_CONTEXT
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// Return to regular code
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mret
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#endif
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