Ivan Olenichev
11 months ago
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/**
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****************************************************************************** |
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* @file stm32f4xx.h |
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* @author MCD Application Team |
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* @version V2.3.2 |
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* @date 26-June-2015 |
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* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File. |
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* |
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* The file is the unique include file that the application programmer |
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* is using in the C source code, usually in main.c. This file contains: |
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* - Configuration section that allows to select: |
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* - The STM32F4xx device used in the target application |
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* - To use or not the peripheral’s drivers in application code(i.e. |
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* code will be based on direct access to peripheral’s registers |
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* rather than drivers API), this option is controlled by |
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* "#define USE_HAL_DRIVER" |
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* |
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****************************************************************************** |
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* @attention |
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* |
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* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
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* |
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* Redistribution and use in source and binary forms, with or without modification, |
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* are permitted provided that the following conditions are met: |
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* 1. Redistributions of source code must retain the above copyright notice, |
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* this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright notice, |
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* this list of conditions and the following disclaimer in the documentation |
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* and/or other materials provided with the distribution. |
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* 3. Neither the name of STMicroelectronics nor the names of its contributors |
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* may be used to endorse or promote products derived from this software |
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* without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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* |
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****************************************************************************** |
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*/ |
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|
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/** @addtogroup CMSIS
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* @{ |
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*/ |
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/** @addtogroup stm32f4xx
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* @{ |
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*/ |
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#ifndef __STM32F4xx_H |
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#define __STM32F4xx_H |
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#ifdef __cplusplus |
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extern "C" { |
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#endif /* __cplusplus */ |
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/** @addtogroup Library_configuration_section
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* @{ |
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*/ |
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/**
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* @brief STM32 Family |
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*/ |
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#if !defined (STM32F4) |
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#define STM32F4 |
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#endif /* STM32F4 */ |
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/* Uncomment the line below according to the target STM32 device used in your
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application |
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*/ |
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#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \ |
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!defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \ |
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!defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE) && !defined (STM32F446xx) |
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/* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */ |
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/* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */ |
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/* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */ |
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/* #define STM32F417xx */ /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */ |
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/* #define STM32F427xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */ |
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/* #define STM32F437xx */ /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */ |
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/* #define STM32F429xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG,
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STM32F439NI, STM32F429IG and STM32F429II Devices */ |
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/* #define STM32F439xx */ /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG,
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STM32F439NI, STM32F439IG and STM32F439II Devices */ |
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/* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */ |
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/* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */ |
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/* #define STM32F411xE */ /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */ |
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/* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC,
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and STM32F446ZE Devices */ |
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#endif |
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/* Tip: To avoid modifying this file each time you need to switch between these
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devices, you can define the device in your toolchain compiler preprocessor. |
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*/ |
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#if !defined (USE_HAL_DRIVER) |
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/**
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* @brief Comment the line below if you will not use the peripherals drivers. |
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In this case, these drivers will not be included and the application code will |
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be based on direct access to peripherals registers |
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*/ |
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/*#define USE_HAL_DRIVER */ |
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#endif /* USE_HAL_DRIVER */ |
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/**
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* @brief CMSIS Device version number V2.3.2 |
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*/ |
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#define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ |
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#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ |
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#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ |
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#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ |
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#define __STM32F4xx_CMSIS_DEVICE_VERSION ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\ |
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|(__STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\ |
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|(__STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 << 8 )\ |
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|(__STM32F4xx_CMSIS_DEVICE_VERSION)) |
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/**
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* @} |
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*/ |
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/** @addtogroup Device_Included
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* @{ |
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*/ |
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#if defined(STM32F405xx) |
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#include "stm32f405xx.h" |
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#elif defined(STM32F415xx) |
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#include "stm32f415xx.h" |
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#elif defined(STM32F407xx) |
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#include "stm32f407xx.h" |
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#elif defined(STM32F417xx) |
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#include "stm32f417xx.h" |
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#elif defined(STM32F427xx) |
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#include "stm32f427xx.h" |
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#elif defined(STM32F437xx) |
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#include "stm32f437xx.h" |
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#elif defined(STM32F429xx) |
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#include "stm32f429xx.h" |
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#elif defined(STM32F439xx) |
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#include "stm32f439xx.h" |
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#elif defined(STM32F401xC) |
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#include "stm32f401xc.h" |
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#elif defined(STM32F401xE) |
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#include "stm32f401xe.h" |
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#elif defined(STM32F411xE) |
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#include "stm32f411xe.h" |
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#elif defined(STM32F446xx) |
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#include "stm32f446xx.h" |
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#else |
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#error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)" |
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#endif |
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/**
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* @} |
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*/ |
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/** @addtogroup Exported_types
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* @{ |
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*/ |
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typedef enum |
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{ |
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RESET = 0, |
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SET = !RESET |
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} FlagStatus, ITStatus; |
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typedef enum |
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{ |
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DISABLE = 0, |
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ENABLE = !DISABLE |
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} FunctionalState; |
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#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) |
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typedef enum |
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{ |
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ERROR = 0, |
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SUCCESS = !ERROR |
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} ErrorStatus; |
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/**
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* @} |
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*/ |
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/** @addtogroup Exported_macro
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* @{ |
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*/ |
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#define SET_BIT(REG, BIT) ((REG) |= (BIT)) |
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#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) |
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#define READ_BIT(REG, BIT) ((REG) & (BIT)) |
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#define CLEAR_REG(REG) ((REG) = (0x0)) |
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#define WRITE_REG(REG, VAL) ((REG) = (VAL)) |
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#define READ_REG(REG) ((REG)) |
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#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) |
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#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) |
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/**
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* @} |
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*/ |
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#if defined (USE_HAL_DRIVER) |
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#include "stm32f4xx_hal.h" |
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#endif /* USE_HAL_DRIVER */ |
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#ifdef __cplusplus |
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} |
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#endif /* __cplusplus */ |
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#endif /* __STM32F4xx_H */ |
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/**
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* @} |
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*/ |
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/**
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* @} |
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*/ |
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
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@ -0,0 +1,122 @@ |
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/**
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****************************************************************************** |
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* @file system_stm32f4xx.h |
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* @author MCD Application Team |
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* @version V2.3.2 |
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* @date 26-June-2015 |
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* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. |
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****************************************************************************** |
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* @attention |
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* |
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* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
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* |
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* Redistribution and use in source and binary forms, with or without modification, |
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* are permitted provided that the following conditions are met: |
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* 1. Redistributions of source code must retain the above copyright notice, |
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* this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright notice, |
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* this list of conditions and the following disclaimer in the documentation |
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* and/or other materials provided with the distribution. |
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* 3. Neither the name of STMicroelectronics nor the names of its contributors |
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* may be used to endorse or promote products derived from this software |
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* without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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* |
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****************************************************************************** |
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*/ |
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/** @addtogroup CMSIS
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* @{ |
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*/ |
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/** @addtogroup stm32f4xx_system
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* @{ |
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*/ |
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/**
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* @brief Define to prevent recursive inclusion |
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*/ |
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#ifndef __SYSTEM_STM32F4XX_H |
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#define __SYSTEM_STM32F4XX_H |
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#ifdef __cplusplus |
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extern "C" { |
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#endif |
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/** @addtogroup STM32F4xx_System_Includes
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* @{ |
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*/ |
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/**
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* @} |
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*/ |
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/** @addtogroup STM32F4xx_System_Exported_types
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* @{ |
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*/ |
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/* This variable is updated in three ways:
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1) by calling CMSIS function SystemCoreClockUpdate() |
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2) by calling HAL API function HAL_RCC_GetSysClockFreq() |
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3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency |
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Note: If you use this function to configure the system clock; then there |
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is no need to call the 2 first functions listed above, since SystemCoreClock |
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variable is updated automatically. |
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*/ |
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extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ |
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/**
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* @} |
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*/ |
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/** @addtogroup STM32F4xx_System_Exported_Constants
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* @{ |
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*/ |
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/**
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* @} |
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*/ |
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/** @addtogroup STM32F4xx_System_Exported_Macros
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* @{ |
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*/ |
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/**
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* @} |
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*/ |
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/** @addtogroup STM32F4xx_System_Exported_Functions
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* @{ |
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*/ |
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extern void SystemInit(void); |
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extern void SystemCoreClockUpdate(void); |
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/**
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* @} |
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*/ |
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#ifdef __cplusplus |
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} |
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#endif |
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#endif /*__SYSTEM_STM32F4XX_H */ |
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/**
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* @} |
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*/ |
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/**
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* @} |
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*/ |
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
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@ -0,0 +1,453 @@ |
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/** |
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****************************************************************************** |
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* @file startup_stm32f401xc.s |
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* @author MCD Application Team |
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* @version V2.2.0 |
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* @date 15-December-2014 |
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* @brief STM32F405xx Devices vector table for Atollic TrueSTUDIO toolchain. |
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* This module performs: |
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* - Set the initial SP |
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* - Set the initial PC == Reset_Handler, |
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* - Set the vector table entries with the exceptions ISR address |
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* - Branches to main in the C library (which eventually |
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* calls main()). |
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* After Reset the Cortex-M4 processor is in Thread mode, |
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* priority is Privileged, and the Stack is set to Main. |
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****************************************************************************** |
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* @attention |
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* |
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* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> |
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* |
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* Redistribution and use in source and binary forms, with or without modification, |
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* are permitted provided that the following conditions are met: |
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* 1. Redistributions of source code must retain the above copyright notice, |
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* this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright notice, |
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* this list of conditions and the following disclaimer in the documentation |
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* and/or other materials provided with the distribution. |
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* 3. Neither the name of STMicroelectronics nor the names of its contributors |
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* may be used to endorse or promote products derived from this software |
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* without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
|||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
|||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
|||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
|||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
|||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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* |
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****************************************************************************** |
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*/ |
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|
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.syntax unified |
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.cpu cortex-m4 |
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.fpu softvfp |
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.thumb |
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.global __Vectors |
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.global Default_Handler |
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/* start address for the initialization values of the .data section. |
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defined in linker script */ |
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.word __etext |
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/* start address for the .data section. defined in linker script */ |
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.word __data_start__ |
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/* end address for the .data section. defined in linker script */ |
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.word __data_end__ |
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/* start address for the .bss section. defined in linker script */ |
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.word __bss_start__ |
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/* end address for the .bss section. defined in linker script */ |
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.word __bss_end__ |
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/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ |
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/** |
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* @brief This is the code that gets called when the processor first |
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* starts execution following a reset event. Only the absolutely |
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* necessary set is performed, after which the application |
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* supplied main() routine is called. |
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* @param None |
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* @retval : None |
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*/ |
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.section .text.Reset_Handler |
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.weak Reset_Handler |
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.type Reset_Handler, %function |
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Reset_Handler: |
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ldr sp, =__StackTop /* set stack pointer */ |
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/* Copy the data segment initializers from flash to SRAM */ |
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movs r1, #0 |
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b LoopCopyDataInit |
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CopyDataInit: |
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ldr r3, =__etext |
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ldr r3, [r3, r1] |
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str r3, [r0, r1] |
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adds r1, r1, #4 |
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LoopCopyDataInit: |
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ldr r0, =__data_start__ |
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ldr r3, =__data_end__ |
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adds r2, r0, r1 |
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cmp r2, r3 |
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bcc CopyDataInit |
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ldr r2, =__bss_start__ |
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b LoopFillZerobss |
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/* Zero fill the bss segment. */ |
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FillZerobss: |
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movs r3, #0 |
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str r3, [r2], #4 |
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LoopFillZerobss: |
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ldr r3, = __bss_end__ |
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cmp r2, r3 |
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bcc FillZerobss |
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/* Call the clock system intitialization function.*/ |
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bl SystemInit |
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/* Call static constructors */ |
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//bl __libc_init_array |
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/* Call the application's entry point.*/ |
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bl main |
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bx lr |
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.size Reset_Handler, .-Reset_Handler |
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/** |
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* @brief This is the code that gets called when the processor receives an |
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* unexpected interrupt. This simply enters an infinite loop, preserving |
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* the system state for examination by a debugger. |
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* @param None |
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* @retval None |
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*/ |
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.section .text.Default_Handler,"ax",%progbits |
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Default_Handler: |
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Infinite_Loop: |
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b Infinite_Loop |
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.size Default_Handler, .-Default_Handler |
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/****************************************************************************** |
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* |
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* The minimal vector table for a Cortex M3. Note that the proper constructs |
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* must be placed on this to ensure that it ends up at physical address |
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* 0x0000.0000. |
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* |
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*******************************************************************************/ |
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.section .vectors,"a",%progbits |
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.type __Vectors, %object |
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.size __Vectors, .-__Vectors |
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__Vectors: |
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.word __StackTop |
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.word Reset_Handler |
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.word NMI_Handler |
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.word HardFault_Handler |
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.word MemManage_Handler |
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.word BusFault_Handler |
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.word UsageFault_Handler |
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.word 0 |
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.word 0 |
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.word 0 |
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.word 0 |
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.word SVC_Handler |
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.word DebugMon_Handler |
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.word 0 |
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.word PendSV_Handler |
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.word SysTick_Handler |
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/* External Interrupts */ |
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.word WWDG_IRQHandler /* Window WatchDog */ |
|||
.word PVD_IRQHandler /* PVD through EXTI Line detection */ |
|||
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ |
|||
.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ |
|||
.word FLASH_IRQHandler /* FLASH */ |
|||
.word RCC_IRQHandler /* RCC */ |
|||
.word EXTI0_IRQHandler /* EXTI Line0 */ |
|||
.word EXTI1_IRQHandler /* EXTI Line1 */ |
|||
.word EXTI2_IRQHandler /* EXTI Line2 */ |
|||
.word EXTI3_IRQHandler /* EXTI Line3 */ |
|||
.word EXTI4_IRQHandler /* EXTI Line4 */ |
|||
.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ |
|||
.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ |
|||
.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ |
|||
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ |
|||
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ |
|||
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ |
|||
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ |
|||
.word ADC_IRQHandler /* ADC1 */ |
|||
.word 0 /* Reserved */ |
|||
.word 0 /* Reserved */ |
|||
.word 0 /* Reserved */ |
|||
.word 0 /* Reserved */ |
|||
.word EXTI9_5_IRQHandler /* External Line[9:5]s */ |
|||
.word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ |
|||
.word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ |
|||
.word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ |
|||
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ |
|||
.word TIM2_IRQHandler /* TIM2 */ |
|||
.word TIM3_IRQHandler /* TIM3 */ |
|||
.word TIM4_IRQHandler /* TIM4 */ |
|||
.word I2C1_EV_IRQHandler /* I2C1 Event */ |
|||
.word I2C1_ER_IRQHandler /* I2C1 Error */ |
|||
.word I2C2_EV_IRQHandler /* I2C2 Event */ |
|||
.word I2C2_ER_IRQHandler /* I2C2 Error */ |
|||
.word SPI1_IRQHandler /* SPI1 */ |
|||
.word SPI2_IRQHandler /* SPI2 */ |
|||
.word USART1_IRQHandler /* USART1 */ |
|||
.word USART2_IRQHandler /* USART2 */ |
|||
.word 0 /* Reserved */ |
|||
.word EXTI15_10_IRQHandler /* External Line[15:10]s */ |
|||
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ |
|||
.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ |
|||
.word 0 /* Reserved */ |
|||
.word 0 /* Reserved */ |
|||
.word 0 /* Reserved */ |
|||
.word 0 /* Reserved */ |
|||
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ |
|||
.word 0 /* Reserved */ |
|||
.word SDIO_IRQHandler /* SDIO */ |
|||
.word TIM5_IRQHandler /* TIM5 */ |
|||
.word SPI3_IRQHandler /* SPI3 */ |
|||
.word 0 /* Reserved */ |
|||
.word 0 /* Reserved */ |
|||
.word 0 /* Reserved */ |
|||
.word 0 /* Reserved */ |
|||
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ |
|||
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ |
|||
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ |
|||
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ |
|||
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ |
|||
.word 0 /* Reserved */ |
|||
.word 0 /* Reserved */ |
|||
.word 0 /* Reserved */ |
|||
.word 0 /* Reserved */ |
|||
.word 0 /* Reserved */ |
|||
.word 0 /* Reserved */ |
|||
.word OTG_FS_IRQHandler /* USB OTG FS */ |
|||
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ |
|||
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ |
|||
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ |
|||
.word USART6_IRQHandler /* USART6 */ |
|||
.word I2C3_EV_IRQHandler /* I2C3 event */ |
|||
.word I2C3_ER_IRQHandler /* I2C3 error */ |
|||
.word 0 /* Reserved */ |
|||
.word 0 /* Reserved */ |
|||
.word 0 /* Reserved */ |
|||
.word 0 /* Reserved */ |
|||
.word 0 /* Reserved */ |
|||
.word 0 /* Reserved */ |
|||
.word 0 /* Reserved */ |
|||
.word FPU_IRQHandler /* FPU */ |
|||
.word 0 /* Reserved */ |
|||
.word 0 /* Reserved */ |
|||
.word SPI4_IRQHandler /* SPI4 */ |
|||
|
|||
/******************************************************************************* |
|||
* |
|||
* Provide weak aliases for each Exception handler to the Default_Handler. |
|||
* As they are weak aliases, any function with the same name will override |
|||
* this definition. |
|||
* |
|||
*******************************************************************************/ |
|||
.weak NMI_Handler |
|||
.thumb_set NMI_Handler,Default_Handler |
|||
|
|||
.weak HardFault_Handler |
|||
.thumb_set HardFault_Handler,Default_Handler |
|||
|
|||
.weak MemManage_Handler |
|||
.thumb_set MemManage_Handler,Default_Handler |
|||
|
|||
.weak BusFault_Handler |
|||
.thumb_set BusFault_Handler,Default_Handler |
|||
|
|||
.weak UsageFault_Handler |
|||
.thumb_set UsageFault_Handler,Default_Handler |
|||
|
|||
.weak SVC_Handler |
|||
.thumb_set SVC_Handler,Default_Handler |
|||
|
|||
.weak DebugMon_Handler |
|||
.thumb_set DebugMon_Handler,Default_Handler |
|||
|
|||
.weak PendSV_Handler |
|||
.thumb_set PendSV_Handler,Default_Handler |
|||
|
|||
.weak SysTick_Handler |
|||
.thumb_set SysTick_Handler,Default_Handler |
|||
|
|||
.weak WWDG_IRQHandler |
|||
.thumb_set WWDG_IRQHandler,Default_Handler |
|||
|
|||
.weak PVD_IRQHandler |
|||
.thumb_set PVD_IRQHandler,Default_Handler |
|||
|
|||
.weak TAMP_STAMP_IRQHandler |
|||
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler |
|||
|
|||
.weak RTC_WKUP_IRQHandler |
|||
.thumb_set RTC_WKUP_IRQHandler,Default_Handler |
|||
|
|||
.weak FLASH_IRQHandler |
|||
.thumb_set FLASH_IRQHandler,Default_Handler |
|||
|
|||
.weak RCC_IRQHandler |
|||
.thumb_set RCC_IRQHandler,Default_Handler |
|||
|
|||
.weak EXTI0_IRQHandler |
|||
.thumb_set EXTI0_IRQHandler,Default_Handler |
|||
|
|||
.weak EXTI1_IRQHandler |
|||
.thumb_set EXTI1_IRQHandler,Default_Handler |
|||
|
|||
.weak EXTI2_IRQHandler |
|||
.thumb_set EXTI2_IRQHandler,Default_Handler |
|||
|
|||
.weak EXTI3_IRQHandler |
|||
.thumb_set EXTI3_IRQHandler,Default_Handler |
|||
|
|||
.weak EXTI4_IRQHandler |
|||
.thumb_set EXTI4_IRQHandler,Default_Handler |
|||
|
|||
.weak DMA1_Stream0_IRQHandler |
|||
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler |
|||
|
|||
.weak DMA1_Stream1_IRQHandler |
|||
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler |
|||
|
|||
.weak DMA1_Stream2_IRQHandler |
|||
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler |
|||
|
|||
.weak DMA1_Stream3_IRQHandler |
|||
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler |
|||
|
|||
.weak DMA1_Stream4_IRQHandler |
|||
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler |
|||
|
|||
.weak DMA1_Stream5_IRQHandler |
|||
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler |
|||
|
|||
.weak DMA1_Stream6_IRQHandler |
|||
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler |
|||
|
|||
.weak ADC_IRQHandler |
|||
.thumb_set ADC_IRQHandler,Default_Handler |
|||
|
|||
.weak EXTI9_5_IRQHandler |
|||
.thumb_set EXTI9_5_IRQHandler,Default_Handler |
|||
|
|||
.weak TIM1_BRK_TIM9_IRQHandler |
|||
.thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler |
|||
|
|||
.weak TIM1_UP_TIM10_IRQHandler |
|||
.thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler |
|||
|
|||
.weak TIM1_TRG_COM_TIM11_IRQHandler |
|||
.thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler |
|||
|
|||
.weak TIM1_CC_IRQHandler |
|||
.thumb_set TIM1_CC_IRQHandler,Default_Handler |
|||
|
|||
.weak TIM2_IRQHandler |
|||
.thumb_set TIM2_IRQHandler,Default_Handler |
|||
|
|||
.weak TIM3_IRQHandler |
|||
.thumb_set TIM3_IRQHandler,Default_Handler |
|||
|
|||
.weak TIM4_IRQHandler |
|||
.thumb_set TIM4_IRQHandler,Default_Handler |
|||
|
|||
.weak I2C1_EV_IRQHandler |
|||
.thumb_set I2C1_EV_IRQHandler,Default_Handler |
|||
|
|||
.weak I2C1_ER_IRQHandler |
|||
.thumb_set I2C1_ER_IRQHandler,Default_Handler |
|||
|
|||
.weak I2C2_EV_IRQHandler |
|||
.thumb_set I2C2_EV_IRQHandler,Default_Handler |
|||
|
|||
.weak I2C2_ER_IRQHandler |
|||
.thumb_set I2C2_ER_IRQHandler,Default_Handler |
|||
|
|||
.weak SPI1_IRQHandler |
|||
.thumb_set SPI1_IRQHandler,Default_Handler |
|||
|
|||
.weak SPI2_IRQHandler |
|||
.thumb_set SPI2_IRQHandler,Default_Handler |
|||
|
|||
.weak USART1_IRQHandler |
|||
.thumb_set USART1_IRQHandler,Default_Handler |
|||
|
|||
.weak USART2_IRQHandler |
|||
.thumb_set USART2_IRQHandler,Default_Handler |
|||
|
|||
.weak EXTI15_10_IRQHandler |
|||
.thumb_set EXTI15_10_IRQHandler,Default_Handler |
|||
|
|||
.weak RTC_Alarm_IRQHandler |
|||
.thumb_set RTC_Alarm_IRQHandler,Default_Handler |
|||
|
|||
.weak OTG_FS_WKUP_IRQHandler |
|||
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler |
|||
|
|||
.weak DMA1_Stream7_IRQHandler |
|||
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler |
|||
|
|||
.weak SDIO_IRQHandler |
|||
.thumb_set SDIO_IRQHandler,Default_Handler |
|||
|
|||
.weak TIM5_IRQHandler |
|||
.thumb_set TIM5_IRQHandler,Default_Handler |
|||
|
|||
.weak SPI3_IRQHandler |
|||
.thumb_set SPI3_IRQHandler,Default_Handler |
|||
|
|||
.weak DMA2_Stream0_IRQHandler |
|||
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler |
|||
|
|||
.weak DMA2_Stream1_IRQHandler |
|||
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler |
|||
|
|||
.weak DMA2_Stream2_IRQHandler |
|||
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler |
|||
|
|||
.weak DMA2_Stream3_IRQHandler |
|||
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler |
|||
|
|||
.weak DMA2_Stream4_IRQHandler |
|||
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler |
|||
|
|||
.weak OTG_FS_IRQHandler |
|||
.thumb_set OTG_FS_IRQHandler,Default_Handler |
|||
|
|||
.weak DMA2_Stream5_IRQHandler |
|||
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler |
|||
|
|||
.weak DMA2_Stream6_IRQHandler |
|||
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler |
|||
|
|||
.weak DMA2_Stream7_IRQHandler |
|||
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler |
|||
|
|||
.weak USART6_IRQHandler |
|||
.thumb_set USART6_IRQHandler,Default_Handler |
|||
|
|||
.weak I2C3_EV_IRQHandler |
|||
.thumb_set I2C3_EV_IRQHandler,Default_Handler |
|||
|
|||
.weak I2C3_ER_IRQHandler |
|||
.thumb_set I2C3_ER_IRQHandler,Default_Handler |
|||
|
|||
.weak FPU_IRQHandler |
|||
.thumb_set FPU_IRQHandler,Default_Handler |
|||
|
|||
.weak SPI4_IRQHandler |
|||
.thumb_set SPI4_IRQHandler,Default_Handler |
|||
|
|||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
|||
|
|||
|
|||
@ -0,0 +1,587 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file system_stm32f4xx.c |
|||
* @author MCD Application Team |
|||
* @version V2.3.2 |
|||
* @date 26-June-2015 |
|||
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. |
|||
* |
|||
* This file provides two functions and one global variable to be called from |
|||
* user application: |
|||
* - SystemInit(): This function is called at startup just after reset and |
|||
* before branch to main program. This call is made inside |
|||
* the "startup_stm32f4xx.s" file. |
|||
* |
|||
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used |
|||
* by the user application to setup the SysTick |
|||
* timer or configure other parameters. |
|||
* |
|||
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must |
|||
* be called whenever the core clock is changed |
|||
* during program execution. |
|||
* |
|||
* |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> |
|||
* |
|||
* Redistribution and use in source and binary forms, with or without modification, |
|||
* are permitted provided that the following conditions are met: |
|||
* 1. Redistributions of source code must retain the above copyright notice, |
|||
* this list of conditions and the following disclaimer. |
|||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
|||
* this list of conditions and the following disclaimer in the documentation |
|||
* and/or other materials provided with the distribution. |
|||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
|||
* may be used to endorse or promote products derived from this software |
|||
* without specific prior written permission. |
|||
* |
|||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
|||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
|||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
|||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
|||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
|||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
|||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
|||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
|||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
|||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/** @addtogroup CMSIS
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup stm32f4xx_system
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup STM32F4xx_System_Private_Includes
|
|||
* @{ |
|||
*/ |
|||
|
|||
|
|||
#include "stm32f4xx.h" |
|||
|
|||
#if !defined (HSE_VALUE) |
|||
#define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ |
|||
#endif /* HSE_VALUE */ |
|||
|
|||
#if !defined (HSI_VALUE) |
|||
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ |
|||
#endif /* HSI_VALUE */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup STM32F4xx_System_Private_Defines
|
|||
* @{ |
|||
*/ |
|||
|
|||
/************************* Miscellaneous Configuration ************************/ |
|||
/*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */ |
|||
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ |
|||
defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) |
|||
/* #define DATA_IN_ExtSRAM */ |
|||
#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx */ |
|||
|
|||
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ |
|||
defined(STM32F446xx) |
|||
/* #define DATA_IN_ExtSDRAM */ |
|||
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */ |
|||
|
|||
#if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM) |
|||
#error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM " |
|||
#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */ |
|||
|
|||
/*!< Uncomment the following line if you need to relocate your vector Table in
|
|||
Internal SRAM. */ |
|||
/* #define VECT_TAB_SRAM */ |
|||
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. |
|||
This value must be a multiple of 0x200. */ |
|||
/******************************************************************************/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup STM32F4xx_System_Private_Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup STM32F4xx_System_Private_Variables
|
|||
* @{ |
|||
*/ |
|||
/* This variable is updated in three ways:
|
|||
1) by calling CMSIS function SystemCoreClockUpdate() |
|||
2) by calling HAL API function HAL_RCC_GetHCLKFreq() |
|||
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency |
|||
Note: If you use this function to configure the system clock; then there |
|||
is no need to call the 2 first functions listed above, since SystemCoreClock |
|||
variable is updated automatically. |
|||
*/ |
|||
uint32_t SystemCoreClock = 16000000; |
|||
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
|
|||
* @{ |
|||
*/ |
|||
|
|||
#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) |
|||
static void SystemInit_ExtMemCtl(void); |
|||
#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup STM32F4xx_System_Private_Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @brief Setup the microcontroller system |
|||
* Initialize the FPU setting, vector table location and External memory |
|||
* configuration. |
|||
* @param None |
|||
* @retval None |
|||
*/ |
|||
void SystemInit(void) |
|||
{ |
|||
/* FPU settings ------------------------------------------------------------*/ |
|||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) |
|||
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ |
|||
#endif |
|||
/* Reset the RCC clock configuration to the default reset state ------------*/ |
|||
/* Set HSION bit */ |
|||
RCC->CR |= (uint32_t)0x00000001; |
|||
|
|||
/* Reset CFGR register */ |
|||
RCC->CFGR = 0x00000000; |
|||
|
|||
/* Reset HSEON, CSSON and PLLON bits */ |
|||
RCC->CR &= (uint32_t)0xFEF6FFFF; |
|||
|
|||
/* Reset PLLCFGR register */ |
|||
RCC->PLLCFGR = 0x24003010; |
|||
|
|||
/* Reset HSEBYP bit */ |
|||
RCC->CR &= (uint32_t)0xFFFBFFFF; |
|||
|
|||
/* Disable all interrupts */ |
|||
RCC->CIR = 0x00000000; |
|||
|
|||
#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) |
|||
SystemInit_ExtMemCtl(); |
|||
#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ |
|||
|
|||
/* Configure the Vector Table location add offset address ------------------*/ |
|||
#ifdef VECT_TAB_SRAM |
|||
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ |
|||
#else |
|||
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ |
|||
#endif |
|||
} |
|||
|
|||
/**
|
|||
* @brief Update SystemCoreClock variable according to Clock Register Values. |
|||
* The SystemCoreClock variable contains the core clock (HCLK), it can |
|||
* be used by the user application to setup the SysTick timer or configure |
|||
* other parameters. |
|||
* |
|||
* @note Each time the core clock (HCLK) changes, this function must be called |
|||
* to update SystemCoreClock variable value. Otherwise, any configuration |
|||
* based on this variable will be incorrect. |
|||
* |
|||
* @note - The system frequency computed by this function is not the real |
|||
* frequency in the chip. It is calculated based on the predefined |
|||
* constant and the selected clock source: |
|||
* |
|||
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) |
|||
* |
|||
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) |
|||
* |
|||
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) |
|||
* or HSI_VALUE(*) multiplied/divided by the PLL factors. |
|||
* |
|||
* (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value |
|||
* 16 MHz) but the real value may vary depending on the variations |
|||
* in voltage and temperature. |
|||
* |
|||
* (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value |
|||
* depends on the application requirements), user has to ensure that HSE_VALUE |
|||
* is same as the real frequency of the crystal used. Otherwise, this function |
|||
* may have wrong result. |
|||
* |
|||
* - The result of this function could be not correct when using fractional |
|||
* value for HSE crystal. |
|||
* |
|||
* @param None |
|||
* @retval None |
|||
*/ |
|||
void SystemCoreClockUpdate(void) |
|||
{ |
|||
uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; |
|||
|
|||
/* Get SYSCLK source -------------------------------------------------------*/ |
|||
tmp = RCC->CFGR & RCC_CFGR_SWS; |
|||
|
|||
switch (tmp) |
|||
{ |
|||
case 0x00: /* HSI used as system clock source */ |
|||
SystemCoreClock = HSI_VALUE; |
|||
break; |
|||
case 0x04: /* HSE used as system clock source */ |
|||
SystemCoreClock = HSE_VALUE; |
|||
break; |
|||
case 0x08: /* PLL used as system clock source */ |
|||
|
|||
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
|
|||
SYSCLK = PLL_VCO / PLL_P |
|||
*/ |
|||
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; |
|||
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; |
|||
|
|||
if (pllsource != 0) |
|||
{ |
|||
/* HSE used as PLL clock source */ |
|||
pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); |
|||
} |
|||
else |
|||
{ |
|||
/* HSI used as PLL clock source */ |
|||
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); |
|||
} |
|||
|
|||
pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; |
|||
SystemCoreClock = pllvco/pllp; |
|||
break; |
|||
default: |
|||
SystemCoreClock = HSI_VALUE; |
|||
break; |
|||
} |
|||
/* Compute HCLK frequency --------------------------------------------------*/ |
|||
/* Get HCLK prescaler */ |
|||
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; |
|||
/* HCLK frequency */ |
|||
SystemCoreClock >>= tmp; |
|||
} |
|||
|
|||
#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) |
|||
/**
|
|||
* @brief Setup the external memory controller. |
|||
* Called in startup_stm32f4xx.s before jump to main. |
|||
* This function configures the external memories (SRAM/SDRAM) |
|||
* This SRAM/SDRAM will be used as program data memory (including heap and stack). |
|||
* @param None |
|||
* @retval None |
|||
*/ |
|||
void SystemInit_ExtMemCtl(void) |
|||
{ |
|||
__IO uint32_t tmp = 0x00; |
|||
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) |
|||
#if defined (DATA_IN_ExtSDRAM) |
|||
register uint32_t tmpreg = 0, timeout = 0xFFFF; |
|||
register uint32_t index; |
|||
|
|||
#if defined(STM32F446xx) |
|||
/* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface
|
|||
clock */ |
|||
RCC->AHB1ENR |= 0x0000007D; |
|||
#else |
|||
/* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
|
|||
clock */ |
|||
RCC->AHB1ENR |= 0x000001F8; |
|||
#endif /* STM32F446xx */ |
|||
/* Delay after an RCC peripheral clock enabling */ |
|||
tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); |
|||
|
|||
#if defined(STM32F446xx) |
|||
/* Connect PAx pins to FMC Alternate function */ |
|||
GPIOA->AFR[0] |= 0xC0000000; |
|||
GPIOA->AFR[1] |= 0x00000000; |
|||
/* Configure PDx pins in Alternate function mode */ |
|||
GPIOA->MODER |= 0x00008000; |
|||
/* Configure PDx pins speed to 50 MHz */ |
|||
GPIOA->OSPEEDR |= 0x00008000; |
|||
/* Configure PDx pins Output type to push-pull */ |
|||
GPIOA->OTYPER |= 0x00000000; |
|||
/* No pull-up, pull-down for PDx pins */ |
|||
GPIOA->PUPDR |= 0x00000000; |
|||
|
|||
/* Connect PCx pins to FMC Alternate function */ |
|||
GPIOC->AFR[0] |= 0x00CC0000; |
|||
GPIOC->AFR[1] |= 0x00000000; |
|||
/* Configure PDx pins in Alternate function mode */ |
|||
GPIOC->MODER |= 0x00000A00; |
|||
/* Configure PDx pins speed to 50 MHz */ |
|||
GPIOC->OSPEEDR |= 0x00000A00; |
|||
/* Configure PDx pins Output type to push-pull */ |
|||
GPIOC->OTYPER |= 0x00000000; |
|||
/* No pull-up, pull-down for PDx pins */ |
|||
GPIOC->PUPDR |= 0x00000000; |
|||
#endif /* STM32F446xx */ |
|||
|
|||
/* Connect PDx pins to FMC Alternate function */ |
|||
GPIOD->AFR[0] = 0x000000CC; |
|||
GPIOD->AFR[1] = 0xCC000CCC; |
|||
/* Configure PDx pins in Alternate function mode */ |
|||
GPIOD->MODER = 0xA02A000A; |
|||
/* Configure PDx pins speed to 50 MHz */ |
|||
GPIOD->OSPEEDR = 0xA02A000A; |
|||
/* Configure PDx pins Output type to push-pull */ |
|||
GPIOD->OTYPER = 0x00000000; |
|||
/* No pull-up, pull-down for PDx pins */ |
|||
GPIOD->PUPDR = 0x00000000; |
|||
|
|||
/* Connect PEx pins to FMC Alternate function */ |
|||
GPIOE->AFR[0] = 0xC00000CC; |
|||
GPIOE->AFR[1] = 0xCCCCCCCC; |
|||
/* Configure PEx pins in Alternate function mode */ |
|||
GPIOE->MODER = 0xAAAA800A; |
|||
/* Configure PEx pins speed to 50 MHz */ |
|||
GPIOE->OSPEEDR = 0xAAAA800A; |
|||
/* Configure PEx pins Output type to push-pull */ |
|||
GPIOE->OTYPER = 0x00000000; |
|||
/* No pull-up, pull-down for PEx pins */ |
|||
GPIOE->PUPDR = 0x00000000; |
|||
|
|||
/* Connect PFx pins to FMC Alternate function */ |
|||
GPIOF->AFR[0] = 0xCCCCCCCC; |
|||
GPIOF->AFR[1] = 0xCCCCCCCC; |
|||
/* Configure PFx pins in Alternate function mode */ |
|||
GPIOF->MODER = 0xAA800AAA; |
|||
/* Configure PFx pins speed to 50 MHz */ |
|||
GPIOF->OSPEEDR = 0xAA800AAA; |
|||
/* Configure PFx pins Output type to push-pull */ |
|||
GPIOF->OTYPER = 0x00000000; |
|||
/* No pull-up, pull-down for PFx pins */ |
|||
GPIOF->PUPDR = 0x00000000; |
|||
|
|||
/* Connect PGx pins to FMC Alternate function */ |
|||
GPIOG->AFR[0] = 0xCCCCCCCC; |
|||
GPIOG->AFR[1] = 0xCCCCCCCC; |
|||
/* Configure PGx pins in Alternate function mode */ |
|||
GPIOG->MODER = 0xAAAAAAAA; |
|||
/* Configure PGx pins speed to 50 MHz */ |
|||
GPIOG->OSPEEDR = 0xAAAAAAAA; |
|||
/* Configure PGx pins Output type to push-pull */ |
|||
GPIOG->OTYPER = 0x00000000; |
|||
/* No pull-up, pull-down for PGx pins */ |
|||
GPIOG->PUPDR = 0x00000000; |
|||
|
|||
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) |
|||
/* Connect PHx pins to FMC Alternate function */ |
|||
GPIOH->AFR[0] = 0x00C0CC00; |
|||
GPIOH->AFR[1] = 0xCCCCCCCC; |
|||
/* Configure PHx pins in Alternate function mode */ |
|||
GPIOH->MODER = 0xAAAA08A0; |
|||
/* Configure PHx pins speed to 50 MHz */ |
|||
GPIOH->OSPEEDR = 0xAAAA08A0; |
|||
/* Configure PHx pins Output type to push-pull */ |
|||
GPIOH->OTYPER = 0x00000000; |
|||
/* No pull-up, pull-down for PHx pins */ |
|||
GPIOH->PUPDR = 0x00000000; |
|||
|
|||
/* Connect PIx pins to FMC Alternate function */ |
|||
GPIOI->AFR[0] = 0xCCCCCCCC; |
|||
GPIOI->AFR[1] = 0x00000CC0; |
|||
/* Configure PIx pins in Alternate function mode */ |
|||
GPIOI->MODER = 0x0028AAAA; |
|||
/* Configure PIx pins speed to 50 MHz */ |
|||
GPIOI->OSPEEDR = 0x0028AAAA; |
|||
/* Configure PIx pins Output type to push-pull */ |
|||
GPIOI->OTYPER = 0x00000000; |
|||
/* No pull-up, pull-down for PIx pins */ |
|||
GPIOI->PUPDR = 0x00000000; |
|||
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ |
|||
|
|||
/*-- FMC Configuration -------------------------------------------------------*/ |
|||
/* Enable the FMC interface clock */ |
|||
RCC->AHB3ENR |= 0x00000001; |
|||
/* Delay after an RCC peripheral clock enabling */ |
|||
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); |
|||
|
|||
/* Configure and enable SDRAM bank1 */ |
|||
#if defined(STM32F446xx) |
|||
FMC_Bank5_6->SDCR[0] = 0x00001954; |
|||
#else |
|||
FMC_Bank5_6->SDCR[0] = 0x000019E4; |
|||
#endif /* STM32F446xx */ |
|||
FMC_Bank5_6->SDTR[0] = 0x01115351; |
|||
|
|||
/* SDRAM initialization sequence */ |
|||
/* Clock enable command */ |
|||
FMC_Bank5_6->SDCMR = 0x00000011; |
|||
tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
|||
while((tmpreg != 0) && (timeout-- > 0)) |
|||
{ |
|||
tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
|||
} |
|||
|
|||
/* Delay */ |
|||
for (index = 0; index<1000; index++); |
|||
|
|||
/* PALL command */ |
|||
FMC_Bank5_6->SDCMR = 0x00000012; |
|||
timeout = 0xFFFF; |
|||
while((tmpreg != 0) && (timeout-- > 0)) |
|||
{ |
|||
tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
|||
} |
|||
|
|||
/* Auto refresh command */ |
|||
#if defined(STM32F446xx) |
|||
FMC_Bank5_6->SDCMR = 0x000000F3; |
|||
#else |
|||
FMC_Bank5_6->SDCMR = 0x00000073; |
|||
#endif /* STM32F446xx */ |
|||
timeout = 0xFFFF; |
|||
while((tmpreg != 0) && (timeout-- > 0)) |
|||
{ |
|||
tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
|||
} |
|||
|
|||
/* MRD register program */ |
|||
#if defined(STM32F446xx) |
|||
FMC_Bank5_6->SDCMR = 0x00044014; |
|||
#else |
|||
FMC_Bank5_6->SDCMR = 0x00046014; |
|||
#endif /* STM32F446xx */ |
|||
timeout = 0xFFFF; |
|||
while((tmpreg != 0) && (timeout-- > 0)) |
|||
{ |
|||
tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
|||
} |
|||
|
|||
/* Set refresh count */ |
|||
tmpreg = FMC_Bank5_6->SDRTR; |
|||
#if defined(STM32F446xx) |
|||
FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1)); |
|||
#else |
|||
FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); |
|||
#endif /* STM32F446xx */ |
|||
|
|||
/* Disable write protection */ |
|||
tmpreg = FMC_Bank5_6->SDCR[0]; |
|||
FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); |
|||
#endif /* DATA_IN_ExtSDRAM */ |
|||
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */ |
|||
|
|||
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ |
|||
defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) |
|||
|
|||
#if defined(DATA_IN_ExtSRAM) |
|||
/*-- GPIOs Configuration -----------------------------------------------------*/ |
|||
/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ |
|||
RCC->AHB1ENR |= 0x00000078; |
|||
/* Delay after an RCC peripheral clock enabling */ |
|||
tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN); |
|||
|
|||
/* Connect PDx pins to FMC Alternate function */ |
|||
GPIOD->AFR[0] = 0x00CCC0CC; |
|||
GPIOD->AFR[1] = 0xCCCCCCCC; |
|||
/* Configure PDx pins in Alternate function mode */ |
|||
GPIOD->MODER = 0xAAAA0A8A; |
|||
/* Configure PDx pins speed to 100 MHz */ |
|||
GPIOD->OSPEEDR = 0xFFFF0FCF; |
|||
/* Configure PDx pins Output type to push-pull */ |
|||
GPIOD->OTYPER = 0x00000000; |
|||
/* No pull-up, pull-down for PDx pins */ |
|||
GPIOD->PUPDR = 0x00000000; |
|||
|
|||
/* Connect PEx pins to FMC Alternate function */ |
|||
GPIOE->AFR[0] = 0xC00CC0CC; |
|||
GPIOE->AFR[1] = 0xCCCCCCCC; |
|||
/* Configure PEx pins in Alternate function mode */ |
|||
GPIOE->MODER = 0xAAAA828A; |
|||
/* Configure PEx pins speed to 100 MHz */ |
|||
GPIOE->OSPEEDR = 0xFFFFC3CF; |
|||
/* Configure PEx pins Output type to push-pull */ |
|||
GPIOE->OTYPER = 0x00000000; |
|||
/* No pull-up, pull-down for PEx pins */ |
|||
GPIOE->PUPDR = 0x00000000; |
|||
|
|||
/* Connect PFx pins to FMC Alternate function */ |
|||
GPIOF->AFR[0] = 0x00CCCCCC; |
|||
GPIOF->AFR[1] = 0xCCCC0000; |
|||
/* Configure PFx pins in Alternate function mode */ |
|||
GPIOF->MODER = 0xAA000AAA; |
|||
/* Configure PFx pins speed to 100 MHz */ |
|||
GPIOF->OSPEEDR = 0xFF000FFF; |
|||
/* Configure PFx pins Output type to push-pull */ |
|||
GPIOF->OTYPER = 0x00000000; |
|||
/* No pull-up, pull-down for PFx pins */ |
|||
GPIOF->PUPDR = 0x00000000; |
|||
|
|||
/* Connect PGx pins to FMC Alternate function */ |
|||
GPIOG->AFR[0] = 0x00CCCCCC; |
|||
GPIOG->AFR[1] = 0x000000C0; |
|||
/* Configure PGx pins in Alternate function mode */ |
|||
GPIOG->MODER = 0x00085AAA; |
|||
/* Configure PGx pins speed to 100 MHz */ |
|||
GPIOG->OSPEEDR = 0x000CAFFF; |
|||
/* Configure PGx pins Output type to push-pull */ |
|||
GPIOG->OTYPER = 0x00000000; |
|||
/* No pull-up, pull-down for PGx pins */ |
|||
GPIOG->PUPDR = 0x00000000; |
|||
|
|||
/*-- FMC/FSMC Configuration --------------------------------------------------*/ |
|||
/* Enable the FMC/FSMC interface clock */ |
|||
RCC->AHB3ENR |= 0x00000001; |
|||
|
|||
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) |
|||
/* Delay after an RCC peripheral clock enabling */ |
|||
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); |
|||
/* Configure and enable Bank1_SRAM2 */ |
|||
FMC_Bank1->BTCR[2] = 0x00001011; |
|||
FMC_Bank1->BTCR[3] = 0x00000201; |
|||
FMC_Bank1E->BWTR[2] = 0x0fffffff; |
|||
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ |
|||
|
|||
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) |
|||
/* Delay after an RCC peripheral clock enabling */ |
|||
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN); |
|||
/* Configure and enable Bank1_SRAM2 */ |
|||
FSMC_Bank1->BTCR[2] = 0x00001011; |
|||
FSMC_Bank1->BTCR[3] = 0x00000201; |
|||
FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF; |
|||
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ |
|||
|
|||
#endif /* DATA_IN_ExtSRAM */ |
|||
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ |
|||
(void)(tmp); |
|||
} |
|||
#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
|||
@ -0,0 +1,136 @@ |
|||
/* ----------------------------------------------------------------------
|
|||
* Copyright (C) 2010-2014 ARM Limited. All rights reserved. |
|||
* |
|||
* $Date: 31. July 2014 |
|||
* $Revision: V1.4.4 |
|||
* |
|||
* Project: CMSIS DSP Library |
|||
* Title: arm_common_tables.h |
|||
* |
|||
* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions |
|||
* |
|||
* Target Processor: Cortex-M4/Cortex-M3 |
|||
* |
|||
* Redistribution and use in source and binary forms, with or without |
|||
* modification, are permitted provided that the following conditions |
|||
* are met: |
|||
* - Redistributions of source code must retain the above copyright |
|||
* notice, this list of conditions and the following disclaimer. |
|||
* - Redistributions in binary form must reproduce the above copyright |
|||
* notice, this list of conditions and the following disclaimer in |
|||
* the documentation and/or other materials provided with the |
|||
* distribution. |
|||
* - Neither the name of ARM LIMITED nor the names of its contributors |
|||
* may be used to endorse or promote products derived from this |
|||
* software without specific prior written permission. |
|||
* |
|||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
|||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
|||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
|||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
|||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
|||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
|||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
|||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
|||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
|||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
|||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
|||
* POSSIBILITY OF SUCH DAMAGE. |
|||
* -------------------------------------------------------------------- */ |
|||
|
|||
#ifndef _ARM_COMMON_TABLES_H |
|||
#define _ARM_COMMON_TABLES_H |
|||
|
|||
#include "arm_math.h" |
|||
|
|||
extern const uint16_t armBitRevTable[1024]; |
|||
extern const q15_t armRecipTableQ15[64]; |
|||
extern const q31_t armRecipTableQ31[64]; |
|||