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/**
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****************************************************************************** |
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* @file stm32f4xx_hal.h |
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* @author MCD Application Team |
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* @version V1.2.0 |
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* @date 26-December-2014 |
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* @brief This file contains all the functions prototypes for the HAL |
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* module driver. |
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****************************************************************************** |
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* @attention |
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* |
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* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
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* |
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* Redistribution and use in source and binary forms, with or without modification, |
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* are permitted provided that the following conditions are met: |
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* 1. Redistributions of source code must retain the above copyright notice, |
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* this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright notice, |
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* this list of conditions and the following disclaimer in the documentation |
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* and/or other materials provided with the distribution. |
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* 3. Neither the name of STMicroelectronics nor the names of its contributors |
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* may be used to endorse or promote products derived from this software |
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* without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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* |
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****************************************************************************** |
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*/ |
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|
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/* Define to prevent recursive inclusion -------------------------------------*/ |
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#ifndef __STM32F4xx_HAL_H |
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#define __STM32F4xx_HAL_H |
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|
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#ifdef __cplusplus |
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extern "C" { |
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#endif |
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|
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/* Includes ------------------------------------------------------------------*/ |
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#include <hal_config.h> |
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|
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/** @addtogroup STM32F4xx_HAL_Driver
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* @{ |
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*/ |
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|
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/** @addtogroup HAL
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* @{ |
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*/ |
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|
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/* Exported types ------------------------------------------------------------*/ |
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/* Exported constants --------------------------------------------------------*/ |
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/* Exported macro ------------------------------------------------------------*/ |
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/** @defgroup HAL_Exported_Macros HAL Exported Macros
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* @{ |
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*/ |
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|
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/** @brief Freeze/Unfreeze Peripherals in Debug mode
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*/ |
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#define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP)) |
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#define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP)) |
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#define __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP)) |
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#define __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP)) |
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#define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP)) |
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#define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP)) |
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#define __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP)) |
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#define __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP)) |
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#define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP)) |
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#define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP)) |
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#define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP)) |
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#define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP)) |
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#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) |
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#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)) |
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#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)) |
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#define __HAL_DBGMCU_FREEZE_CAN1() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN1_STOP)) |
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#define __HAL_DBGMCU_FREEZE_CAN2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN2_STOP)) |
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#define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP)) |
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#define __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP)) |
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#define __HAL_DBGMCU_FREEZE_TIM9() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM9_STOP)) |
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#define __HAL_DBGMCU_FREEZE_TIM10() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM10_STOP)) |
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#define __HAL_DBGMCU_FREEZE_TIM11() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM11_STOP)) |
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#define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP)) |
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#define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP)) |
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#define __HAL_DBGMCU_UNFREEZE_TIM4() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP)) |
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#define __HAL_DBGMCU_UNFREEZE_TIM5() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP)) |
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#define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP)) |
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#define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP)) |
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#define __HAL_DBGMCU_UNFREEZE_TIM12() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP)) |
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#define __HAL_DBGMCU_UNFREEZE_TIM13() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP)) |
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#define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP)) |
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#define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP)) |
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#define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP)) |
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#define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP)) |
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#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) |
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#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)) |
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#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)) |
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#define __HAL_DBGMCU_UNFREEZE_CAN1() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN1_STOP)) |
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#define __HAL_DBGMCU_UNFREEZE_CAN2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN2_STOP)) |
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#define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP)) |
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#define __HAL_DBGMCU_UNFREEZE_TIM8() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP)) |
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#define __HAL_DBGMCU_UNFREEZE_TIM9() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM9_STOP)) |
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#define __HAL_DBGMCU_UNFREEZE_TIM10() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM10_STOP)) |
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#define __HAL_DBGMCU_UNFREEZE_TIM11() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM11_STOP)) |
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/** @brief Main Flash memory mapped at 0x00000000
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*/ |
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#define __HAL_SYSCFG_REMAPMEMORY_FLASH() (SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE)) |
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/** @brief System Flash memory mapped at 0x00000000
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*/ |
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#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\ |
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SYSCFG->MEMRMP |= SYSCFG_MEMRMP_MEM_MODE_0;\ |
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}while(0); |
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/** @brief Embedded SRAM mapped at 0x00000000
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*/ |
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#define __HAL_SYSCFG_REMAPMEMORY_SRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\ |
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SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_0 | SYSCFG_MEMRMP_MEM_MODE_1);\ |
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}while(0); |
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#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) |
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/** @brief FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
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*/ |
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#define __HAL_SYSCFG_REMAPMEMORY_FSMC() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\ |
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SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1);\ |
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}while(0); |
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#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ |
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#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) |
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/** @brief FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
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*/ |
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#define __HAL_SYSCFG_REMAPMEMORY_FMC() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\ |
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SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1);\ |
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}while(0); |
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/** @brief FMC/SDRAM Bank 1 and 2 mapped at 0x00000000
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*/ |
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#define __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\ |
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SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_2);\ |
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}while(0); |
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#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ |
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/**
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* @} |
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*/ |
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/* Exported functions --------------------------------------------------------*/ |
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/** @addtogroup HAL_Exported_Functions
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* @{ |
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*/ |
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/** @addtogroup HAL_Exported_Functions_Group1
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* @{ |
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*/ |
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/* Initialization and de-initialization functions ******************************/ |
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HAL_StatusTypeDef HAL_Init(void); |
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HAL_StatusTypeDef HAL_DeInit(void); |
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void HAL_MspInit(void); |
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void HAL_MspDeInit(void); |
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uint32_t HAL_GetHSECrystalFreqMHz(void); |
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HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); |
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/**
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* @} |
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*/ |
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/** @addtogroup HAL_Exported_Functions_Group2
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* @{ |
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*/ |
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/* Peripheral Control functions ************************************************/ |
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void HAL_IncTick(void); |
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void HAL_Delay(__IO uint32_t Delay); |
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uint32_t HAL_GetTick(void); |
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void HAL_SuspendTick(void); |
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void HAL_ResumeTick(void); |
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uint32_t HAL_GetHalVersion(void); |
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uint32_t HAL_GetREVID(void); |
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uint32_t HAL_GetDEVID(void); |
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void HAL_DBGMCU_EnableDBGSleepMode(void); |
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void HAL_DBGMCU_DisableDBGSleepMode(void); |
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void HAL_DBGMCU_EnableDBGStopMode(void); |
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void HAL_DBGMCU_DisableDBGStopMode(void); |
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void HAL_DBGMCU_EnableDBGStandbyMode(void); |
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void HAL_DBGMCU_DisableDBGStandbyMode(void); |
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void HAL_EnableCompensationCell(void); |
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void HAL_DisableCompensationCell(void); |
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#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) |
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void HAL_EnableMemorySwappingBank(void); |
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void HAL_DisableMemorySwappingBank(void); |
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#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ |
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/**
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* @} |
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*/ |
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/**
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* @} |
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*/ |
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/* Private types -------------------------------------------------------------*/ |
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/* Private variables ---------------------------------------------------------*/ |
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/** @defgroup HAL_Private_Variables HAL Private Variables
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* @{ |
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*/ |
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/**
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* @} |
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*/ |
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/* Private constants ---------------------------------------------------------*/ |
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/** @defgroup HAL_Private_Constants HAL Private Constants
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* @{ |
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*/ |
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/**
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* @} |
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*/ |
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/* Private macros ------------------------------------------------------------*/ |
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/* Private functions ---------------------------------------------------------*/ |
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/**
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* @} |
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*/ |
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/**
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* @} |
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*/ |
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#ifdef __cplusplus |
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} |
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#endif |
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#endif /* __STM32F4xx_HAL_H */ |
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
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/**
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****************************************************************************** |
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* @file stm32f4xx_hal_adc.h |
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* @author MCD Application Team |
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* @version V1.2.0 |
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* @date 26-December-2014 |
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* @brief Header file of ADC HAL extension module. |
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****************************************************************************** |
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* @attention |
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* |
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* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
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* |
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* Redistribution and use in source and binary forms, with or without modification, |
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* are permitted provided that the following conditions are met: |
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* 1. Redistributions of source code must retain the above copyright notice, |
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* this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright notice, |
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* this list of conditions and the following disclaimer in the documentation |
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* and/or other materials provided with the distribution. |
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* 3. Neither the name of STMicroelectronics nor the names of its contributors |
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* may be used to endorse or promote products derived from this software |
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* without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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* |
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****************************************************************************** |
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*/ |
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|
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/* Define to prevent recursive inclusion -------------------------------------*/ |
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#ifndef __STM32F4xx_ADC_H |
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#define __STM32F4xx_ADC_H |
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#ifdef __cplusplus |
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extern "C" { |
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#endif |
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/* Includes ------------------------------------------------------------------*/ |
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#include "stm32f4xx_hal_def.h" |
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/** @addtogroup STM32F4xx_HAL_Driver
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* @{ |
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*/ |
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/** @addtogroup ADC
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* @{ |
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*/ |
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/* Exported types ------------------------------------------------------------*/ |
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/** @defgroup ADC_Exported_Types ADC Exported Types
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* @{ |
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*/ |
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/**
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* @brief HAL State structures definition |
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*/ |
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typedef enum |
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{ |
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HAL_ADC_STATE_RESET = 0x00, /*!< ADC not yet initialized or disabled */ |
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HAL_ADC_STATE_READY = 0x01, /*!< ADC peripheral ready for use */ |
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HAL_ADC_STATE_BUSY = 0x02, /*!< An internal process is ongoing */ |
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HAL_ADC_STATE_BUSY_REG = 0x12, /*!< Regular conversion is ongoing */ |
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HAL_ADC_STATE_BUSY_INJ = 0x22, /*!< Injected conversion is ongoing */ |
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HAL_ADC_STATE_BUSY_INJ_REG = 0x32, /*!< Injected and regular conversion are ongoing */ |
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HAL_ADC_STATE_TIMEOUT = 0x03, /*!< Timeout state */ |
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HAL_ADC_STATE_ERROR = 0x04, /*!< ADC state error */ |
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HAL_ADC_STATE_EOC = 0x05, /*!< Conversion is completed */ |
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HAL_ADC_STATE_EOC_REG = 0x15, /*!< Regular conversion is completed */ |
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HAL_ADC_STATE_EOC_INJ = 0x25, /*!< Injected conversion is completed */ |
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HAL_ADC_STATE_EOC_INJ_REG = 0x35, /*!< Injected and regular conversion are completed */ |
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HAL_ADC_STATE_AWD = 0x06 /*!< ADC state analog watchdog */ |
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}HAL_ADC_StateTypeDef; |
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/**
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* @brief ADC Init structure definition |
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*/ |
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typedef struct |
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{ |
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uint32_t ClockPrescaler; /*!< Select the frequency of the clock to the ADC. The clock is common for
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all the ADCs. |
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This parameter can be a value of @ref ADC_ClockPrescaler */ |
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uint32_t Resolution; /*!< Configures the ADC resolution dual mode.
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This parameter can be a value of @ref ADC_Resolution */ |
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uint32_t DataAlign; /*!< Specifies whether the ADC data alignment is left or right.
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This parameter can be a value of @ref ADC_data_align */ |
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uint32_t ScanConvMode; /*!< Specifies whether the conversion is performed in Scan (multi channels) or
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Single (one channel) mode. |
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This parameter can be set to ENABLE or DISABLE */ |
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uint32_t EOCSelection; /*!< Specifies whether the EOC flag is set
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at the end of single channel conversion or at the end of all conversions. |
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This parameter can be a value of @ref ADC_EOCSelection */ |
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uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in Continuous or Single mode.
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This parameter can be set to ENABLE or DISABLE. */ |
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uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests is performed in Continuous or in Single mode.
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This parameter can be set to ENABLE or DISABLE. */ |
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uint32_t NbrOfConversion; /*!< Specifies the number of ADC conversions that will be done using the sequencer for
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regular channel group. |
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This parameter must be a number between Min_Data = 1 and Max_Data = 16. */ |
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uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversion is performed in Discontinuous or not
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for regular channels. |
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This parameter can be set to ENABLE or DISABLE. */ |
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uint32_t NbrOfDiscConversion; /*!< Specifies the number of ADC discontinuous conversions that will be done
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using the sequencer for regular channel group. |
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This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ |
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uint32_t ExternalTrigConvEdge; /*!< Select the external trigger edge and enable the trigger of a regular group.
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This parameter can be a value of @ref ADC_External_trigger_edge_Regular */ |
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uint32_t ExternalTrigConv; /*!< Select the external event used to trigger the start of conversion of a regular group.
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This parameter can be a value of @ref ADC_External_trigger_Source_Regular */ |
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}ADC_InitTypeDef; |
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/**
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* @brief ADC handle Structure definition |
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*/ |
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typedef struct |
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{ |
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ADC_TypeDef *Instance; /*!< Register base address */ |
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ADC_InitTypeDef Init; /*!< ADC required parameters */ |
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__IO uint32_t NbrOfCurrentConversionRank; /*!< ADC number of current conversion rank */ |
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DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ |
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HAL_LockTypeDef Lock; /*!< ADC locking object */ |
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__IO HAL_ADC_StateTypeDef State; /*!< ADC communication state */ |
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__IO uint32_t ErrorCode; /*!< ADC Error code */ |
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}ADC_HandleTypeDef; |
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/**
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* @brief ADC Configuration regular Channel structure definition |
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*/ |
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typedef struct |
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{ |
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uint32_t Channel; /*!< The ADC channel to configure.
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This parameter can be a value of @ref ADC_channels */ |
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uint32_t Rank; /*!< The rank in the regular group sequencer.
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This parameter must be a number between Min_Data = 1 and Max_Data = 16 */ |
|||
uint32_t SamplingTime; /*!< The sample time value to be set for the selected channel.
|
|||
This parameter can be a value of @ref ADC_sampling_times */ |
|||
uint32_t Offset; /*!< Reserved for future use, can be set to 0 */ |
|||
}ADC_ChannelConfTypeDef; |
|||
|
|||
/**
|
|||
* @brief ADC Configuration multi-mode structure definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode.
|
|||
This parameter can be a value of @ref ADC_analog_watchdog_selection */ |
|||
uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
|
|||
This parameter must be a 12-bit value. */ |
|||
uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
|
|||
This parameter must be a 12-bit value. */ |
|||
uint32_t Channel; /*!< Configures ADC channel for the analog watchdog.
|
|||
This parameter has an effect only if watchdog mode is configured on single channel |
|||
This parameter can be a value of @ref ADC_channels */ |
|||
uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured
|
|||
is interrupt mode or in polling mode. |
|||
This parameter can be set to ENABLE or DISABLE */ |
|||
uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */ |
|||
}ADC_AnalogWDGConfTypeDef; |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported constants --------------------------------------------------------*/ |
|||
/** @defgroup ADC_Exported_Constants ADC Exported Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup ADC_Error_Code ADC Error Code
|
|||
* @{ |
|||
*/ |
|||
#define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */ |
|||
#define HAL_ADC_ERROR_OVR ((uint32_t)0x01) /*!< OVR error */ |
|||
#define HAL_ADC_ERROR_DMA ((uint32_t)0x02) /*!< DMA transfer error */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
|
|||
/** @defgroup ADC_ClockPrescaler ADC Clock Prescaler
|
|||
* @{ |
|||
*/ |
|||
#define ADC_CLOCKPRESCALER_PCLK_DIV2 ((uint32_t)0x00000000) |
|||
#define ADC_CLOCKPRESCALER_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0) |
|||
#define ADC_CLOCKPRESCALER_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1) |
|||
#define ADC_CLOCKPRESCALER_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup ADC_delay_between_2_sampling_phases ADC Delay Between 2 Sampling Phases
|
|||
* @{ |
|||
*/ |
|||
#define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)0x00000000) |
|||
#define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0) |
|||
#define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1) |
|||
#define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) |
|||
#define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)ADC_CCR_DELAY_2) |
|||
#define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0)) |
|||
#define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1)) |
|||
#define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) |
|||
#define ADC_TWOSAMPLINGDELAY_13CYCLES ((uint32_t)ADC_CCR_DELAY_3) |
|||
#define ADC_TWOSAMPLINGDELAY_14CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0)) |
|||
#define ADC_TWOSAMPLINGDELAY_15CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1)) |
|||
#define ADC_TWOSAMPLINGDELAY_16CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) |
|||
#define ADC_TWOSAMPLINGDELAY_17CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2)) |
|||
#define ADC_TWOSAMPLINGDELAY_18CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0)) |
|||
#define ADC_TWOSAMPLINGDELAY_19CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1)) |
|||
#define ADC_TWOSAMPLINGDELAY_20CYCLES ((uint32_t)ADC_CCR_DELAY) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup ADC_Resolution ADC Resolution
|
|||
* @{ |
|||
*/ |
|||
#define ADC_RESOLUTION_12B ((uint32_t)0x00000000) |
|||
#define ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0) |
|||
#define ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1) |
|||
#define ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup ADC_External_trigger_edge_Regular ADC External Trigger Edge Regular
|
|||
* @{ |
|||
*/ |
|||
#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000) |
|||
#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0) |
|||
#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1) |
|||
#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup ADC_External_trigger_Source_Regular ADC External Trigger Source Regular
|
|||
* @{ |
|||
*/ |
|||
#define ADC_EXTERNALTRIGCONV_T1_CC1 ((uint32_t)0x00000000) |
|||
#define ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0) |
|||
#define ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1) |
|||
#define ADC_EXTERNALTRIGCONV_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) |
|||
#define ADC_EXTERNALTRIGCONV_T2_CC3 ((uint32_t)ADC_CR2_EXTSEL_2) |
|||
#define ADC_EXTERNALTRIGCONV_T2_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)) |
|||
#define ADC_EXTERNALTRIGCONV_T2_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1)) |
|||
#define ADC_EXTERNALTRIGCONV_T3_CC1 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) |
|||
#define ADC_EXTERNALTRIGCONV_T3_TRGO ((uint32_t)ADC_CR2_EXTSEL_3) |
|||
#define ADC_EXTERNALTRIGCONV_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0)) |
|||
#define ADC_EXTERNALTRIGCONV_T5_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1)) |
|||
#define ADC_EXTERNALTRIGCONV_T5_CC2 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) |
|||
#define ADC_EXTERNALTRIGCONV_T5_CC3 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2)) |
|||
#define ADC_EXTERNALTRIGCONV_T8_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)) |
|||
#define ADC_EXTERNALTRIGCONV_T8_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1)) |
|||
#define ADC_EXTERNALTRIGCONV_Ext_IT11 ((uint32_t)ADC_CR2_EXTSEL) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup ADC_data_align ADC Data Align
|
|||
* @{ |
|||
*/ |
|||
#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000) |
|||
#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup ADC_channels ADC Common Channels
|
|||
* @{ |
|||
*/ |
|||
#define ADC_CHANNEL_0 ((uint32_t)0x00000000) |
|||
#define ADC_CHANNEL_1 ((uint32_t)ADC_CR1_AWDCH_0) |
|||
#define ADC_CHANNEL_2 ((uint32_t)ADC_CR1_AWDCH_1) |
|||
#define ADC_CHANNEL_3 ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) |
|||
#define ADC_CHANNEL_4 ((uint32_t)ADC_CR1_AWDCH_2) |
|||
#define ADC_CHANNEL_5 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)) |
|||
#define ADC_CHANNEL_6 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1)) |
|||
#define ADC_CHANNEL_7 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) |
|||
#define ADC_CHANNEL_8 ((uint32_t)ADC_CR1_AWDCH_3) |
|||
#define ADC_CHANNEL_9 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0)) |
|||
#define ADC_CHANNEL_10 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1)) |
|||
#define ADC_CHANNEL_11 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) |
|||
#define ADC_CHANNEL_12 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2)) |
|||
#define ADC_CHANNEL_13 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)) |
|||
#define ADC_CHANNEL_14 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1)) |
|||
#define ADC_CHANNEL_15 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) |
|||
#define ADC_CHANNEL_16 ((uint32_t)ADC_CR1_AWDCH_4) |
|||
#define ADC_CHANNEL_17 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0)) |
|||
#define ADC_CHANNEL_18 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1)) |
|||
|
|||
#define ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_17) |
|||
#define ADC_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup ADC_sampling_times ADC Sampling Times
|
|||
* @{ |
|||
*/ |
|||
#define ADC_SAMPLETIME_3CYCLES ((uint32_t)0x00000000) |
|||
#define ADC_SAMPLETIME_15CYCLES ((uint32_t)ADC_SMPR1_SMP10_0) |
|||
#define ADC_SAMPLETIME_28CYCLES ((uint32_t)ADC_SMPR1_SMP10_1) |
|||
#define ADC_SAMPLETIME_56CYCLES ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0)) |
|||
#define ADC_SAMPLETIME_84CYCLES ((uint32_t)ADC_SMPR1_SMP10_2) |
|||
#define ADC_SAMPLETIME_112CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0)) |
|||
#define ADC_SAMPLETIME_144CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1)) |
|||
#define ADC_SAMPLETIME_480CYCLES ((uint32_t)ADC_SMPR1_SMP10) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup ADC_EOCSelection ADC EOC Selection
|
|||
* @{ |
|||
*/ |
|||
#define ADC_EOC_SEQ_CONV ((uint32_t)0x00000000) |
|||
#define ADC_EOC_SINGLE_CONV ((uint32_t)0x00000001) |
|||
#define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)0x00000002) /*!< reserved for future use */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup ADC_Event_type ADC Event Type
|
|||
* @{ |
|||
*/ |
|||
#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) |
|||
#define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup ADC_analog_watchdog_selection ADC Analog Watchdog Selection
|
|||
* @{ |
|||
*/ |
|||
#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN)) |
|||
#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN)) |
|||
#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) |
|||
#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN) |
|||
#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN) |
|||
#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) |
|||
#define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup ADC_interrupts_definition ADC Interrupts Definition
|
|||
* @{ |
|||
*/ |
|||
#define ADC_IT_EOC ((uint32_t)ADC_CR1_EOCIE) |
|||
#define ADC_IT_AWD ((uint32_t)ADC_CR1_AWDIE) |
|||
#define ADC_IT_JEOC ((uint32_t)ADC_CR1_JEOCIE) |
|||
#define ADC_IT_OVR ((uint32_t)ADC_CR1_OVRIE) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup ADC_flags_definition ADC Flags Definition
|
|||
* @{ |
|||
*/ |
|||
#define ADC_FLAG_AWD ((uint32_t)ADC_SR_AWD) |
|||
#define ADC_FLAG_EOC ((uint32_t)ADC_SR_EOC) |
|||
#define ADC_FLAG_JEOC ((uint32_t)ADC_SR_JEOC) |
|||
#define ADC_FLAG_JSTRT ((uint32_t)ADC_SR_JSTRT) |
|||
#define ADC_FLAG_STRT ((uint32_t)ADC_SR_STRT) |
|||
#define ADC_FLAG_OVR ((uint32_t)ADC_SR_OVR) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup ADC_channels_type ADC Channels Type
|
|||
* @{ |
|||
*/ |
|||
#define ADC_ALL_CHANNELS ((uint32_t)0x00000001) |
|||
#define ADC_REGULAR_CHANNELS ((uint32_t)0x00000002) /*!< reserved for future use */ |
|||
#define ADC_INJECTED_CHANNELS ((uint32_t)0x00000003) /*!< reserved for future use */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported macro ------------------------------------------------------------*/ |
|||
/** @defgroup ADC_Exported_Macros ADC Exported Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @brief Reset ADC handle state
|
|||
* @param __HANDLE__: ADC handle |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET) |
|||
|
|||
/**
|
|||
* @brief Enable the ADC peripheral. |
|||
* @param __HANDLE__: ADC handle |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON) |
|||
|
|||
/**
|
|||
* @brief Disable the ADC peripheral. |
|||
* @param __HANDLE__: ADC handle |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON) |
|||
|
|||
/**
|
|||
* @brief Enable the ADC end of conversion interrupt. |
|||
* @param __HANDLE__: specifies the ADC Handle. |
|||
* @param __INTERRUPT__: ADC Interrupt. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__)) |
|||
|
|||
/**
|
|||
* @brief Disable the ADC end of conversion interrupt. |
|||
* @param __HANDLE__: specifies the ADC Handle. |
|||
* @param __INTERRUPT__: ADC interrupt. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__)) |
|||
|
|||
/** @brief Check if the specified ADC interrupt source is enabled or disabled.
|
|||
* @param __HANDLE__: specifies the ADC Handle. |
|||
* @param __INTERRUPT__: specifies the ADC interrupt source to check. |
|||
* @retval The new state of __IT__ (TRUE or FALSE). |
|||
*/ |
|||
#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
|||
|
|||
/**
|
|||
* @brief Clear the ADC's pending flags. |
|||
* @param __HANDLE__: specifies the ADC Handle. |
|||
* @param __FLAG__: ADC flag. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__)) |
|||
|
|||
/**
|
|||
* @brief Get the selected ADC's flag status. |
|||
* @param __HANDLE__: specifies the ADC Handle. |
|||
* @param __FLAG__: ADC flag. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Include ADC HAL Extension module */ |
|||
#include "stm32f4xx_hal_adc_ex.h" |
|||
|
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @addtogroup ADC_Exported_Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup ADC_Exported_Functions_Group1
|
|||
* @{ |
|||
*/ |
|||
/* Initialization/de-initialization functions ***********************************/ |
|||
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc); |
|||
HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); |
|||
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc); |
|||
void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup ADC_Exported_Functions_Group2
|
|||
* @{ |
|||
*/ |
|||
/* I/O operation functions ******************************************************/ |
|||
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc); |
|||
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc); |
|||
HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); |
|||
|
|||
HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout); |
|||
|
|||
HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc); |
|||
HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc); |
|||
|
|||
void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc); |
|||
|
|||
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); |
|||
HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc); |
|||
|
|||
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc); |
|||
|
|||
void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc); |
|||
void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc); |
|||
void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc); |
|||
void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup ADC_Exported_Functions_Group3
|
|||
* @{ |
|||
*/ |
|||
/* Peripheral Control functions *************************************************/ |
|||
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig); |
|||
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup ADC_Exported_Functions_Group4
|
|||
* @{ |
|||
*/ |
|||
/* Peripheral State functions ***************************************************/ |
|||
HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc); |
|||
uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
/* Private types -------------------------------------------------------------*/ |
|||
/* Private variables ---------------------------------------------------------*/ |
|||
/* Private constants ---------------------------------------------------------*/ |
|||
/** @defgroup ADC_Private_Constants ADC Private Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private macros ------------------------------------------------------------*/ |
|||
/** @defgroup ADC_Private_Macros ADC Private Macros
|
|||
* @{ |
|||
*/ |
|||
#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV2) || \ |
|||
((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV4) || \ |
|||
((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV6) || \ |
|||
((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV8)) |
|||
#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \ |
|||
((DELAY) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \ |
|||
((DELAY) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \ |
|||
((DELAY) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \ |
|||
((DELAY) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \ |
|||
((DELAY) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \ |
|||
((DELAY) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \ |
|||
((DELAY) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \ |
|||
((DELAY) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \ |
|||
((DELAY) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \ |
|||
((DELAY) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \ |
|||
((DELAY) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \ |
|||
((DELAY) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \ |
|||
((DELAY) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \ |
|||
((DELAY) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \ |
|||
((DELAY) == ADC_TWOSAMPLINGDELAY_20CYCLES)) |
|||
#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \ |
|||
((RESOLUTION) == ADC_RESOLUTION_10B) || \ |
|||
((RESOLUTION) == ADC_RESOLUTION_8B) || \ |
|||
((RESOLUTION) == ADC_RESOLUTION_6B)) |
|||
#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ |
|||
((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ |
|||
((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ |
|||
((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING)) |
|||
#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ |
|||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \ |
|||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \ |
|||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ |
|||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \ |
|||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC4) || \ |
|||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \ |
|||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \ |
|||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ |
|||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \ |
|||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1) || \ |
|||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC2) || \ |
|||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3) || \ |
|||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || \ |
|||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \ |
|||
((REGTRIG) == ADC_EXTERNALTRIGCONV_Ext_IT11)) |
|||
#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ |
|||
((ALIGN) == ADC_DATAALIGN_LEFT)) |
|||
#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ |
|||
((CHANNEL) == ADC_CHANNEL_1) || \ |
|||
((CHANNEL) == ADC_CHANNEL_2) || \ |
|||
((CHANNEL) == ADC_CHANNEL_3) || \ |
|||
((CHANNEL) == ADC_CHANNEL_4) || \ |
|||
((CHANNEL) == ADC_CHANNEL_5) || \ |
|||
((CHANNEL) == ADC_CHANNEL_6) || \ |
|||
((CHANNEL) == ADC_CHANNEL_7) || \ |
|||
((CHANNEL) == ADC_CHANNEL_8) || \ |
|||
((CHANNEL) == ADC_CHANNEL_9) || \ |
|||
((CHANNEL) == ADC_CHANNEL_10) || \ |
|||
((CHANNEL) == ADC_CHANNEL_11) || \ |
|||
((CHANNEL) == ADC_CHANNEL_12) || \ |
|||
((CHANNEL) == ADC_CHANNEL_13) || \ |
|||
((CHANNEL) == ADC_CHANNEL_14) || \ |
|||
((CHANNEL) == ADC_CHANNEL_15) || \ |
|||
((CHANNEL) == ADC_CHANNEL_16) || \ |
|||
((CHANNEL) == ADC_CHANNEL_17) || \ |
|||
((CHANNEL) == ADC_CHANNEL_18)) |
|||
#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_3CYCLES) || \ |
|||
((TIME) == ADC_SAMPLETIME_15CYCLES) || \ |
|||
((TIME) == ADC_SAMPLETIME_28CYCLES) || \ |
|||
((TIME) == ADC_SAMPLETIME_56CYCLES) || \ |
|||
((TIME) == ADC_SAMPLETIME_84CYCLES) || \ |
|||
((TIME) == ADC_SAMPLETIME_112CYCLES) || \ |
|||
((TIME) == ADC_SAMPLETIME_144CYCLES) || \ |
|||
((TIME) == ADC_SAMPLETIME_480CYCLES)) |
|||
#define IS_ADC_EOCSelection(EOCSelection) (((EOCSelection) == ADC_EOC_SINGLE_CONV) || \ |
|||
((EOCSelection) == ADC_EOC_SEQ_CONV) || \ |
|||
((EOCSelection) == ADC_EOC_SINGLE_SEQ_CONV)) |
|||
#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \ |
|||
((EVENT) == ADC_OVR_EVENT)) |
|||
#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ |
|||
((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ |
|||
((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ |
|||
((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \ |
|||
((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ |
|||
((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) || \ |
|||
((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE)) |
|||
#define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ADC_ALL_CHANNELS) || \ |
|||
((CHANNEL_TYPE) == ADC_REGULAR_CHANNELS) || \ |
|||
((CHANNEL_TYPE) == ADC_INJECTED_CHANNELS)) |
|||
#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= ((uint32_t)0xFFF)) |
|||
|
|||
#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)16))) |
|||
#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= ((uint32_t)1)) && ((RANK) <= ((uint32_t)16))) |
|||
#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8))) |
|||
#define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \ |
|||
((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= ((uint32_t)0x0FFF))) || \ |
|||
(((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= ((uint32_t)0x03FF))) || \ |
|||
(((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= ((uint32_t)0x00FF))) || \ |
|||
(((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= ((uint32_t)0x003F)))) |
|||
|
|||
/**
|
|||
* @brief Set ADC Regular channel sequence length. |
|||
* @param _NbrOfConversion_: Regular channel sequence length. |
|||
* @retval None |
|||
*/ |
|||
#define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << 20) |
|||
|
|||
/**
|
|||
* @brief Set the ADC's sample time for channel numbers between 10 and 18. |
|||
* @param _SAMPLETIME_: Sample time parameter. |
|||
* @param _CHANNELNB_: Channel number. |
|||
* @retval None |
|||
*/ |
|||
#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10))) |
|||
|
|||
/**
|
|||
* @brief Set the ADC's sample time for channel numbers between 0 and 9. |
|||
* @param _SAMPLETIME_: Sample time parameter. |
|||
* @param _CHANNELNB_: Channel number. |
|||
* @retval None |
|||
*/ |
|||
#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((uint32_t)((uint16_t)(_CHANNELNB_))))) |
|||
|
|||
/**
|
|||
* @brief Set the selected regular channel rank for rank between 1 and 6. |
|||
* @param _CHANNELNB_: Channel number. |
|||
* @param _RANKNB_: Rank number. |
|||
* @retval None |
|||
*/ |
|||
#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 1))) |
|||
|
|||
/**
|
|||
* @brief Set the selected regular channel rank for rank between 7 and 12. |
|||
* @param _CHANNELNB_: Channel number. |
|||
* @param _RANKNB_: Rank number. |
|||
* @retval None |
|||
*/ |
|||
#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 7))) |
|||
|
|||
/**
|
|||
* @brief Set the selected regular channel rank for rank between 13 and 16. |
|||
* @param _CHANNELNB_: Channel number. |
|||
* @param _RANKNB_: Rank number. |
|||
* @retval None |
|||
*/ |
|||
#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 13))) |
|||
|
|||
/**
|
|||
* @brief Enable ADC continuous conversion mode. |
|||
* @param _CONTINUOUS_MODE_: Continuous mode. |
|||
* @retval None |
|||
*/ |
|||
#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1) |
|||
|
|||
/**
|
|||
* @brief Configures the number of discontinuous conversions for the regular group channels. |
|||
* @param _NBR_DISCONTINUOUSCONV_: Number of discontinuous conversions. |
|||
* @retval None |
|||
*/ |
|||
#define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1) << 13) |
|||
|
|||
/**
|
|||
* @brief Enable ADC scan mode. |
|||
* @param _SCANCONV_MODE_: Scan conversion mode. |
|||
* @retval None |
|||
*/ |
|||
#define ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8) |
|||
|
|||
/**
|
|||
* @brief Enable the ADC end of conversion selection. |
|||
* @param _EOCSelection_MODE_: End of conversion selection mode. |
|||
* @retval None |
|||
*/ |
|||
#define ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10) |
|||
|
|||
/**
|
|||
* @brief Enable the ADC DMA continuous request. |
|||
* @param _DMAContReq_MODE_: DMA continuous request mode. |
|||
* @retval None |
|||
*/ |
|||
#define ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9) |
|||
|
|||
/**
|
|||
* @brief Return resolution bits in CR1 register. |
|||
* @param __HANDLE__: ADC handle |
|||
* @retval None |
|||
*/ |
|||
#define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES) |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private functions ---------------------------------------------------------*/ |
|||
/** @defgroup ADC_Private_Functions ADC Private Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif /*__STM32F4xx_ADC_H */ |
|||
|
|||
|
|||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
@ -0,0 +1,340 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32f4xx_hal_adc.h |
|||
* @author MCD Application Team |
|||
* @version V1.2.0 |
|||
* @date 26-December-2014 |
|||
* @brief Header file of ADC HAL module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
|||
* |
|||
* Redistribution and use in source and binary forms, with or without modification, |
|||
* are permitted provided that the following conditions are met: |
|||
* 1. Redistributions of source code must retain the above copyright notice, |
|||
* this list of conditions and the following disclaimer. |
|||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
|||
* this list of conditions and the following disclaimer in the documentation |
|||
* and/or other materials provided with the distribution. |
|||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
|||
* may be used to endorse or promote products derived from this software |
|||
* without specific prior written permission. |
|||
* |
|||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
|||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
|||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
|||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
|||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
|||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
|||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
|||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
|||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
|||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef __STM32F4xx_ADC_EX_H |
|||
#define __STM32F4xx_ADC_EX_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32f4xx_hal_def.h" |
|||
|
|||
/** @addtogroup STM32F4xx_HAL_Driver
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup ADCEx
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Exported types ------------------------------------------------------------*/ |
|||
/** @defgroup ADCEx_Exported_Types ADC Exported Types
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @brief ADC Configuration injected Channel structure definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t InjectedChannel; /*!< Configure the ADC injected channel.
|
|||
This parameter can be a value of @ref ADC_channels */ |
|||
uint32_t InjectedRank; /*!< The rank in the injected group sequencer
|
|||
This parameter must be a number between Min_Data = 1 and Max_Data = 4. */ |
|||
uint32_t InjectedSamplingTime; /*!< The sample time value to be set for the selected channel.
|
|||
This parameter can be a value of @ref ADC_sampling_times */ |
|||
uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data when convert injected channels.
|
|||
This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ |
|||
uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ADC conversions that will be done using the sequencer for
|
|||
injected channel group. |
|||
This parameter must be a number between Min_Data = 1 and Max_Data = 4. */ |
|||
uint32_t AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group
|
|||
conversion after regular one */ |
|||
uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversion is performed in Discontinuous mode or not for injected channels.
|
|||
This parameter can be set to ENABLE or DISABLE. */ |
|||
uint32_t ExternalTrigInjecConvEdge; /*!< Select the external trigger edge and enable the trigger of an injected channels.
|
|||
This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected */ |
|||
uint32_t ExternalTrigInjecConv; /*!< Select the external event used to trigger the start of conversion of a injected channels.
|
|||
This parameter can be a value of @ref ADCEx_External_trigger_Source_Injected */ |
|||
}ADC_InjectionConfTypeDef; |
|||
|
|||
/**
|
|||
* @brief ADC Configuration multi-mode structure definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t Mode; /*!< Configures the ADC to operate in independent or multi mode.
|
|||
This parameter can be a value of @ref ADCEx_Common_mode */ |
|||
uint32_t DMAAccessMode; /*!< Configures the Direct memory access mode for multi ADC mode.
|
|||
This parameter can be a value of @ref ADCEx_Direct_memory_access_mode_for_multi_mode */ |
|||
uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.
|
|||
This parameter can be a value of @ref ADC_delay_between_2_sampling_phases */ |
|||
}ADC_MultiModeTypeDef; |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported constants --------------------------------------------------------*/ |
|||
/** @defgroup ADCEx_Exported_Constants ADC Exported Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup ADCEx_Common_mode ADC Common Mode
|
|||
* @{ |
|||
*/ |
|||
#define ADC_MODE_INDEPENDENT ((uint32_t)0x00000000) |
|||
#define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)ADC_CCR_MULTI_0) |
|||
#define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)ADC_CCR_MULTI_1) |
|||
#define ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0)) |
|||
#define ADC_DUALMODE_REGSIMULT ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1)) |
|||
#define ADC_DUALMODE_INTERL ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0)) |
|||
#define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0)) |
|||
#define ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0)) |
|||
#define ADC_TRIPLEMODE_REGSIMULT_AlterTrig ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_1)) |
|||
#define ADC_TRIPLEMODE_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0)) |
|||
#define ADC_TRIPLEMODE_REGSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1)) |
|||
#define ADC_TRIPLEMODE_INTERL ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0)) |
|||
#define ADC_TRIPLEMODE_ALTERTRIG ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0)) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup ADCEx_Direct_memory_access_mode_for_multi_mode ADC Direct Memory Access Mode For Multi Mode
|
|||
* @{ |
|||
*/ |
|||
#define ADC_DMAACCESSMODE_DISABLED ((uint32_t)0x00000000) /*!< DMA mode disabled */ |
|||
#define ADC_DMAACCESSMODE_1 ((uint32_t)ADC_CCR_DMA_0) /*!< DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/ |
|||
#define ADC_DMAACCESSMODE_2 ((uint32_t)ADC_CCR_DMA_1) /*!< DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/ |
|||
#define ADC_DMAACCESSMODE_3 ((uint32_t)ADC_CCR_DMA) /*!< DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup ADCEx_External_trigger_edge_Injected ADC External Trigger Edge Injected
|
|||
* @{ |
|||
*/ |
|||
#define ADC_EXTERNALTRIGINJECCONVEDGE_NONE ((uint32_t)0x00000000) |
|||
#define ADC_EXTERNALTRIGINJECCONVEDGE_RISING ((uint32_t)ADC_CR2_JEXTEN_0) |
|||
#define ADC_EXTERNALTRIGINJECCONVEDGE_FALLING ((uint32_t)ADC_CR2_JEXTEN_1) |
|||
#define ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_JEXTEN) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup ADCEx_External_trigger_Source_Injected ADC External Trigger Source Injected
|
|||
* @{ |
|||
*/ |
|||
#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ((uint32_t)0x00000000) |
|||
#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ((uint32_t)ADC_CR2_JEXTSEL_0) |
|||
#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ((uint32_t)ADC_CR2_JEXTSEL_1) |
|||
#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) |
|||
#define ADC_EXTERNALTRIGINJECCONV_T3_CC2 ((uint32_t)ADC_CR2_JEXTSEL_2) |
|||
#define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0)) |
|||
#define ADC_EXTERNALTRIGINJECCONV_T4_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1)) |
|||
#define ADC_EXTERNALTRIGINJECCONV_T4_CC2 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) |
|||
#define ADC_EXTERNALTRIGINJECCONV_T4_CC3 ((uint32_t)ADC_CR2_JEXTSEL_3) |
|||
#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0)) |
|||
#define ADC_EXTERNALTRIGINJECCONV_T5_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1)) |
|||
#define ADC_EXTERNALTRIGINJECCONV_T5_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) |
|||
#define ADC_EXTERNALTRIGINJECCONV_T8_CC2 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2)) |
|||
#define ADC_EXTERNALTRIGINJECCONV_T8_CC3 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0)) |
|||
#define ADC_EXTERNALTRIGINJECCONV_T8_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1)) |
|||
#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ((uint32_t)ADC_CR2_JEXTSEL) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup ADCEx_injected_channel_selection ADC Injected Channel Selection
|
|||
* @{ |
|||
*/ |
|||
#define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001) |
|||
#define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002) |
|||
#define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003) |
|||
#define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup ADCEx_channels ADC Specific Channels
|
|||
* @{ |
|||
*/ |
|||
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ |
|||
defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) |
|||
#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_16) |
|||
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ |
|||
|
|||
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) |
|||
#define ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT ((uint32_t)0x10000000) /* Dummy bit for driver internal usage, not used in ADC channel setting registers CR1 or SQRx */ |
|||
#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_18 | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT) |
|||
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F411xE */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported macro ------------------------------------------------------------*/ |
|||
/** @defgroup ADC_Exported_Macros ADC Exported Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @addtogroup ADCEx_Exported_Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup ADCEx_Exported_Functions_Group1
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* I/O operation functions ******************************************************/ |
|||
HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc); |
|||
HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc); |
|||
HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc); |
|||
HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc); |
|||
uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank); |
|||
HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); |
|||
HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc); |
|||
uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc); |
|||
void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc); |
|||
|
|||
/* Peripheral Control functions *************************************************/ |
|||
HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected); |
|||
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode); |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
/* Private types -------------------------------------------------------------*/ |
|||
/* Private variables ---------------------------------------------------------*/ |
|||
/* Private constants ---------------------------------------------------------*/ |
|||
/** @defgroup ADCEx_Private_Constants ADC Private Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private macros ------------------------------------------------------------*/ |
|||
/** @defgroup ADCEx_Private_Macros ADC Private Macros
|
|||
* @{ |
|||
*/ |
|||
#define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT) || \ |
|||
((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \ |
|||
((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \ |
|||
((MODE) == ADC_DUALMODE_INJECSIMULT) || \ |
|||
((MODE) == ADC_DUALMODE_REGSIMULT) || \ |
|||
((MODE) == ADC_DUALMODE_INTERL) || \ |
|||
((MODE) == ADC_DUALMODE_ALTERTRIG) || \ |
|||
((MODE) == ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT) || \ |
|||
((MODE) == ADC_TRIPLEMODE_REGSIMULT_AlterTrig) || \ |
|||
((MODE) == ADC_TRIPLEMODE_INJECSIMULT) || \ |
|||
((MODE) == ADC_TRIPLEMODE_REGSIMULT) || \ |
|||
((MODE) == ADC_TRIPLEMODE_INTERL) || \ |
|||
((MODE) == ADC_TRIPLEMODE_ALTERTRIG)) |
|||
#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAACCESSMODE_DISABLED) || \ |
|||
((MODE) == ADC_DMAACCESSMODE_1) || \ |
|||
((MODE) == ADC_DMAACCESSMODE_2) || \ |
|||
((MODE) == ADC_DMAACCESSMODE_3)) |
|||
#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_NONE) || \ |
|||
((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_RISING) || \ |
|||
((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_FALLING) || \ |
|||
((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING)) |
|||
#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \ |
|||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \ |
|||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ |
|||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ |
|||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC2) || \ |
|||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ |
|||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC1) || \ |
|||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC2) || \ |
|||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \ |
|||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ |
|||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || \ |
|||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO) || \ |
|||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || \ |
|||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC3) || \ |
|||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \ |
|||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15)) |
|||
#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)4))) |
|||
#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= ((uint32_t)1)) && ((RANK) <= ((uint32_t)4))) |
|||
|
|||
/**
|
|||
* @brief Set the selected injected Channel rank. |
|||
* @param _CHANNELNB_: Channel number. |
|||
* @param _RANKNB_: Rank number. |
|||
* @param _JSQR_JL_: Sequence length. |
|||
* @retval None |
|||
*/ |
|||
#define ADC_JSQR(_CHANNELNB_, _RANKNB_, _JSQR_JL_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * (uint8_t)(((_RANKNB_) + 3) - (_JSQR_JL_)))) |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private functions ---------------------------------------------------------*/ |
|||
/** @defgroup ADCEx_Private_Functions ADC Private Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif /*__STM32F4xx_ADC_EX_H */ |
|||
|
|||
|
|||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
@ -0,0 +1,773 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32f4xx_hal_can.h |
|||
* @author MCD Application Team |
|||
* @version V1.2.0 |
|||
* @date 26-December-2014 |
|||
* @brief Header file of CAN HAL module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
|||
* |
|||
* Redistribution and use in source and binary forms, with or without modification, |
|||
* are permitted provided that the following conditions are met: |
|||
* 1. Redistributions of source code must retain the above copyright notice, |
|||
* this list of conditions and the following disclaimer. |
|||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
|||
* this list of conditions and the following disclaimer in the documentation |
|||
* and/or other materials provided with the distribution. |
|||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
|||
* may be used to endorse or promote products derived from this software |
|||
* without specific prior written permission. |
|||
* |
|||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
|||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
|||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
|||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
|||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
|||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
|||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
|||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
|||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
|||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef __STM32F4xx_HAL_CAN_H |
|||
#define __STM32F4xx_HAL_CAN_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) |
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32f4xx_hal_def.h" |
|||
|
|||
/** @addtogroup STM32F4xx_HAL_Driver
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup CAN
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Exported types ------------------------------------------------------------*/ |
|||
/** @defgroup CAN_Exported_Types CAN Exported Types
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @brief HAL State structures definition |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_CAN_STATE_RESET = 0x00, /*!< CAN not yet initialized or disabled */ |
|||
HAL_CAN_STATE_READY = 0x01, /*!< CAN initialized and ready for use */ |
|||
HAL_CAN_STATE_BUSY = 0x02, /*!< CAN process is ongoing */ |
|||
HAL_CAN_STATE_BUSY_TX = 0x12, /*!< CAN process is ongoing */ |
|||
HAL_CAN_STATE_BUSY_RX = 0x22, /*!< CAN process is ongoing */ |
|||
HAL_CAN_STATE_BUSY_TX_RX = 0x32, /*!< CAN process is ongoing */ |
|||
HAL_CAN_STATE_TIMEOUT = 0x03, /*!< Timeout state */ |
|||
HAL_CAN_STATE_ERROR = 0x04 /*!< CAN error state */ |
|||
|
|||
}HAL_CAN_StateTypeDef; |
|||
|
|||
/**
|
|||
* @brief CAN init structure definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t Prescaler; /*!< Specifies the length of a time quantum.
|
|||
This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */ |
|||
|
|||
uint32_t Mode; /*!< Specifies the CAN operating mode.
|
|||
This parameter can be a value of @ref CAN_operating_mode */ |
|||
|
|||
uint32_t SJW; /*!< Specifies the maximum number of time quanta
|
|||
the CAN hardware is allowed to lengthen or |
|||
shorten a bit to perform resynchronization. |
|||
This parameter can be a value of @ref CAN_synchronisation_jump_width */ |
|||
|
|||
uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1.
|
|||
This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */ |
|||
|
|||
uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
|
|||
This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ |
|||
|
|||
uint32_t TTCM; /*!< Enable or disable the time triggered communication mode.
|
|||
This parameter can be set to ENABLE or DISABLE. */ |
|||
|
|||
uint32_t ABOM; /*!< Enable or disable the automatic bus-off management.
|
|||
This parameter can be set to ENABLE or DISABLE */ |
|||
|
|||
uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode.
|
|||
This parameter can be set to ENABLE or DISABLE */ |
|||
|
|||
uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode.
|
|||
This parameter can be set to ENABLE or DISABLE */ |
|||
|
|||
uint32_t RFLM; /*!< Enable or disable the receive FIFO Locked mode.
|
|||
This parameter can be set to ENABLE or DISABLE */ |
|||
|
|||
uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority.
|
|||
This parameter can be set to ENABLE or DISABLE */ |
|||
}CAN_InitTypeDef; |
|||
|
|||
/**
|
|||
* @brief CAN filter configuration structure definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
|
|||
configuration, first one for a 16-bit configuration). |
|||
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
|||
|
|||
uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
|
|||
configuration, second one for a 16-bit configuration). |
|||
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
|||
|
|||
uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
|
|||
according to the mode (MSBs for a 32-bit configuration, |
|||
first one for a 16-bit configuration). |
|||
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
|||
|
|||
uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
|
|||
according to the mode (LSBs for a 32-bit configuration, |
|||
second one for a 16-bit configuration). |
|||
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
|||
|
|||
uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
|
|||
This parameter can be a value of @ref CAN_filter_FIFO */ |
|||
|
|||
uint32_t FilterNumber; /*!< Specifies the filter which will be initialized.
|
|||
This parameter must be a number between Min_Data = 0 and Max_Data = 27 */ |
|||
|
|||
uint32_t FilterMode; /*!< Specifies the filter mode to be initialized.
|
|||
|