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538 lines
16 KiB
538 lines
16 KiB
/*!
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\file gd32vf103_dac.c
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\brief DAC driver
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\version 2019-06-05, V1.0.0, firmware for GD32VF103
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*/
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/*
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Copyright (c) 2019, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#include "gd32vf103_dac.h"
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/* DAC register bit offset */
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#define DAC1_REG_OFFSET ((uint32_t)16U)
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#define DH_12BIT_OFFSET ((uint32_t)16U)
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#define DH_8BIT_OFFSET ((uint32_t)8U)
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/*!
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\brief deinitialize DAC
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\param[in] none
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\param[out] none
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\retval none
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*/
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void dac_deinit(void)
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{
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rcu_periph_reset_enable(RCU_DACRST);
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rcu_periph_reset_disable(RCU_DACRST);
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}
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/*!
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\brief enable DAC
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\param[in] dac_periph: DACx(x = 0,1)
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\param[out] none
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\retval none
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*/
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void dac_enable(uint32_t dac_periph)
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{
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if(DAC0 == dac_periph){
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DAC_CTL |= DAC_CTL_DEN0;
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}else{
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DAC_CTL |= DAC_CTL_DEN1;
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}
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}
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/*!
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\brief disable DAC
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\param[in] dac_periph: DACx(x = 0,1)
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\param[out] none
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\retval none
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*/
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void dac_disable(uint32_t dac_periph)
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{
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if(DAC0 == dac_periph){
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DAC_CTL &= ~DAC_CTL_DEN0;
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}else{
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DAC_CTL &= ~DAC_CTL_DEN1;
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}
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}
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/*!
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\brief enable DAC DMA function
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\param[in] dac_periph: DACx(x = 0,1)
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\param[out] none
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\retval none
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*/
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void dac_dma_enable(uint32_t dac_periph)
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{
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if(DAC0 == dac_periph){
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DAC_CTL |= DAC_CTL_DDMAEN0;
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}else{
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DAC_CTL |= DAC_CTL_DDMAEN1;
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}
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}
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/*!
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\brief disable DAC DMA function
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\param[in] dac_periph: DACx(x = 0,1)
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\param[out] none
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\retval none
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*/
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void dac_dma_disable(uint32_t dac_periph)
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{
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if(DAC0 == dac_periph){
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DAC_CTL &= ~DAC_CTL_DDMAEN0;
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}else{
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DAC_CTL &= ~DAC_CTL_DDMAEN1;
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}
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}
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/*!
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\brief enable DAC output buffer
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\param[in] dac_periph: DACx(x = 0,1)
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\param[out] none
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\retval none
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*/
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void dac_output_buffer_enable(uint32_t dac_periph)
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{
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if(DAC0 == dac_periph){
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DAC_CTL &= ~DAC_CTL_DBOFF0;
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}else{
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DAC_CTL &= ~DAC_CTL_DBOFF1;
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}
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}
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/*!
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\brief disable DAC output buffer
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\param[in] dac_periph: DACx(x = 0,1)
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\param[out] none
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\retval none
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*/
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void dac_output_buffer_disable(uint32_t dac_periph)
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{
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if(DAC0 == dac_periph){
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DAC_CTL |= DAC_CTL_DBOFF0;
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}else{
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DAC_CTL |= DAC_CTL_DBOFF1;
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}
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}
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/*!
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\brief get DAC output value
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\param[in] dac_periph: DACx(x = 0,1)
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\param[out] none
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\retval DAC output data
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*/
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uint16_t dac_output_value_get(uint32_t dac_periph)
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{
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uint16_t data = 0U;
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if(DAC0 == dac_periph){
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/* store the DAC0 output value */
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data = (uint16_t)DAC0_DO;
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}else{
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/* store the DAC1 output value */
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data = (uint16_t)DAC1_DO;
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}
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return data;
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}
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/*!
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\brief set the DAC specified data holding register value
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\param[in] dac_periph: DACx(x = 0,1)
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\param[in] dac_align: data alignment
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only one parameter can be selected which is shown as below:
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\arg DAC_ALIGN_8B_R: data right 8 bit alignment
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\arg DAC_ALIGN_12B_R: data right 12 bit alignment
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\arg DAC_ALIGN_12B_L: data left 12 bit alignment
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\param[in] data: data to be loaded
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\param[out] none
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\retval none
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*/
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void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data)
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{
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if(DAC0 == dac_periph){
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switch(dac_align){
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/* data right 12 bit alignment */
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case DAC_ALIGN_12B_R:
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DAC0_R12DH = data;
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break;
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/* data left 12 bit alignment */
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case DAC_ALIGN_12B_L:
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DAC0_L12DH = data;
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break;
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/* data right 8 bit alignment */
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case DAC_ALIGN_8B_R:
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DAC0_R8DH = data;
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break;
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default:
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break;
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}
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}else{
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switch(dac_align){
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/* data right 12 bit alignment */
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case DAC_ALIGN_12B_R:
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DAC1_R12DH = data;
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break;
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/* data left 12 bit alignment */
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case DAC_ALIGN_12B_L:
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DAC1_L12DH = data;
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break;
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/* data right 8 bit alignment */
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case DAC_ALIGN_8B_R:
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DAC1_R8DH = data;
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break;
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default:
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break;
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}
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}
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}
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/*!
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\brief enable DAC trigger
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\param[in] dac_periph: DACx(x = 0,1)
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\param[out] none
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\retval none
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*/
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void dac_trigger_enable(uint32_t dac_periph)
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{
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if(DAC0 == dac_periph){
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DAC_CTL |= DAC_CTL_DTEN0;
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}else{
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DAC_CTL |= DAC_CTL_DTEN1;
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}
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}
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/*!
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\brief disable DAC trigger
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\param[in] dac_periph: DACx(x = 0,1)
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\param[out] none
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\retval none
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*/
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void dac_trigger_disable(uint32_t dac_periph)
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{
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if(DAC0 == dac_periph){
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DAC_CTL &= ~DAC_CTL_DTEN0;
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}else{
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DAC_CTL &= ~DAC_CTL_DTEN1;
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}
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}
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/*!
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\brief set DAC trigger source
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\param[in] dac_periph: DACx(x = 0,1)
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\param[in] triggersource: external triggers of DAC
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only one parameter can be selected which is shown as below:
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\arg DAC_TRIGGER_T1_TRGO: TIMER1 TRGO
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\arg DAC_TRIGGER_T2_TRGO: TIMER2 TRGO
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\arg DAC_TRIGGER_T3_TRGO: TIMER3 TRGO
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\arg DAC_TRIGGER_T4_TRGO: TIMER4 TRGO
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\arg DAC_TRIGGER_T5_TRGO: TIMER5 TRGO
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\arg DAC_TRIGGER_T6_TRGO: TIMER6 TRGO
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\arg DAC_TRIGGER_EXTI_9: EXTI interrupt line9 event
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\arg DAC_TRIGGER_SOFTWARE: software trigger
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\param[out] none
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\retval none
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*/
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void dac_trigger_source_config(uint32_t dac_periph,uint32_t triggersource)
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{
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if(DAC0 == dac_periph){
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/* configure DAC0 trigger source */
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DAC_CTL &= ~DAC_CTL_DTSEL0;
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DAC_CTL |= triggersource;
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}else{
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/* configure DAC1 trigger source */
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DAC_CTL &= ~DAC_CTL_DTSEL1;
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DAC_CTL |= (triggersource << DAC1_REG_OFFSET);
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}
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}
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/*!
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\brief enable DAC software trigger
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\param[in] dac_periph: DACx(x = 0,1)
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\retval none
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*/
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void dac_software_trigger_enable(uint32_t dac_periph)
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{
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if(DAC0 == dac_periph){
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DAC_SWT |= DAC_SWT_SWTR0;
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}else{
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DAC_SWT |= DAC_SWT_SWTR1;
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}
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}
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/*!
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\brief disable DAC software trigger
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\param[in] dac_periph: DACx(x = 0,1)
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\param[out] none
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\retval none
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*/
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void dac_software_trigger_disable(uint32_t dac_periph)
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{
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if(DAC0 == dac_periph){
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DAC_SWT &= ~DAC_SWT_SWTR0;
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}else{
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DAC_SWT &= ~DAC_SWT_SWTR1;
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}
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}
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/*!
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\brief configure DAC wave mode
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\param[in] dac_periph: DACx(x = 0,1)
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\param[in] wave_mode: noise wave mode
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only one parameter can be selected which is shown as below:
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\arg DAC_WAVE_DISABLE: wave disable
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\arg DAC_WAVE_MODE_LFSR: LFSR noise mode
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\arg DAC_WAVE_MODE_TRIANGLE: triangle noise mode
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\param[out] none
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\retval none
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*/
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void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode)
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{
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if(DAC0 == dac_periph){
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/* configure DAC0 wave mode */
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DAC_CTL &= ~DAC_CTL_DWM0;
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DAC_CTL |= wave_mode;
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}else{
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/* configure DAC1 wave mode */
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DAC_CTL &= ~DAC_CTL_DWM1;
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DAC_CTL |= (wave_mode << DAC1_REG_OFFSET);
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}
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}
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/*!
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\brief configure DAC wave bit width
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\param[in] dac_periph: DACx(x = 0,1)
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\param[in] bit_width: noise wave bit width
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only one parameter can be selected which is shown as below:
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\arg DAC_WAVE_BIT_WIDTH_1: bit width of the wave signal is 1
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\arg DAC_WAVE_BIT_WIDTH_2: bit width of the wave signal is 2
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\arg DAC_WAVE_BIT_WIDTH_3: bit width of the wave signal is 3
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\arg DAC_WAVE_BIT_WIDTH_4: bit width of the wave signal is 4
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\arg DAC_WAVE_BIT_WIDTH_5: bit width of the wave signal is 5
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\arg DAC_WAVE_BIT_WIDTH_6: bit width of the wave signal is 6
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\arg DAC_WAVE_BIT_WIDTH_7: bit width of the wave signal is 7
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\arg DAC_WAVE_BIT_WIDTH_8: bit width of the wave signal is 8
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\arg DAC_WAVE_BIT_WIDTH_9: bit width of the wave signal is 9
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\arg DAC_WAVE_BIT_WIDTH_10: bit width of the wave signal is 10
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\arg DAC_WAVE_BIT_WIDTH_11: bit width of the wave signal is 11
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\arg DAC_WAVE_BIT_WIDTH_12: bit width of the wave signal is 12
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\param[out] none
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\retval none
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*/
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void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width)
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{
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if(DAC0 == dac_periph){
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/* configure DAC0 wave bit width */
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DAC_CTL &= ~DAC_CTL_DWBW0;
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DAC_CTL |= bit_width;
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}else{
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/* configure DAC1 wave bit width */
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DAC_CTL &= ~DAC_CTL_DWBW1;
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DAC_CTL |= (bit_width << DAC1_REG_OFFSET);
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}
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}
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/*!
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\brief configure DAC LFSR noise mode
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\param[in] dac_periph: DACx(x = 0,1)
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\param[in] unmask_bits: unmask LFSR bits in DAC LFSR noise mode
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only one parameter can be selected which is shown as below:
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\arg DAC_LFSR_BIT0: unmask the LFSR bit0
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\arg DAC_LFSR_BITS1_0: unmask the LFSR bits[1:0]
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\arg DAC_LFSR_BITS2_0: unmask the LFSR bits[2:0]
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\arg DAC_LFSR_BITS3_0: unmask the LFSR bits[3:0]
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\arg DAC_LFSR_BITS4_0: unmask the LFSR bits[4:0]
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\arg DAC_LFSR_BITS5_0: unmask the LFSR bits[5:0]
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\arg DAC_LFSR_BITS6_0: unmask the LFSR bits[6:0]
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\arg DAC_LFSR_BITS7_0: unmask the LFSR bits[7:0]
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\arg DAC_LFSR_BITS8_0: unmask the LFSR bits[8:0]
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\arg DAC_LFSR_BITS9_0: unmask the LFSR bits[9:0]
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\arg DAC_LFSR_BITS10_0: unmask the LFSR bits[10:0]
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\arg DAC_LFSR_BITS11_0: unmask the LFSR bits[11:0]
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\param[out] none
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\retval none
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*/
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void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits)
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{
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if(DAC0 == dac_periph){
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/* configure DAC0 LFSR noise mode */
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DAC_CTL &= ~DAC_CTL_DWBW0;
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DAC_CTL |= unmask_bits;
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}else{
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/* configure DAC1 LFSR noise mode */
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DAC_CTL &= ~DAC_CTL_DWBW1;
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DAC_CTL |= (unmask_bits << DAC1_REG_OFFSET);
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}
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}
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/*!
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\brief configure DAC triangle noise mode
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\param[in] dac_periph: DACx(x = 0,1)
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\param[in] amplitude: triangle amplitude in DAC triangle noise mode
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only one parameter can be selected which is shown as below:
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\arg DAC_TRIANGLE_AMPLITUDE_1: triangle amplitude is 1
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\arg DAC_TRIANGLE_AMPLITUDE_3: triangle amplitude is 3
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\arg DAC_TRIANGLE_AMPLITUDE_7: triangle amplitude is 7
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\arg DAC_TRIANGLE_AMPLITUDE_15: triangle amplitude is 15
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\arg DAC_TRIANGLE_AMPLITUDE_31: triangle amplitude is 31
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\arg DAC_TRIANGLE_AMPLITUDE_63: triangle amplitude is 63
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\arg DAC_TRIANGLE_AMPLITUDE_127: triangle amplitude is 127
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\arg DAC_TRIANGLE_AMPLITUDE_255: triangle amplitude is 255
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\arg DAC_TRIANGLE_AMPLITUDE_511: triangle amplitude is 511
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\arg DAC_TRIANGLE_AMPLITUDE_1023: triangle amplitude is 1023
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\arg DAC_TRIANGLE_AMPLITUDE_2047: triangle amplitude is 2047
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\arg DAC_TRIANGLE_AMPLITUDE_4095: triangle amplitude is 4095
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\param[out] none
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\retval none
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*/
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void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude)
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{
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if(DAC0 == dac_periph){
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/* configure DAC0 triangle noise mode */
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DAC_CTL &= ~DAC_CTL_DWBW0;
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DAC_CTL |= amplitude;
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}else{
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/* configure DAC1 triangle noise mode */
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DAC_CTL &= ~DAC_CTL_DWBW1;
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DAC_CTL |= (amplitude << DAC1_REG_OFFSET);
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}
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}
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/*!
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\brief enable DAC concurrent mode
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\param[in] none
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\param[out] none
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\retval none
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*/
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void dac_concurrent_enable(void)
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{
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uint32_t ctl = 0U;
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ctl = DAC_CTL_DEN0 | DAC_CTL_DEN1;
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DAC_CTL |= (ctl);
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}
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/*!
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\brief disable DAC concurrent mode
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\param[in] none
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\param[out] none
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\retval none
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*/
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void dac_concurrent_disable(void)
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{
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uint32_t ctl = 0U;
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ctl = DAC_CTL_DEN0 | DAC_CTL_DEN1;
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DAC_CTL &= (~ctl);
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}
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/*!
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\brief enable DAC concurrent software trigger function
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\param[in] none
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\param[out] none
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\retval none
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*/
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void dac_concurrent_software_trigger_enable(void)
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{
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uint32_t swt = 0U;
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swt = DAC_SWT_SWTR0 | DAC_SWT_SWTR1;
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DAC_SWT |= (swt);
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}
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/*!
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\brief disable DAC concurrent software trigger function
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\param[in] none
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\param[out] none
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\retval none
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*/
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void dac_concurrent_software_trigger_disable(void)
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{
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uint32_t swt = 0U;
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swt = DAC_SWT_SWTR0 | DAC_SWT_SWTR1;
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DAC_SWT &= (~swt);
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}
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/*!
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\brief enable DAC concurrent buffer function
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\param[in] none
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\param[out] none
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\retval none
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*/
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void dac_concurrent_output_buffer_enable(void)
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{
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uint32_t ctl = 0U;
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ctl = DAC_CTL_DBOFF0 | DAC_CTL_DBOFF1;
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DAC_CTL &= (~ctl);
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}
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/*!
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\brief disable DAC concurrent buffer function
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\param[in] none
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\param[out] none
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\retval none
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*/
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void dac_concurrent_output_buffer_disable(void)
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{
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uint32_t ctl = 0U;
|
|
ctl = DAC_CTL_DBOFF0 | DAC_CTL_DBOFF1;
|
|
DAC_CTL |= (ctl);
|
|
}
|
|
|
|
/*!
|
|
\brief set DAC concurrent mode data holding register value
|
|
\param[in] dac_align: data alignment
|
|
only one parameter can be selected which is shown as below:
|
|
\arg DAC_ALIGN_8B_R: data right 8b alignment
|
|
\arg DAC_ALIGN_12B_R: data right 12b alignment
|
|
\arg DAC_ALIGN_12B_L: data left 12b alignment
|
|
\param[in] data0: data to be loaded
|
|
\param[in] data1: data to be loaded
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1)
|
|
{
|
|
uint32_t data = 0U;
|
|
switch(dac_align){
|
|
/* data right 12b alignment */
|
|
case DAC_ALIGN_12B_R:
|
|
data = ((uint32_t)data1 << DH_12BIT_OFFSET) | data0;
|
|
DACC_R12DH = data;
|
|
break;
|
|
/* data left 12b alignment */
|
|
case DAC_ALIGN_12B_L:
|
|
data = ((uint32_t)data1 << DH_12BIT_OFFSET) | data0;
|
|
DACC_L12DH = data;
|
|
break;
|
|
/* data right 8b alignment */
|
|
case DAC_ALIGN_8B_R:
|
|
data = ((uint32_t)data1 << DH_8BIT_OFFSET) | data0;
|
|
DACC_R8DH = data;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|