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274 lines
7.8 KiB
274 lines
7.8 KiB
/*!
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\file gd32vf103_rtc.c
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\brief RTC driver
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\version 2019-06-05, V1.0.0, firmware for GD32VF103
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*/
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/*
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Copyright (c) 2019, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#include "gd32vf103_rtc.h"
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/* RTC register high / low bits mask */
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#define RTC_HIGH_BITS_MASK ((uint32_t)0x000F0000U) /* RTC high bits mask */
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#define RTC_LOW_BITS_MASK ((uint32_t)0x0000FFFFU) /* RTC low bits mask */
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/* RTC register high bits offset */
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#define RTC_HIGH_BITS_OFFSET ((uint32_t)16U)
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/*!
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\brief enter RTC configuration mode
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\param[in] none
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\param[out] none
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\retval none
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*/
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void rtc_configuration_mode_enter(void)
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{
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RTC_CTL |= RTC_CTL_CMF;
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}
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/*!
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\brief exit RTC configuration mode
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\param[in] none
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\param[out] none
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\retval none
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*/
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void rtc_configuration_mode_exit(void)
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{
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RTC_CTL &= ~RTC_CTL_CMF;
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}
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/*!
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\brief set RTC counter value
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\param[in] cnt: RTC counter value
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\param[out] none
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\retval none
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*/
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void rtc_counter_set(uint32_t cnt)
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{
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rtc_configuration_mode_enter();
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/* set the RTC counter high bits */
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RTC_CNTH = (cnt >> RTC_HIGH_BITS_OFFSET);
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/* set the RTC counter low bits */
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RTC_CNTL = (cnt & RTC_LOW_BITS_MASK);
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rtc_configuration_mode_exit();
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}
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/*!
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\brief set RTC prescaler value
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\param[in] psc: RTC prescaler value
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\param[out] none
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\retval none
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*/
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void rtc_prescaler_set(uint32_t psc)
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{
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rtc_configuration_mode_enter();
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/* set the RTC prescaler high bits */
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RTC_PSCH = ((psc & RTC_HIGH_BITS_MASK) >> RTC_HIGH_BITS_OFFSET);
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/* set the RTC prescaler low bits */
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RTC_PSCL = (psc & RTC_LOW_BITS_MASK);
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rtc_configuration_mode_exit();
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}
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/*!
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\brief wait RTC last write operation finished flag set
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\param[in] none
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\param[out] none
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\retval none
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*/
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void rtc_lwoff_wait(void)
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{
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/* loop until LWOFF flag is set */
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while(RESET == (RTC_CTL & RTC_CTL_LWOFF)){
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}
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}
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/*!
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\brief wait RTC registers synchronized flag set
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\param[in] none
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\param[out] none
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\retval none
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*/
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void rtc_register_sync_wait(void)
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{
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/* clear RSYNF flag */
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RTC_CTL &= ~RTC_CTL_RSYNF;
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/* loop until RSYNF flag is set */
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while(RESET == (RTC_CTL & RTC_CTL_RSYNF)){
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}
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}
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/*!
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\brief set RTC alarm value
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\param[in] alarm: RTC alarm value
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\param[out] none
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\retval none
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*/
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void rtc_alarm_config(uint32_t alarm)
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{
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rtc_configuration_mode_enter();
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/* set the alarm high bits */
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RTC_ALRMH = (alarm >> RTC_HIGH_BITS_OFFSET);
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/* set the alarm low bits */
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RTC_ALRML = (alarm & RTC_LOW_BITS_MASK);
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rtc_configuration_mode_exit();
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}
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/*!
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\brief get RTC counter value
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\param[in] none
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\param[out] none
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\retval RTC counter value
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*/
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uint32_t rtc_counter_get(void)
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{
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uint32_t temp = 0x0U;
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temp = RTC_CNTL;
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temp |= (RTC_CNTH << RTC_HIGH_BITS_OFFSET);
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return temp;
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}
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/*!
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\brief get RTC divider value
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\param[in] none
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\param[out] none
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\retval RTC divider value
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*/
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uint32_t rtc_divider_get(void)
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{
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uint32_t temp = 0x00U;
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temp = ((RTC_DIVH & RTC_DIVH_DIV) << RTC_HIGH_BITS_OFFSET);
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temp |= RTC_DIVL;
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return temp;
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}
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/*!
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\brief get RTC flag status
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\param[in] flag: specify which flag status to get
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only one parameter can be selected which is shown as below:
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\arg RTC_FLAG_SECOND: second interrupt flag
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\arg RTC_FLAG_ALARM: alarm interrupt flag
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\arg RTC_FLAG_OVERFLOW: overflow interrupt flag
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\arg RTC_FLAG_RSYN: registers synchronized flag
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\arg RTC_FLAG_LWOF: last write operation finished flag
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\param[out] none
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\retval SET or RESET
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*/
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FlagStatus rtc_flag_get(uint32_t flag)
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{
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if(RESET != (RTC_CTL & flag)){
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return SET;
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}else{
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return RESET;
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}
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}
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/*!
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\brief clear RTC flag status
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\param[in] flag: specify which flag status to clear
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one or more parameters can be selected which are shown as below:
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\arg RTC_FLAG_SECOND: second interrupt flag
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\arg RTC_FLAG_ALARM: alarm interrupt flag
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\arg RTC_FLAG_OVERFLOW: overflow interrupt flag
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\arg RTC_FLAG_RSYN: registers synchronized flag
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\param[out] none
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\retval none
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*/
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void rtc_flag_clear(uint32_t flag)
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{
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/* clear RTC flag */
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RTC_CTL &= ~flag;
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}
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/*!
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\brief get RTC interrupt flag status
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\param[in] flag: specify which flag status to get
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only one parameter can be selected which is shown as below:
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\arg RTC_INT_FLAG_SECOND: second interrupt flag
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\arg RTC_INT_FLAG_ALARM: alarm interrupt flag
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\arg RTC_INT_FLAG_OVERFLOW: overflow interrupt flag
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\param[out] none
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\retval SET or RESET
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*/
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FlagStatus rtc_interrupt_flag_get(uint32_t flag)
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{
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if(RESET != (RTC_CTL & flag)){
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return SET;
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}else{
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return RESET;
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}
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}
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/*!
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\brief clear RTC interrupt flag status
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\param[in] flag: specify which flag status to clear
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one or more parameters can be selected which are shown as below:
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\arg RTC_INT_FLAG_SECOND: second interrupt flag
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\arg RTC_INT_FLAG_ALARM: alarm interrupt flag
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\arg RTC_INT_FLAG_OVERFLOW: overflow interrupt flag
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\param[out] none
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\retval none
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*/
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void rtc_interrupt_flag_clear(uint32_t flag)
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{
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/* clear RTC interrupt flag */
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RTC_CTL &= ~flag;
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}
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/*!
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\brief enable RTC interrupt
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\param[in] interrupt: specify which interrupt to enbale
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one or more parameters can be selected which are shown as below:
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\arg RTC_INT_SECOND: second interrupt
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\arg RTC_INT_ALARM: alarm interrupt
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\arg RTC_INT_OVERFLOW: overflow interrupt
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\param[out] none
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\retval none
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*/
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void rtc_interrupt_enable(uint32_t interrupt)
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{
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RTC_INTEN |= interrupt;
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}
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/*!
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\brief disable RTC interrupt
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\param[in] interrupt: specify which interrupt to disbale
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one or more parameters can be selected which are shown as below:
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\arg RTC_INT_SECOND: second interrupt
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\arg RTC_INT_ALARM: alarm interrupt
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\arg RTC_INT_OVERFLOW: overflow interrupt
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\param[out] none
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\retval none
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*/
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void rtc_interrupt_disable(uint32_t interrupt)
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{
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RTC_INTEN &= ~interrupt;
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}
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