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259 lines
6.0 KiB
259 lines
6.0 KiB
// See LICENSE for license details.
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#include "riscv_encoding.h"
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.section .init
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.weak eclic_msip_handler
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.weak eclic_mtip_handler
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.weak eclic_bwei_handler
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.weak eclic_pmovi_handler
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.weak WWDGT_IRQHandler
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.weak LVD_IRQHandler
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.weak TAMPER_IRQHandler
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.weak RTC_IRQHandler
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.weak FMC_IRQHandler
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.weak RCU_IRQHandler
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.weak EXTI0_IRQHandler
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.weak EXTI1_IRQHandler
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.weak EXTI2_IRQHandler
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.weak EXTI3_IRQHandler
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.weak EXTI4_IRQHandler
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.weak DMA0_Channel0_IRQHandler
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.weak DMA0_Channel1_IRQHandler
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.weak DMA0_Channel2_IRQHandler
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.weak DMA0_Channel3_IRQHandler
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.weak DMA0_Channel4_IRQHandler
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.weak DMA0_Channel5_IRQHandler
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.weak DMA0_Channel6_IRQHandler
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.weak ADC0_1_IRQHandler
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.weak CAN0_TX_IRQHandler
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.weak CAN0_RX0_IRQHandler
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.weak CAN0_RX1_IRQHandler
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.weak CAN0_EWMC_IRQHandler
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.weak EXTI5_9_IRQHandler
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.weak TIMER0_BRK_IRQHandler
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.weak TIMER0_UP_IRQHandler
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.weak TIMER0_TRG_CMT_IRQHandler
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.weak TIMER0_Channel_IRQHandler
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.weak TIMER1_IRQHandler
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.weak TIMER2_IRQHandler
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.weak TIMER3_IRQHandler
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.weak I2C0_EV_IRQHandler
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.weak I2C0_ER_IRQHandler
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.weak I2C1_EV_IRQHandler
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.weak I2C1_ER_IRQHandler
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.weak SPI0_IRQHandler
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.weak SPI1_IRQHandler
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.weak USART0_IRQHandler
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.weak USART1_IRQHandler
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.weak USART2_IRQHandler
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.weak EXTI10_15_IRQHandler
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.weak RTC_Alarm_IRQHandler
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.weak USBFS_WKUP_IRQHandler
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.weak EXMC_IRQHandler
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.weak TIMER4_IRQHandler
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.weak SPI2_IRQHandler
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.weak UART3_IRQHandler
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.weak UART4_IRQHandler
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.weak TIMER5_IRQHandler
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.weak TIMER6_IRQHandler
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.weak DMA1_Channel0_IRQHandler
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.weak DMA1_Channel1_IRQHandler
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.weak DMA1_Channel2_IRQHandler
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.weak DMA1_Channel3_IRQHandler
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.weak DMA1_Channel4_IRQHandler
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.weak CAN1_TX_IRQHandler
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.weak CAN1_RX0_IRQHandler
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.weak CAN1_RX1_IRQHandler
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.weak CAN1_EWMC_IRQHandler
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.weak USBFS_IRQHandler
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vector_base:
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j _start
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.align 2
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.word 0
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.word 0
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.word eclic_msip_handler
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.word 0
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.word 0
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.word 0
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.word eclic_mtip_handler
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word eclic_bwei_handler
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.word eclic_pmovi_handler
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.word WWDGT_IRQHandler
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.word LVD_IRQHandler
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.word TAMPER_IRQHandler
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.word RTC_IRQHandler
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.word FMC_IRQHandler
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.word RCU_IRQHandler
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.word EXTI0_IRQHandler
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.word EXTI1_IRQHandler
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.word EXTI2_IRQHandler
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.word EXTI3_IRQHandler
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.word EXTI4_IRQHandler
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.word DMA0_Channel0_IRQHandler
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.word DMA0_Channel1_IRQHandler
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.word DMA0_Channel2_IRQHandler
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.word DMA0_Channel3_IRQHandler
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.word DMA0_Channel4_IRQHandler
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.word DMA0_Channel5_IRQHandler
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.word DMA0_Channel6_IRQHandler
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.word ADC0_1_IRQHandler
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.word CAN0_TX_IRQHandler
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.word CAN0_RX0_IRQHandler
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.word CAN0_RX1_IRQHandler
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.word CAN0_EWMC_IRQHandler
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.word EXTI5_9_IRQHandler
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.word TIMER0_BRK_IRQHandler
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.word TIMER0_UP_IRQHandler
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.word TIMER0_TRG_CMT_IRQHandler
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.word TIMER0_Channel_IRQHandler
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.word TIMER1_IRQHandler
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.word TIMER2_IRQHandler
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.word TIMER3_IRQHandler
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.word I2C0_EV_IRQHandler
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.word I2C0_ER_IRQHandler
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.word I2C1_EV_IRQHandler
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.word I2C1_ER_IRQHandler
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.word SPI0_IRQHandler
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.word SPI1_IRQHandler
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.word USART0_IRQHandler
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.word USART1_IRQHandler
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.word USART2_IRQHandler
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.word EXTI10_15_IRQHandler
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.word RTC_Alarm_IRQHandler
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.word USBFS_WKUP_IRQHandler
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word EXMC_IRQHandler
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.word 0
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.word TIMER4_IRQHandler
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.word SPI2_IRQHandler
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.word UART3_IRQHandler
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.word UART4_IRQHandler
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.word TIMER5_IRQHandler
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.word TIMER6_IRQHandler
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.word DMA1_Channel0_IRQHandler
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.word DMA1_Channel1_IRQHandler
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.word DMA1_Channel2_IRQHandler
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.word DMA1_Channel3_IRQHandler
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.word DMA1_Channel4_IRQHandler
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.word 0
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.word 0
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.word CAN1_TX_IRQHandler
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.word CAN1_RX0_IRQHandler
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.word CAN1_RX1_IRQHandler
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.word CAN1_EWMC_IRQHandler
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.word USBFS_IRQHandler
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.globl _start
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.type _start,@function
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_start:
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csrc CSR_MSTATUS, MSTATUS_MIE
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/* Jump to logical address first to ensure correct operation of RAM region */
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la a0, _start
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li a1, 1
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slli a1, a1, 29
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bleu a1, a0, _start0800
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srli a1, a1, 2
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bleu a1, a0, _start0800
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la a0, _start0800
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add a0, a0, a1
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jr a0
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_start0800:
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/* Set the the NMI base to share with mtvec by setting CSR_MMISC_CTL */
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li t0, 0x200
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csrs CSR_MMISC_CTL, t0
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/* Intial the mtvt*/
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la t0, vector_base
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csrw CSR_MTVT, t0
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/* Intial the mtvt2 and enable it*/
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la t0, irq_entry
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csrw CSR_MTVT2, t0
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csrs CSR_MTVT2, 0x1
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/* Intial the CSR MTVEC for the Trap ane NMI base addr*/
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la t0, trap_entry
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csrw CSR_MTVEC, t0
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#ifdef __riscv_flen
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/* Enable FPU */
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li t0, MSTATUS_FS
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csrs mstatus, t0
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csrw fcsr, x0
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#endif
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.option push
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.option norelax
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la gp, __global_pointer$
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.option pop
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la sp, _sp
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/* Load data section */
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la a0, _data_lma
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la a1, _data
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la a2, _edata
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bgeu a1, a2, 2f
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1:
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lw t0, (a0)
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sw t0, (a1)
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addi a0, a0, 4
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addi a1, a1, 4
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bltu a1, a2, 1b
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2:
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/* Clear bss section */
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la a0, __bss_start
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la a1, _end
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bgeu a0, a1, 2f
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1:
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sw zero, (a0)
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addi a0, a0, 4
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bltu a0, a1, 1b
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2:
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/*enable mcycle_minstret*/
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csrci CSR_MCOUNTINHIBIT, 0x5
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/* Call global constructors */
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// la a0, __libc_fini_array
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// call atexit
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// call __libc_init_array
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call _init
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/* argc = argv = 0 */
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li a0, 0
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li a1, 0
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call main
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// tail exit
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1:
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j 1b
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.global disable_mcycle_minstret
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disable_mcycle_minstret:
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csrsi CSR_MCOUNTINHIBIT, 0x5
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ret
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.global enable_mcycle_minstret
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enable_mcycle_minstret:
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csrci CSR_MCOUNTINHIBIT, 0x5
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ret
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