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129 lines
3.9 KiB
129 lines
3.9 KiB
/*!
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\file gd32vf103_eclic.c
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\brief ECLIC(Enhancement Core-Local Interrupt Controller) driver
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\version 2019-06-05, V1.0.1, firmware for GD32VF103
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*/
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/*
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Copyright (c) 2019, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#include "gd32vf103_eclic.h"
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#include "riscv_encoding.h"
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#define REG_DBGMCU2 ((uint32_t)0xE0042008)
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#define REG_DBGMCU2EN ((uint32_t)0xE004200C)
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/*!
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\brief enable the global interrupt
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\param[in] none
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\param[out] none
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\retval none
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*/
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void eclic_global_interrupt_enable(void)
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{
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/* set machine interrupt enable bit */
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set_csr(mstatus, MSTATUS_MIE);
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}
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/*!
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\brief disable the global interrupt
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\param[in] none
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\param[out] none
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\retval none
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*/
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void eclic_global_interrupt_disable(void)
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{
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/* clear machine interrupt enable bit */
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clear_csr(mstatus, MSTATUS_MIE);
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}
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/*!
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\brief set the priority group
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\param[in] prigroup: specify the priority group
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\arg ECLIC_PRIGROUP_LEVEL0_PRIO4
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\arg ECLIC_PRIGROUP_LEVEL1_PRIO3
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\arg ECLIC_PRIGROUP_LEVEL2_PRIO2
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\arg ECLIC_PRIGROUP_LEVEL3_PRIO1
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\arg ECLIC_PRIGROUP_LEVEL4_PRIO0
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\param[out] none
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\retval none
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*/
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void eclic_priority_group_set(uint32_t prigroup)
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{
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eclic_set_nlbits(prigroup);
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}
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/*!
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\brief enable the interrupt request
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\param[in] source: interrupt request, detailed in IRQn_Type
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\param[in] level: the level needed to set (maximum is 15, refer to the priority group)
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\param[in] priority: the priority needed to set (maximum is 15, refer to the priority group)
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\param[out] none
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\retval none
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*/
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void eclic_irq_enable(uint32_t source, uint8_t level, uint8_t priority)
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{
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eclic_enable_interrupt(source);
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eclic_set_irq_lvl_abs(source, level);
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eclic_set_irq_priority(source, priority);
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}
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/*!
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\brief disable the interrupt request
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\param[in] source: interrupt request, detailed in IRQn_Type
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\param[out] none
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\retval none
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*/
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void eclic_irq_disable(uint32_t source)
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{
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eclic_disable_interrupt(source);
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}
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/*!
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\brief reset system
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\param[in] none
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\param[out] none
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\retval none
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*/
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void eclic_system_reset(void)
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{
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REG32(REG_DBGMCU2EN) = 0x4b5a6978;
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REG32(REG_DBGMCU2) = 0x1;
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}
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/*!
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\brief send event(SEV)
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\param[in] none
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\param[out] none
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\retval none
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*/
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void eclic_send_event(void)
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{
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set_csr(0x812, 0x1);
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}
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