From e29ef848611e77fb83665fb8c6ec1edc64f1b06d Mon Sep 17 00:00:00 2001 From: Robert Fisk Date: Thu, 12 Nov 2015 10:39:31 +1300 Subject: [PATCH] Modify firmware for v1.0 hardware with STM32F401RC micro: - Processor-specific header - Startup file - Linker script - Project settings - Debugger config script - Debugger project settings - Board revision detection routines --- Downstream/.cproject | 42 +- Downstream/Downstream Debug.launch | 2 +- Downstream/Downstream Release.launch | 2 +- .../Device/ST/STM32F4xx/Include/stm32f401xc.h | 2795 +------------ .../Templates/gcc/startup_stm32f401xc.S | 133 +- Downstream/Inc/board_config.h | 7 + Downstream/OpenOCD_USG_v1.0.cfg | 4 + Downstream/Src/main.c | 62 +- .../gcc_arm_stm32f401.ld | 37 +- Downstream/olimex_stm32_h407.cfg | 8 - Upstream/.cproject | 36 +- Upstream/.settings/language.settings.xml | 2 +- .../Device/ST/STM32F4xx/Include/stm32f401xc.h | 3509 +---------------- .../Templates/gcc/startup_stm32f401xc.S | 155 +- Upstream/Inc/board_config.h | 13 +- Upstream/OpenOCD_USG_v1.0.cfg | 4 + Upstream/Src/main.c | 59 +- Upstream/Upstream Debug.launch | 2 +- Upstream/Upstream Release.launch | 2 +- .../gcc_arm_stm32f401.ld | 37 +- Upstream/olimex_stm32_h405.cfg | 8 - 21 files changed, 376 insertions(+), 6543 deletions(-) rename Upstream/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h => Downstream/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xc.h (59%) mode change 100755 => 100644 rename Upstream/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f405xx.S => Downstream/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f401xc.S (76%) create mode 100644 Downstream/OpenOCD_USG_v1.0.cfg rename Upstream/gcc_arm_stm32f405.ld => Downstream/gcc_arm_stm32f401.ld (72%) delete mode 100644 Downstream/olimex_stm32_h407.cfg rename Downstream/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h => Upstream/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xc.h (54%) rename Downstream/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f407xx.S => Upstream/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f401xc.S (74%) mode change 100644 => 100755 create mode 100644 Upstream/OpenOCD_USG_v1.0.cfg rename Downstream/gcc_arm_stm32f407.ld => Upstream/gcc_arm_stm32f401.ld (72%) delete mode 100644 Upstream/olimex_stm32_h405.cfg diff --git a/Downstream/.cproject b/Downstream/.cproject index 2f3dd93..2730d12 100644 --- a/Downstream/.cproject +++ b/Downstream/.cproject @@ -48,6 +48,9 @@ @@ -60,7 +63,7 @@ @@ -70,7 +73,7 @@ @@ -80,6 +83,9 @@ @@ -103,8 +109,8 @@ - @@ -164,6 +169,9 @@ @@ -176,7 +184,7 @@ @@ -185,7 +193,7 @@ - diff --git a/Downstream/Downstream Debug.launch b/Downstream/Downstream Debug.launch index e9b4910..0db9354 100644 --- a/Downstream/Downstream Debug.launch +++ b/Downstream/Downstream Debug.launch @@ -16,7 +16,7 @@ - + diff --git a/Downstream/Downstream Release.launch b/Downstream/Downstream Release.launch index 2eb546d..f38e233 100644 --- a/Downstream/Downstream Release.launch +++ b/Downstream/Downstream Release.launch @@ -16,7 +16,7 @@ - + diff --git a/Upstream/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h b/Downstream/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xc.h old mode 100755 new mode 100644 similarity index 59% rename from Upstream/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h rename to Downstream/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xc.h index c185d19..aa591d8 --- a/Upstream/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h +++ b/Downstream/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xc.h @@ -1,10 +1,10 @@ /** ****************************************************************************** - * @file stm32f405xx.h + * @file stm32f401xc.h * @author MCD Application Team - * @version V2.2.0 - * @date 15-December-2014 - * @brief CMSIS STM32F405xx Device Peripheral Access Layer Header File. + * @version V2.3.2 + * @date 26-June-2015 + * @brief CMSIS STM32F401xCxx Device Peripheral Access Layer Header File. * * This file contains: * - Data structures and the address mapping for all peripherals @@ -14,7 +14,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -45,12 +45,12 @@ * @{ */ -/** @addtogroup stm32f405xx +/** @addtogroup stm32f401xc * @{ */ -#ifndef __STM32F405xx_H -#define __STM32F405xx_H +#ifndef __STM32F401xC_H +#define __STM32F401xC_H #ifdef __cplusplus extern "C" { @@ -113,10 +113,6 @@ typedef enum DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ - CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ - CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ @@ -133,32 +129,18 @@ typedef enum SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ USART1_IRQn = 37, /*!< USART1 global Interrupt */ USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ - OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ - TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ - TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ - TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ - TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ - FSMC_IRQn = 48, /*!< FSMC global Interrupt */ SDIO_IRQn = 49, /*!< SDIO global Interrupt */ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ - TIM7_IRQn = 55, /*!< TIM7 global interrupt */ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ - CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ - CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ - CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ - CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ @@ -166,12 +148,8 @@ typedef enum USART6_IRQn = 71, /*!< USART6 global interrupt */ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ - OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ - OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ - OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ - OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ - HASH_RNG_IRQn = 80, /*!< Hash and RNG global interrupt */ - FPU_IRQn = 81 /*!< FPU global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + SPI4_IRQn = 84 /*!< SPI4 global Interrupt */ } IRQn_Type; /** @@ -222,71 +200,6 @@ typedef struct AND triple modes, Address offset: ADC1 base address + 0x308 */ } ADC_Common_TypeDef; - -/** - * @brief Controller Area Network TxMailBox - */ - -typedef struct -{ - __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ - __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ - __IO uint32_t TDLR; /*!< CAN mailbox data low register */ - __IO uint32_t TDHR; /*!< CAN mailbox data high register */ -} CAN_TxMailBox_TypeDef; - -/** - * @brief Controller Area Network FIFOMailBox - */ - -typedef struct -{ - __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ - __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ - __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ - __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ -} CAN_FIFOMailBox_TypeDef; - -/** - * @brief Controller Area Network FilterRegister - */ - -typedef struct -{ - __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ - __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ -} CAN_FilterRegister_TypeDef; - -/** - * @brief Controller Area Network - */ - -typedef struct -{ - __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ - __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ - __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ - __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ - __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ - __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ - __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ - __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ - uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ - CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ - CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ - uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ - __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ - __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ - uint32_t RESERVED2; /*!< Reserved, 0x208 */ - __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ - uint32_t RESERVED3; /*!< Reserved, 0x210 */ - __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ - uint32_t RESERVED4; /*!< Reserved, 0x218 */ - __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ - uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ - CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ -} CAN_TypeDef; - /** * @brief CRC calculation unit */ @@ -300,28 +213,6 @@ typedef struct __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ } CRC_TypeDef; -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ - __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ - __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ - __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ - __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ - __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ - __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ - __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ - __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ - __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ - __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ - __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ - __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ - __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ -} DAC_TypeDef; - /** * @brief Debug MCU */ @@ -387,61 +278,6 @@ typedef struct __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */ } FLASH_TypeDef; - -/** - * @brief Flexible Static Memory Controller - */ - -typedef struct -{ - __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ -} FSMC_Bank1_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank1E - */ - -typedef struct -{ - __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ -} FSMC_Bank1E_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank2 - */ - -typedef struct -{ - __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ - __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ - __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ - __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ - uint32_t RESERVED0; /*!< Reserved, 0x70 */ - __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ - uint32_t RESERVED1; /*!< Reserved, 0x78 */ - uint32_t RESERVED2; /*!< Reserved, 0x7C */ - __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */ - __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ - __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ - __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ - uint32_t RESERVED3; /*!< Reserved, 0x90 */ - __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ -} FSMC_Bank2_3_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank4 - */ - -typedef struct -{ - __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */ - __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */ - __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */ - __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */ - __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */ -} FSMC_Bank4_TypeDef; - - /** * @brief General Purpose I/O */ @@ -699,20 +535,6 @@ typedef struct __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ } WWDG_TypeDef; - - -/** - * @brief RNG - */ - -typedef struct -{ - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ -} RNG_TypeDef; - - /** * @brief __USB_OTG_Core_register @@ -843,18 +665,13 @@ USB_OTG_HostChannelTypeDef; #define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */ #define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */ #define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */ -#define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */ #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ #define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */ -#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ -#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */ #define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */ -#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */ -#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */ +#define SRAM2_BB_BASE ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region */ #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ -#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */ -#define FLASH_END ((uint32_t)0x080FFFFF) /*!< FLASH end address */ -#define CCMDATARAM_END ((uint32_t)0x1000FFFF) /*!< CCM data RAM end address */ +#define BKPSRAM_BB_BASE ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region */ +#define FLASH_END ((uint32_t)0x0803FFFF) /*!< FLASH end address */ /* Legacy defines */ #define SRAM_BASE SRAM1_BASE @@ -872,11 +689,6 @@ USB_OTG_HostChannelTypeDef; #define TIM3_BASE (APB1PERIPH_BASE + 0x0400) #define TIM4_BASE (APB1PERIPH_BASE + 0x0800) #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) -#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) -#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) -#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) -#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) -#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) #define RTC_BASE (APB1PERIPH_BASE + 0x2800) #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) #define IWDG_BASE (APB1PERIPH_BASE + 0x3000) @@ -885,28 +697,20 @@ USB_OTG_HostChannelTypeDef; #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000) #define USART2_BASE (APB1PERIPH_BASE + 0x4400) -#define USART3_BASE (APB1PERIPH_BASE + 0x4800) -#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) -#define UART5_BASE (APB1PERIPH_BASE + 0x5000) #define I2C1_BASE (APB1PERIPH_BASE + 0x5400) #define I2C2_BASE (APB1PERIPH_BASE + 0x5800) #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00) -#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) -#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) #define PWR_BASE (APB1PERIPH_BASE + 0x7000) -#define DAC_BASE (APB1PERIPH_BASE + 0x7400) /*!< APB2 peripherals */ #define TIM1_BASE (APB2PERIPH_BASE + 0x0000) -#define TIM8_BASE (APB2PERIPH_BASE + 0x0400) #define USART1_BASE (APB2PERIPH_BASE + 0x1000) #define USART6_BASE (APB2PERIPH_BASE + 0x1400) #define ADC1_BASE (APB2PERIPH_BASE + 0x2000) -#define ADC2_BASE (APB2PERIPH_BASE + 0x2100) -#define ADC3_BASE (APB2PERIPH_BASE + 0x2200) #define ADC_BASE (APB2PERIPH_BASE + 0x2300) #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00) #define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define SPI4_BASE (APB2PERIPH_BASE + 0x3400) #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800) #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00) #define TIM9_BASE (APB2PERIPH_BASE + 0x4000) @@ -919,10 +723,7 @@ USB_OTG_HostChannelTypeDef; #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800) #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00) #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000) -#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400) -#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800) #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00) -#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000) #define CRC_BASE (AHB1PERIPH_BASE + 0x3000) #define RCC_BASE (AHB1PERIPH_BASE + 0x3800) #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00) @@ -945,20 +746,10 @@ USB_OTG_HostChannelTypeDef; #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) -/*!< AHB2 peripherals */ -#define RNG_BASE (AHB2PERIPH_BASE + 0x60800) - -/*!< FSMC Bankx registers base address */ -#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) -#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) -#define FSMC_Bank2_3_R_BASE (FSMC_R_BASE + 0x0060) -#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) - /* Debug MCU registers base address */ #define DBGMCU_BASE ((uint32_t )0xE0042000) /*!< USB registers base address */ -#define USB_OTG_HS_PERIPH_BASE ((uint32_t )0x40040000) #define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000) #define USB_OTG_GLOBAL_BASE ((uint32_t )0x000) @@ -985,11 +776,6 @@ USB_OTG_HostChannelTypeDef; #define TIM3 ((TIM_TypeDef *) TIM3_BASE) #define TIM4 ((TIM_TypeDef *) TIM4_BASE) #define TIM5 ((TIM_TypeDef *) TIM5_BASE) -#define TIM6 ((TIM_TypeDef *) TIM6_BASE) -#define TIM7 ((TIM_TypeDef *) TIM7_BASE) -#define TIM12 ((TIM_TypeDef *) TIM12_BASE) -#define TIM13 ((TIM_TypeDef *) TIM13_BASE) -#define TIM14 ((TIM_TypeDef *) TIM14_BASE) #define RTC ((RTC_TypeDef *) RTC_BASE) #define WWDG ((WWDG_TypeDef *) WWDG_BASE) #define IWDG ((IWDG_TypeDef *) IWDG_BASE) @@ -998,26 +784,18 @@ USB_OTG_HostChannelTypeDef; #define SPI3 ((SPI_TypeDef *) SPI3_BASE) #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE) #define USART2 ((USART_TypeDef *) USART2_BASE) -#define USART3 ((USART_TypeDef *) USART3_BASE) -#define UART4 ((USART_TypeDef *) UART4_BASE) -#define UART5 ((USART_TypeDef *) UART5_BASE) #define I2C1 ((I2C_TypeDef *) I2C1_BASE) #define I2C2 ((I2C_TypeDef *) I2C2_BASE) #define I2C3 ((I2C_TypeDef *) I2C3_BASE) -#define CAN1 ((CAN_TypeDef *) CAN1_BASE) -#define CAN2 ((CAN_TypeDef *) CAN2_BASE) #define PWR ((PWR_TypeDef *) PWR_BASE) -#define DAC ((DAC_TypeDef *) DAC_BASE) #define TIM1 ((TIM_TypeDef *) TIM1_BASE) -#define TIM8 ((TIM_TypeDef *) TIM8_BASE) #define USART1 ((USART_TypeDef *) USART1_BASE) #define USART6 ((USART_TypeDef *) USART6_BASE) #define ADC ((ADC_Common_TypeDef *) ADC_BASE) #define ADC1 ((ADC_TypeDef *) ADC1_BASE) -#define ADC2 ((ADC_TypeDef *) ADC2_BASE) -#define ADC3 ((ADC_TypeDef *) ADC3_BASE) #define SDIO ((SDIO_TypeDef *) SDIO_BASE) -#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define SPI4 ((SPI_TypeDef *) SPI4_BASE) #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) #define EXTI ((EXTI_TypeDef *) EXTI_BASE) #define TIM9 ((TIM_TypeDef *) TIM9_BASE) @@ -1028,10 +806,7 @@ USB_OTG_HostChannelTypeDef; #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) -#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) -#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) -#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) #define CRC ((CRC_TypeDef *) CRC_BASE) #define RCC ((RCC_TypeDef *) RCC_BASE) #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) @@ -1052,17 +827,11 @@ USB_OTG_HostChannelTypeDef; #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) -#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) -#define RNG ((RNG_TypeDef *) RNG_BASE) -#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) -#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) -#define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE) -#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) +#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) -#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE) /** * @} @@ -1441,1327 +1210,6 @@ USB_OTG_HostChannelTypeDef; #define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */ #define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */ -/******************************************************************************/ -/* */ -/* Controller Area Network */ -/* */ -/******************************************************************************/ -/*!BSRR = (UPSTREAM_TX_REQUEST_PIN << BSRR_SHIFT_HIGH)) #define DBGMCU_IDCODE_DEV_ID_405_407_415_417 0x413 +#define DBGMCU_IDCODE_DEV_ID_401xB_xC 0x423 + +#define BOARD_REV_PIN_MASK 0x07 +#define BOARD_ID_PIN_MASK 0x08 +#define BOARD_REV_ID_PORT GPIOC + +#define BOARD_REV_1_0_BETA 0 #endif /* INC_BOARD_CONFIG_H_ */ diff --git a/Downstream/OpenOCD_USG_v1.0.cfg b/Downstream/OpenOCD_USG_v1.0.cfg new file mode 100644 index 0000000..41e0411 --- /dev/null +++ b/Downstream/OpenOCD_USG_v1.0.cfg @@ -0,0 +1,4 @@ +# Default work area for the STM32F4x is 64K. We'll just leave it at that. +# set WORKAREASIZE 0x10000 + +source [find target/stm32f4x.cfg] diff --git a/Downstream/Src/main.c b/Downstream/Src/main.c index 3509f53..40263ae 100644 --- a/Downstream/Src/main.c +++ b/Downstream/Src/main.c @@ -83,26 +83,27 @@ void CheckFirmwareMatchesHardware(void) GPIO_InitTypeDef GPIO_InitStruct; - if ((*(uint32_t*)DBGMCU_BASE & DBGMCU_IDCODE_DEV_ID) == DBGMCU_IDCODE_DEV_ID_405_407_415_417) - { - //The H407 board has a STAT LED on PC13. If there is no pullup on this pin, - //then we are probably running on another board. - __HAL_RCC_GPIOC_CLK_ENABLE(); - GPIO_InitStruct.Pin = FAULT_LED_PIN; - GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = GPIO_PULLDOWN; - GPIO_InitStruct.Speed = GPIO_SPEED_LOW; - GPIO_InitStruct.Alternate = 0; - HAL_GPIO_Init(FAULT_LED_PORT, &GPIO_InitStruct); - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(FAULT_LED_PORT, &GPIO_InitStruct); - - if (FAULT_LED_PORT->IDR & FAULT_LED_PIN) - { - //Pin pulls up, so this is an H407 board :) - return; - } - } + if ((*(uint32_t*)DBGMCU_BASE & DBGMCU_IDCODE_DEV_ID) == DBGMCU_IDCODE_DEV_ID_401xB_xC) + { + //Read in board revision and ID on port C + __HAL_RCC_GPIOC_CLK_ENABLE(); + GPIO_InitStruct.Pin = BOARD_REV_PIN_MASK | BOARD_ID_PIN_MASK; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_LOW; + GPIO_InitStruct.Alternate = 0; + HAL_GPIO_Init(BOARD_REV_ID_PORT, &GPIO_InitStruct); + + //Correct board revision? + if ((BOARD_REV_ID_PORT->IDR & BOARD_REV_PIN_MASK) == BOARD_REV_1_0_BETA) + { + //Correct board ID: downstream? + if (!(BOARD_REV_ID_PORT->IDR & BOARD_ID_PIN_MASK)) + { + return; + } + } + } //This is not the hardware we expected, so turn on our fault LED(s) and die in a heap. GPIO_InitStruct.Pin = FAULT_LED_PIN | H405_FAULT_LED_PIN; @@ -131,7 +132,7 @@ void SystemClock_Config(void) RCC_OscInitStruct.HSEState = RCC_HSE_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = 12; + RCC_OscInitStruct.PLL.PLLM = 8; RCC_OscInitStruct.PLL.PLLN = 336; RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; RCC_OscInitStruct.PLL.PLLQ = 7; @@ -157,15 +158,14 @@ void GPIO_Init(void) { GPIO_InitTypeDef GPIO_InitStruct; - /* GPIO Ports Clock Enable */ - //__GPIOH_CLK_ENABLE(); - __HAL_RCC_GPIOA_CLK_ENABLE(); - __HAL_RCC_GPIOB_CLK_ENABLE(); - __HAL_RCC_GPIOC_CLK_ENABLE(); - __HAL_RCC_GPIOD_CLK_ENABLE(); - __HAL_RCC_GPIOE_CLK_ENABLE(); - __HAL_RCC_GPIOF_CLK_ENABLE(); - __HAL_RCC_GPIOG_CLK_ENABLE(); + + /* GPIO Ports Clock Enable */ + //__GPIOH_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + __HAL_RCC_GPIOE_CLK_ENABLE(); //Bulk initialise all ports as inputs with pullups active, //excluding JTAG pins which must remain as AF0! @@ -181,8 +181,6 @@ void GPIO_Init(void) HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); - HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); - HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); //USB VBUS pins are analog input GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; diff --git a/Upstream/gcc_arm_stm32f405.ld b/Downstream/gcc_arm_stm32f401.ld similarity index 72% rename from Upstream/gcc_arm_stm32f405.ld rename to Downstream/gcc_arm_stm32f401.ld index 8e01b1e..704655f 100755 --- a/Upstream/gcc_arm_stm32f405.ld +++ b/Downstream/gcc_arm_stm32f401.ld @@ -1,10 +1,9 @@ /* Linker script to configure memory regions. */ MEMORY { - FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K - SRAM1 (xrw) : ORIGIN = 0x20000000, LENGTH = 112K - SRAM2 (xrw) : ORIGIN = 0x2001C000, LENGTH = 16K - CCMRAM (rw) : ORIGIN = 0x10000000, LENGTH = 64K + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256K + SRAM1 (xrw) : ORIGIN = 0x20000000, LENGTH = 64K + } /* Library configurations */ @@ -112,33 +111,5 @@ SECTIONS /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") - - - /* TODO: Place DMA buffers here. - * SRAM1 and SRAM2 can be accessed simultaneously. - * Startup file does not initialise this area. */ - .sram2 : - { - . = ALIGN(4); - *(.sram2) - *(.sram2*) - . = ALIGN(4); - } >SRAM2 - - - _siccmram = LOADADDR(.ccmram); - - /* CCM-RAM section - * Use for stack and heap if SRAM1 & SRAM2 is full. - */ - .ccmram : - { - . = ALIGN(4); - _sccmram = .; - *(.ccmram) - *(.ccmram*) - - . = ALIGN(4); - _eccmram = .; - } >CCMRAM /* AT> FLASH */ + } diff --git a/Downstream/olimex_stm32_h407.cfg b/Downstream/olimex_stm32_h407.cfg deleted file mode 100644 index 2f69524..0000000 --- a/Downstream/olimex_stm32_h407.cfg +++ /dev/null @@ -1,8 +0,0 @@ -# Olimex STM32-H407 eval board -# http://olimex.com/dev/stm32-h407.html - -# Default work area for the STM32F4x is 64K. We'll just leave it at that. -# Work-area size (RAM size) = 128kB for STM32F405RG device -# set WORKAREASIZE 0x20000 - -source [find target/stm32f4x.cfg] diff --git a/Upstream/.cproject b/Upstream/.cproject index 0983f0b..fc2b121 100755 --- a/Upstream/.cproject +++ b/Upstream/.cproject @@ -24,7 +24,7 @@ @@ -72,7 +72,7 @@ @@ -81,7 +81,7 @@ @@ -198,7 +197,7 @@ @@ -240,8 +239,8 @@ - diff --git a/Upstream/.settings/language.settings.xml b/Upstream/.settings/language.settings.xml index c8d28e9..f7a9c79 100755 --- a/Upstream/.settings/language.settings.xml +++ b/Upstream/.settings/language.settings.xml @@ -5,7 +5,7 @@ - + diff --git a/Downstream/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h b/Upstream/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xc.h similarity index 54% rename from Downstream/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h rename to Upstream/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xc.h index f5fe69f..aa591d8 100644 --- a/Downstream/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h +++ b/Upstream/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xc.h @@ -1,10 +1,10 @@ /** ****************************************************************************** - * @file stm32f407xx.h + * @file stm32f401xc.h * @author MCD Application Team * @version V2.3.2 * @date 26-June-2015 - * @brief CMSIS STM32F407xx Device Peripheral Access Layer Header File. + * @brief CMSIS STM32F401xCxx Device Peripheral Access Layer Header File. * * This file contains: * - Data structures and the address mapping for all peripherals @@ -45,12 +45,12 @@ * @{ */ -/** @addtogroup stm32f407xx +/** @addtogroup stm32f401xc * @{ */ -#ifndef __STM32F407xx_H -#define __STM32F407xx_H +#ifndef __STM32F401xC_H +#define __STM32F401xC_H #ifdef __cplusplus extern "C" { @@ -113,10 +113,6 @@ typedef enum DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ - CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ - CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ @@ -133,34 +129,18 @@ typedef enum SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ USART1_IRQn = 37, /*!< USART1 global Interrupt */ USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ - OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ - TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ - TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ - TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ - TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ - FSMC_IRQn = 48, /*!< FSMC global Interrupt */ SDIO_IRQn = 49, /*!< SDIO global Interrupt */ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ - TIM7_IRQn = 55, /*!< TIM7 global interrupt */ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ - ETH_IRQn = 61, /*!< Ethernet global Interrupt */ - ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ - CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ - CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ - CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ - CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ @@ -168,13 +148,8 @@ typedef enum USART6_IRQn = 71, /*!< USART6 global interrupt */ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ - OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ - OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ - OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ - OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ - DCMI_IRQn = 78, /*!< DCMI global interrupt */ - HASH_RNG_IRQn = 80, /*!< Hash and RNG global interrupt */ - FPU_IRQn = 81 /*!< FPU global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + SPI4_IRQn = 84 /*!< SPI4 global Interrupt */ } IRQn_Type; /** @@ -225,71 +200,6 @@ typedef struct AND triple modes, Address offset: ADC1 base address + 0x308 */ } ADC_Common_TypeDef; - -/** - * @brief Controller Area Network TxMailBox - */ - -typedef struct -{ - __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ - __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ - __IO uint32_t TDLR; /*!< CAN mailbox data low register */ - __IO uint32_t TDHR; /*!< CAN mailbox data high register */ -} CAN_TxMailBox_TypeDef; - -/** - * @brief Controller Area Network FIFOMailBox - */ - -typedef struct -{ - __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ - __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ - __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ - __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ -} CAN_FIFOMailBox_TypeDef; - -/** - * @brief Controller Area Network FilterRegister - */ - -typedef struct -{ - __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ - __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ -} CAN_FilterRegister_TypeDef; - -/** - * @brief Controller Area Network - */ - -typedef struct -{ - __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ - __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ - __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ - __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ - __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ - __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ - __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ - __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ - uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ - CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ - CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ - uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ - __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ - __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ - uint32_t RESERVED2; /*!< Reserved, 0x208 */ - __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ - uint32_t RESERVED3; /*!< Reserved, 0x210 */ - __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ - uint32_t RESERVED4; /*!< Reserved, 0x218 */ - __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ - uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ - CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ -} CAN_TypeDef; - /** * @brief CRC calculation unit */ @@ -303,28 +213,6 @@ typedef struct __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ } CRC_TypeDef; -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ - __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ - __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ - __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ - __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ - __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ - __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ - __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ - __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ - __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ - __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ - __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ - __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ - __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ -} DAC_TypeDef; - /** * @brief Debug MCU */ @@ -337,24 +225,6 @@ typedef struct __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ }DBGMCU_TypeDef; -/** - * @brief DCMI - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ - __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ - __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ - __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ - __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ - __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ - __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ - __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ - __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ - __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ - __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ -} DCMI_TypeDef; /** * @brief DMA Controller @@ -379,80 +249,6 @@ typedef struct } DMA_TypeDef; -/** - * @brief Ethernet MAC - */ - -typedef struct -{ - __IO uint32_t MACCR; - __IO uint32_t MACFFR; - __IO uint32_t MACHTHR; - __IO uint32_t MACHTLR; - __IO uint32_t MACMIIAR; - __IO uint32_t MACMIIDR; - __IO uint32_t MACFCR; - __IO uint32_t MACVLANTR; /* 8 */ - uint32_t RESERVED0[2]; - __IO uint32_t MACRWUFFR; /* 11 */ - __IO uint32_t MACPMTCSR; - uint32_t RESERVED1[2]; - __IO uint32_t MACSR; /* 15 */ - __IO uint32_t MACIMR; - __IO uint32_t MACA0HR; - __IO uint32_t MACA0LR; - __IO uint32_t MACA1HR; - __IO uint32_t MACA1LR; - __IO uint32_t MACA2HR; - __IO uint32_t MACA2LR; - __IO uint32_t MACA3HR; - __IO uint32_t MACA3LR; /* 24 */ - uint32_t RESERVED2[40]; - __IO uint32_t MMCCR; /* 65 */ - __IO uint32_t MMCRIR; - __IO uint32_t MMCTIR; - __IO uint32_t MMCRIMR; - __IO uint32_t MMCTIMR; /* 69 */ - uint32_t RESERVED3[14]; - __IO uint32_t MMCTGFSCCR; /* 84 */ - __IO uint32_t MMCTGFMSCCR; - uint32_t RESERVED4[5]; - __IO uint32_t MMCTGFCR; - uint32_t RESERVED5[10]; - __IO uint32_t MMCRFCECR; - __IO uint32_t MMCRFAECR; - uint32_t RESERVED6[10]; - __IO uint32_t MMCRGUFCR; - uint32_t RESERVED7[334]; - __IO uint32_t PTPTSCR; - __IO uint32_t PTPSSIR; - __IO uint32_t PTPTSHR; - __IO uint32_t PTPTSLR; - __IO uint32_t PTPTSHUR; - __IO uint32_t PTPTSLUR; - __IO uint32_t PTPTSAR; - __IO uint32_t PTPTTHR; - __IO uint32_t PTPTTLR; - __IO uint32_t RESERVED8; - __IO uint32_t PTPTSSR; - uint32_t RESERVED9[565]; - __IO uint32_t DMABMR; - __IO uint32_t DMATPDR; - __IO uint32_t DMARPDR; - __IO uint32_t DMARDLAR; - __IO uint32_t DMATDLAR; - __IO uint32_t DMASR; - __IO uint32_t DMAOMR; - __IO uint32_t DMAIER; - __IO uint32_t DMAMFBOCR; - __IO uint32_t DMARSWTR; - uint32_t RESERVED10[8]; - __IO uint32_t DMACHTDR; - __IO uint32_t DMACHRDR; - __IO uint32_t DMACHTBAR; - __IO uint32_t DMACHRBAR; -} ETH_TypeDef; - /** * @brief External Interrupt/Event Controller */ @@ -482,61 +278,6 @@ typedef struct __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */ } FLASH_TypeDef; - -/** - * @brief Flexible Static Memory Controller - */ - -typedef struct -{ - __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ -} FSMC_Bank1_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank1E - */ - -typedef struct -{ - __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ -} FSMC_Bank1E_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank2 - */ - -typedef struct -{ - __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ - __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ - __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ - __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ - uint32_t RESERVED0; /*!< Reserved, 0x70 */ - __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ - uint32_t RESERVED1; /*!< Reserved, 0x78 */ - uint32_t RESERVED2; /*!< Reserved, 0x7C */ - __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */ - __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ - __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ - __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ - uint32_t RESERVED3; /*!< Reserved, 0x90 */ - __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ -} FSMC_Bank2_3_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank4 - */ - -typedef struct -{ - __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */ - __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */ - __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */ - __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */ - __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */ -} FSMC_Bank4_TypeDef; - - /** * @brief General Purpose I/O */ @@ -794,43 +535,30 @@ typedef struct __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ } WWDG_TypeDef; - -/** - * @brief RNG - */ - -typedef struct -{ - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ -} RNG_TypeDef; - - /** * @brief __USB_OTG_Core_register */ typedef struct { - __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h*/ - __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h*/ - __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h*/ - __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch*/ - __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h*/ - __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h*/ - __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h*/ - __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch*/ - __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h*/ - __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/ - __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/ - __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch*/ - uint32_t Reserved30[2]; /* Reserved 030h*/ - __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/ - __IO uint32_t CID; /* User ID Register 03Ch*/ - uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/ - __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/ - __IO uint32_t DIEPTXF[0x0F];/* dev Periodic Transmit FIFO */ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register Address offset : 0x00 */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register Address offset : 0x04 */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register Address offset : 0x08 */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register Address offset : 0x0C */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register Address offset : 0x10 */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register Address offset : 0x14 */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register Address offset : 0x18 */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register Address offset : 0x1C */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register Address offset : 0x20 */ + __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register Address offset : 0x24 */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register Address offset : 0x28 */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg Address offset : 0x2C */ + uint32_t Reserved30[2]; /* Reserved Address offset : 0x30 */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register Address offset : 0x38 */ + __IO uint32_t CID; /*!< User ID Register Address offset : 0x3C */ + uint32_t Reserved40[48]; /*!< Reserved Address offset : 0x40-0xFF */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg Address offset : 0x100 */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */ } USB_OTG_GlobalTypeDef; @@ -841,26 +569,26 @@ USB_OTG_GlobalTypeDef; */ typedef struct { - __IO uint32_t DCFG; /* dev Configuration Register 800h*/ - __IO uint32_t DCTL; /* dev Control Register 804h*/ - __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/ - uint32_t Reserved0C; /* Reserved 80Ch*/ - __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/ - __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/ - __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/ - __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/ - uint32_t Reserved20; /* Reserved 820h*/ - uint32_t Reserved9; /* Reserved 824h*/ - __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/ - __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/ - __IO uint32_t DTHRCTL; /* dev thr 830h*/ - __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/ - __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/ - __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/ - uint32_t Reserved40; /* dedicated EP mask 840h*/ - __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/ - uint32_t Reserved44[15]; /* Reserved 844-87Ch*/ - __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/ + __IO uint32_t DCFG; /*!< dev Configuration Register Address offset : 0x800 */ + __IO uint32_t DCTL; /*!< dev Control Register Address offset : 0x804 */ + __IO uint32_t DSTS; /*!< dev Status Register (RO) Address offset : 0x808 */ + uint32_t Reserved0C; /*!< Reserved Address offset : 0x80C */ + __IO uint32_t DIEPMSK; /* !< dev IN Endpoint Mask Address offset : 0x810 */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask Address offset : 0x814 */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg Address offset : 0x818 */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask Address offset : 0x81C */ + uint32_t Reserved20; /*!< Reserved Address offset : 0x820 */ + uint32_t Reserved9; /*!< Reserved Address offset : 0x824 */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register Address offset : 0x828 */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register Address offset : 0x82C */ + __IO uint32_t DTHRCTL; /*!< dev thr Address offset : 0x830 */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk Address offset : 0x834 */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt Address offset : 0x838 */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk Address offset : 0x83C */ + uint32_t Reserved40; /*!< dedicated EP mask Address offset : 0x840 */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask Address offset : 0x844 */ + uint32_t Reserved44[15]; /*!< Reserved Address offset : 0x844-0x87C */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk Address offset : 0x884 */ } USB_OTG_DeviceTypeDef; @@ -870,14 +598,14 @@ USB_OTG_DeviceTypeDef; */ typedef struct { - __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/ - uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/ - __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/ - uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/ - __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/ - __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/ - __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/ - uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/ + __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ + uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ } USB_OTG_INEndpointTypeDef; @@ -904,12 +632,12 @@ USB_OTG_OUTEndpointTypeDef; typedef struct { __IO uint32_t HCFG; /* Host Configuration Register 400h*/ - __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/ - __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/ - uint32_t Reserved40C; /* Reserved 40Ch*/ - __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/ - __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/ - __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/ + __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/ + __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/ + uint32_t Reserved40C; /* Reserved 40Ch*/ + __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/ + __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/ + __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/ } USB_OTG_HostTypeDef; @@ -939,13 +667,11 @@ USB_OTG_HostChannelTypeDef; #define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */ #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ #define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */ -#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ #define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */ #define SRAM2_BB_BASE ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region */ #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ #define BKPSRAM_BB_BASE ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region */ -#define FLASH_END ((uint32_t)0x080FFFFF) /*!< FLASH end address */ -#define CCMDATARAM_END ((uint32_t)0x1000FFFF) /*!< CCM data RAM end address */ +#define FLASH_END ((uint32_t)0x0803FFFF) /*!< FLASH end address */ /* Legacy defines */ #define SRAM_BASE SRAM1_BASE @@ -963,11 +689,6 @@ USB_OTG_HostChannelTypeDef; #define TIM3_BASE (APB1PERIPH_BASE + 0x0400) #define TIM4_BASE (APB1PERIPH_BASE + 0x0800) #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) -#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) -#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) -#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) -#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) -#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) #define RTC_BASE (APB1PERIPH_BASE + 0x2800) #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) #define IWDG_BASE (APB1PERIPH_BASE + 0x3000) @@ -976,28 +697,20 @@ USB_OTG_HostChannelTypeDef; #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000) #define USART2_BASE (APB1PERIPH_BASE + 0x4400) -#define USART3_BASE (APB1PERIPH_BASE + 0x4800) -#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) -#define UART5_BASE (APB1PERIPH_BASE + 0x5000) #define I2C1_BASE (APB1PERIPH_BASE + 0x5400) #define I2C2_BASE (APB1PERIPH_BASE + 0x5800) #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00) -#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) -#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) #define PWR_BASE (APB1PERIPH_BASE + 0x7000) -#define DAC_BASE (APB1PERIPH_BASE + 0x7400) /*!< APB2 peripherals */ #define TIM1_BASE (APB2PERIPH_BASE + 0x0000) -#define TIM8_BASE (APB2PERIPH_BASE + 0x0400) #define USART1_BASE (APB2PERIPH_BASE + 0x1000) #define USART6_BASE (APB2PERIPH_BASE + 0x1400) #define ADC1_BASE (APB2PERIPH_BASE + 0x2000) -#define ADC2_BASE (APB2PERIPH_BASE + 0x2100) -#define ADC3_BASE (APB2PERIPH_BASE + 0x2200) #define ADC_BASE (APB2PERIPH_BASE + 0x2300) #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00) #define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define SPI4_BASE (APB2PERIPH_BASE + 0x3400) #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800) #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00) #define TIM9_BASE (APB2PERIPH_BASE + 0x4000) @@ -1010,10 +723,7 @@ USB_OTG_HostChannelTypeDef; #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800) #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00) #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000) -#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400) -#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800) #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00) -#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000) #define CRC_BASE (AHB1PERIPH_BASE + 0x3000) #define RCC_BASE (AHB1PERIPH_BASE + 0x3800) #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00) @@ -1035,27 +745,11 @@ USB_OTG_HostChannelTypeDef; #define DMA2_Stream5_BASE (DMA2_BASE + 0x088) #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) -#define ETH_BASE (AHB1PERIPH_BASE + 0x8000) -#define ETH_MAC_BASE (ETH_BASE) -#define ETH_MMC_BASE (ETH_BASE + 0x0100) -#define ETH_PTP_BASE (ETH_BASE + 0x0700) -#define ETH_DMA_BASE (ETH_BASE + 0x1000) - -/*!< AHB2 peripherals */ -#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000) -#define RNG_BASE (AHB2PERIPH_BASE + 0x60800) - -/*!< FSMC Bankx registers base address */ -#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) -#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) -#define FSMC_Bank2_3_R_BASE (FSMC_R_BASE + 0x0060) -#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) /* Debug MCU registers base address */ #define DBGMCU_BASE ((uint32_t )0xE0042000) /*!< USB registers base address */ -#define USB_OTG_HS_PERIPH_BASE ((uint32_t )0x40040000) #define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000) #define USB_OTG_GLOBAL_BASE ((uint32_t )0x000) @@ -1082,11 +776,6 @@ USB_OTG_HostChannelTypeDef; #define TIM3 ((TIM_TypeDef *) TIM3_BASE) #define TIM4 ((TIM_TypeDef *) TIM4_BASE) #define TIM5 ((TIM_TypeDef *) TIM5_BASE) -#define TIM6 ((TIM_TypeDef *) TIM6_BASE) -#define TIM7 ((TIM_TypeDef *) TIM7_BASE) -#define TIM12 ((TIM_TypeDef *) TIM12_BASE) -#define TIM13 ((TIM_TypeDef *) TIM13_BASE) -#define TIM14 ((TIM_TypeDef *) TIM14_BASE) #define RTC ((RTC_TypeDef *) RTC_BASE) #define WWDG ((WWDG_TypeDef *) WWDG_BASE) #define IWDG ((IWDG_TypeDef *) IWDG_BASE) @@ -1095,26 +784,18 @@ USB_OTG_HostChannelTypeDef; #define SPI3 ((SPI_TypeDef *) SPI3_BASE) #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE) #define USART2 ((USART_TypeDef *) USART2_BASE) -#define USART3 ((USART_TypeDef *) USART3_BASE) -#define UART4 ((USART_TypeDef *) UART4_BASE) -#define UART5 ((USART_TypeDef *) UART5_BASE) #define I2C1 ((I2C_TypeDef *) I2C1_BASE) #define I2C2 ((I2C_TypeDef *) I2C2_BASE) #define I2C3 ((I2C_TypeDef *) I2C3_BASE) -#define CAN1 ((CAN_TypeDef *) CAN1_BASE) -#define CAN2 ((CAN_TypeDef *) CAN2_BASE) #define PWR ((PWR_TypeDef *) PWR_BASE) -#define DAC ((DAC_TypeDef *) DAC_BASE) #define TIM1 ((TIM_TypeDef *) TIM1_BASE) -#define TIM8 ((TIM_TypeDef *) TIM8_BASE) #define USART1 ((USART_TypeDef *) USART1_BASE) #define USART6 ((USART_TypeDef *) USART6_BASE) #define ADC ((ADC_Common_TypeDef *) ADC_BASE) #define ADC1 ((ADC_TypeDef *) ADC1_BASE) -#define ADC2 ((ADC_TypeDef *) ADC2_BASE) -#define ADC3 ((ADC_TypeDef *) ADC3_BASE) #define SDIO ((SDIO_TypeDef *) SDIO_BASE) -#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define SPI4 ((SPI_TypeDef *) SPI4_BASE) #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) #define EXTI ((EXTI_TypeDef *) EXTI_BASE) #define TIM9 ((TIM_TypeDef *) TIM9_BASE) @@ -1125,10 +806,7 @@ USB_OTG_HostChannelTypeDef; #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) -#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) -#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) -#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) #define CRC ((CRC_TypeDef *) CRC_BASE) #define RCC ((RCC_TypeDef *) RCC_BASE) #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) @@ -1150,18 +828,10 @@ USB_OTG_HostChannelTypeDef; #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) -#define ETH ((ETH_TypeDef *) ETH_BASE) -#define DCMI ((DCMI_TypeDef *) DCMI_BASE) -#define RNG ((RNG_TypeDef *) RNG_BASE) -#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) -#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) -#define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE) -#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) -#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE) /** * @} @@ -1540,1327 +1210,6 @@ USB_OTG_HostChannelTypeDef; #define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */ #define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */ -/******************************************************************************/ -/* */ -/* Controller Area Network */ -/* */ -/******************************************************************************/ -/*!BSRR = (FAULT_LED_PIN << BSRR_SHIFT_LOW)) //Fault LED is active-low #define FAULT_LED_OFF (FAULT_LED_PORT->BSRR = (FAULT_LED_PIN << BSRR_SHIFT_HIGH)) -#define OTHER_BOARDS_FAULT_LED_PIN GPIO_PIN_13 //Fault LED on Olimex H407 board, and USG v1.0 -#define OTHER_BOARDS_FAULT_LED_ON (FAULT_LED_PORT->BSRR = (OTHER_BOARDS_FAULT_LED_PIN << BSRR_SHIFT_LOW)) +#define H405_FAULT_LED_PIN GPIO_PIN_12 //Fault LED on Olimex H405 board +#define H405_FAULT_LED_ON (FAULT_LED_PORT->BSRR = (H405_FAULT_LED_PIN << BSRR_SHIFT_LOW)) #define INT_ACTIVE_PIN GPIO_PIN_5 //Temporary indicator of SPI (or whatever) activity #define INT_ACTIVE_PORT GPIOB @@ -48,6 +48,13 @@ #define DOWNSTREAM_TX_OK_ACTIVE (!(DOWNSTREAM_TX_OK_PORT->IDR & DOWNSTREAM_TX_OK_PIN)) #define DBGMCU_IDCODE_DEV_ID_405_407_415_417 0x413 +#define DBGMCU_IDCODE_DEV_ID_401xB_xC 0x423 + +#define BOARD_REV_PIN_MASK 0x07 +#define BOARD_ID_PIN_MASK 0x08 +#define BOARD_REV_ID_PORT GPIOC + +#define BOARD_REV_1_0_BETA 0 #endif /* INC_BOARD_CONFIG_H_ */ diff --git a/Upstream/OpenOCD_USG_v1.0.cfg b/Upstream/OpenOCD_USG_v1.0.cfg new file mode 100644 index 0000000..41e0411 --- /dev/null +++ b/Upstream/OpenOCD_USG_v1.0.cfg @@ -0,0 +1,4 @@ +# Default work area for the STM32F4x is 64K. We'll just leave it at that. +# set WORKAREASIZE 0x10000 + +source [find target/stm32f4x.cfg] diff --git a/Upstream/Src/main.c b/Upstream/Src/main.c index e14b8e0..c9b8faf 100755 --- a/Upstream/Src/main.c +++ b/Upstream/Src/main.c @@ -88,35 +88,36 @@ void CheckFirmwareMatchesHardware(void) GPIO_InitTypeDef GPIO_InitStruct; - if ((*(uint32_t*)DBGMCU_BASE & DBGMCU_IDCODE_DEV_ID) == DBGMCU_IDCODE_DEV_ID_405_407_415_417) - { - //The H405 board has a STAT LED on PC12. If there is no pullup on this pin, - //then we are probably running on another board. - __HAL_RCC_GPIOC_CLK_ENABLE(); - GPIO_InitStruct.Pin = FAULT_LED_PIN; - GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = GPIO_PULLDOWN; - GPIO_InitStruct.Speed = GPIO_SPEED_LOW; - GPIO_InitStruct.Alternate = 0; - HAL_GPIO_Init(FAULT_LED_PORT, &GPIO_InitStruct); - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(FAULT_LED_PORT, &GPIO_InitStruct); - - if (FAULT_LED_PORT->IDR & FAULT_LED_PIN) - { - //Pin pulls up, so this is an H405 board :) - return; - } - } - - //This is not the hardware we expected, so turn on our fault LED(s) and die in a heap. - GPIO_InitStruct.Pin = FAULT_LED_PIN | OTHER_BOARDS_FAULT_LED_PIN; - GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(FAULT_LED_PORT, &GPIO_InitStruct); - FAULT_LED_ON; - OTHER_BOARDS_FAULT_LED_ON; - while (1); + if ((*(uint32_t*)DBGMCU_BASE & DBGMCU_IDCODE_DEV_ID) == DBGMCU_IDCODE_DEV_ID_401xB_xC) + { + //Read in board revision and ID on port C + __HAL_RCC_GPIOC_CLK_ENABLE(); + GPIO_InitStruct.Pin = BOARD_REV_PIN_MASK | BOARD_ID_PIN_MASK; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_LOW; + GPIO_InitStruct.Alternate = 0; + HAL_GPIO_Init(BOARD_REV_ID_PORT, &GPIO_InitStruct); + + //Correct board revision? + if ((BOARD_REV_ID_PORT->IDR & BOARD_REV_PIN_MASK) == BOARD_REV_1_0_BETA) + { + //Correct board ID: upstream? + if ((BOARD_REV_ID_PORT->IDR & BOARD_ID_PIN_MASK)) + { + return; + } + } + } + + //This is not the hardware we expected, so turn on our fault LED(s) and die in a heap. + GPIO_InitStruct.Pin = FAULT_LED_PIN | H405_FAULT_LED_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(FAULT_LED_PORT, &GPIO_InitStruct); + FAULT_LED_ON; + H405_FAULT_LED_ON; + while (1); } diff --git a/Upstream/Upstream Debug.launch b/Upstream/Upstream Debug.launch index 02b5f91..e8f5790 100644 --- a/Upstream/Upstream Debug.launch +++ b/Upstream/Upstream Debug.launch @@ -16,7 +16,7 @@ - + diff --git a/Upstream/Upstream Release.launch b/Upstream/Upstream Release.launch index 3819eb6..345f6aa 100644 --- a/Upstream/Upstream Release.launch +++ b/Upstream/Upstream Release.launch @@ -16,7 +16,7 @@ - + diff --git a/Downstream/gcc_arm_stm32f407.ld b/Upstream/gcc_arm_stm32f401.ld similarity index 72% rename from Downstream/gcc_arm_stm32f407.ld rename to Upstream/gcc_arm_stm32f401.ld index 8e01b1e..704655f 100755 --- a/Downstream/gcc_arm_stm32f407.ld +++ b/Upstream/gcc_arm_stm32f401.ld @@ -1,10 +1,9 @@ /* Linker script to configure memory regions. */ MEMORY { - FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K - SRAM1 (xrw) : ORIGIN = 0x20000000, LENGTH = 112K - SRAM2 (xrw) : ORIGIN = 0x2001C000, LENGTH = 16K - CCMRAM (rw) : ORIGIN = 0x10000000, LENGTH = 64K + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256K + SRAM1 (xrw) : ORIGIN = 0x20000000, LENGTH = 64K + } /* Library configurations */ @@ -112,33 +111,5 @@ SECTIONS /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") - - - /* TODO: Place DMA buffers here. - * SRAM1 and SRAM2 can be accessed simultaneously. - * Startup file does not initialise this area. */ - .sram2 : - { - . = ALIGN(4); - *(.sram2) - *(.sram2*) - . = ALIGN(4); - } >SRAM2 - - - _siccmram = LOADADDR(.ccmram); - - /* CCM-RAM section - * Use for stack and heap if SRAM1 & SRAM2 is full. - */ - .ccmram : - { - . = ALIGN(4); - _sccmram = .; - *(.ccmram) - *(.ccmram*) - - . = ALIGN(4); - _eccmram = .; - } >CCMRAM /* AT> FLASH */ + } diff --git a/Upstream/olimex_stm32_h405.cfg b/Upstream/olimex_stm32_h405.cfg deleted file mode 100644 index 35f9ed8..0000000 --- a/Upstream/olimex_stm32_h405.cfg +++ /dev/null @@ -1,8 +0,0 @@ -# Olimex STM32-H405 eval board -# http://olimex.com/dev/stm32-h405.html - -# Default work area for the STM32F4x is 64K. We'll just leave it at that. -# Work-area size (RAM size) = 128kB for STM32F405RG device -# set WORKAREASIZE 0x20000 - -source [find target/stm32f4x.cfg]