Browse Source

Moved OpenOCD config to its own folder

USG_1.0
Robert Fisk 6 years ago
parent
commit
e94aea019e
  1. 7
      OpenOCD_scripts/README
  2. 0
      OpenOCD_scripts/board/OpenOCD_USG_v1.0.cfg
  3. 82
      OpenOCD_scripts/target/stm32f4x.cfg
  4. 4
      Upstream/OpenOCD_USG_v1.0.cfg

7
OpenOCD_scripts/README

@ -0,0 +1,7 @@
Copy these files into your OpenOCD/scripts directory, then configure Eclipse and OpenOCD to use them.
Example OpenOCD options:
-f interface/ftdi/olimex-arm-usb-tiny-h.cfg -f board/OpenOCD_USG_v1.0.cfg
More info for Eclipse OpenOCD configuration:
http://gnuarmeclipse.github.io/debug/openocd/

0
Downstream/OpenOCD_USG_v1.0.cfg → OpenOCD_scripts/board/OpenOCD_USG_v1.0.cfg

82
OpenOCD_scripts/target/stm32f4x.cfg

@ -0,0 +1,82 @@
# script for stm32f4x family
#
# stm32 devices support both JTAG and SWD transports.
#
source [find target/swj-dp.tcl]
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME stm32f4x
}
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
set _ENDIAN little
}
# Work-area is a space in RAM used for flash programming
# By default use 64kB
if { [info exists WORKAREASIZE] } {
set _WORKAREASIZE $WORKAREASIZE
} else {
set _WORKAREASIZE 0x10000
}
#jtag scan chain
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
# See STM Document RM0090
# Section 38.6.3 - corresponds to Cortex-M4 r0p1
set _CPUTAPID 0x4ba00477
}
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
if { [info exists BSTAPID] } {
set _BSTAPID $BSTAPID
} else {
# See STM Document RM0090
# Section 38.6.2
# STM32F405xx/07xx and STM32F415xx/17xx
set _BSTAPID1 0x06413041
# STM32F42xxx and STM32F43xxx
set _BSTAPID2 0x06419041
# STM32F401xB/C
set _BSTAPID3 0x06423041
# STM32F401xD/E
set _BSTAPID4 0x06433041
}
if {$using_jtag} {
jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
-expected-id $_BSTAPID2 -expected-id $_BSTAPID3 -expected-id $_BSTAPID4
}
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
#
# Since we may be running of an RC oscilator, we crank down the speed a
# bit more to be on the safe side. Perhaps superstition, but if are
# running off a crystal, we can run closer to the limit. Note
# that there can be a pretty wide band where things are more or less stable.
adapter_khz 1000
adapter_nsrst_delay 100
if {$using_jtag} {
jtag_ntrst_delay 100
}
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq

4
Upstream/OpenOCD_USG_v1.0.cfg

@ -1,4 +0,0 @@
# Default work area for the STM32F4x is 64K. We'll just leave it at that.
# set WORKAREASIZE 0x10000
source [find target/stm32f4x.cfg]
Loading…
Cancel
Save