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437 lines
12 KiB
437 lines
12 KiB
/*
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* upstream_spi.c
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*
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* Created on: 21/06/2015
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* Author: Robert Fisk
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*/
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#include <upstream_interface_def.h>
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#include <upstream_spi.h>
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#include "stm32f4xx_hal.h"
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#include "usbd_def.h"
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#include "board_config.h"
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SPI_HandleTypeDef Hspi1;
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UpstreamPacketTypeDef UpstreamPacket0;
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UpstreamPacketTypeDef UpstreamPacket1;
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UpstreamPacketTypeDef* CurrentWorkingPacket;
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UpstreamPacketTypeDef* NextTxPacket; //Indicates we have a pending TX packet
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InterfaceStateTypeDef UpstreamInterfaceState;
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FreePacketCallbackTypeDef PendingFreePacketCallback; //Indicates someone is waiting for a packet buffer to become available
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SpiPacketReceivedCallbackTypeDef ReceivePacketCallback; //Indicates someone is waiting for a received packet
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uint8_t SentCommandClass;
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uint8_t SentCommand;
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static void SPI1_Init(void);
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static HAL_StatusTypeDef Upstream_CheckBeginPacketReception(void);
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static void Upstream_BeginPacketReception(UpstreamPacketTypeDef* freePacket);
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void Upstream_InitSPI(void)
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{
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UpstreamInterfaceState = UPSTREAM_INTERFACE_RESET;
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SPI1_Init();
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UpstreamPacket0.Busy = NOT_BUSY;
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UpstreamPacket1.Busy = NOT_BUSY;
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NextTxPacket = NULL;
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PendingFreePacketCallback = NULL;
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ReceivePacketCallback = NULL;
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//Todo: check connection to downstream, await client USB insertion
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while (!DOWNSTREAM_TX_OK_ACTIVE);
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UpstreamInterfaceState = UPSTREAM_INTERFACE_IDLE;
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}
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void SPI1_Init(void)
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{
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Hspi1.Instance = SPI1;
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Hspi1.State = HAL_SPI_STATE_RESET;
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Hspi1.Init.Mode = SPI_MODE_MASTER;
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Hspi1.Init.Direction = SPI_DIRECTION_2LINES;
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Hspi1.Init.DataSize = SPI_DATASIZE_8BIT;
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Hspi1.Init.CLKPolarity = SPI_POLARITY_LOW;
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Hspi1.Init.CLKPhase = SPI_PHASE_1EDGE;
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Hspi1.Init.NSS = SPI_NSS_SOFT;
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Hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_32; //42MHz APB2 / 32 = 1.3Mbaud
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Hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
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Hspi1.Init.TIMode = SPI_TIMODE_DISABLED;
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Hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_ENABLED;
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Hspi1.Init.CRCPolynomial = SPI_CRC_DEFAULTPOLYNOMIAL;
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HAL_SPI_Init(&Hspi1);
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}
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//Used by USB interface classes, and by our internal RX code.
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HAL_StatusTypeDef Upstream_GetFreePacket(FreePacketCallbackTypeDef callback)
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{
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//Sanity checks
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if ((UpstreamInterfaceState < UPSTREAM_INTERFACE_IDLE) ||
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(UpstreamInterfaceState > UPSTREAM_INTERFACE_RX_PACKET))
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{
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SPI_INTERFACE_FREAKOUT_HAL_ERROR;
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}
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//Do we already have a queued callback?
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if (PendingFreePacketCallback != NULL)
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{
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SPI_INTERFACE_FREAKOUT_HAL_ERROR;
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}
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//Check if there is a free buffer now
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if (UpstreamPacket0.Busy == NOT_BUSY)
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{
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UpstreamPacket0.Busy = BUSY;
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callback(&UpstreamPacket0);
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return HAL_OK;
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}
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if (UpstreamPacket1.Busy == NOT_BUSY)
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{
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UpstreamPacket1.Busy = BUSY;
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callback(&UpstreamPacket1);
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return HAL_OK;
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}
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//Otherwise save requested address for when a buffer becomes free in the future
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PendingFreePacketCallback = callback;
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return HAL_OK;
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}
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UpstreamPacketTypeDef* Upstream_GetFreePacketImmediately(void)
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{
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//Sanity checks
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if ((UpstreamInterfaceState < UPSTREAM_INTERFACE_IDLE) ||
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(UpstreamInterfaceState > UPSTREAM_INTERFACE_RX_PACKET))
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{
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SPI_INTERFACE_FREAKOUT_HAL_ERROR;
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}
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//We are expecting a free buffer now
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if (UpstreamPacket0.Busy == NOT_BUSY)
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{
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UpstreamPacket0.Busy = BUSY;
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return &UpstreamPacket0;
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}
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if (UpstreamPacket1.Busy == NOT_BUSY)
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{
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UpstreamPacket1.Busy = BUSY;
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return &UpstreamPacket1;
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}
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//Should not happen:
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SPI_INTERFACE_FREAKOUT_HAL_ERROR;
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}
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//Used by USB interface classes, and by our internal RX code.
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void Upstream_ReleasePacket(UpstreamPacketTypeDef* packetToRelease)
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{
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FreePacketCallbackTypeDef tempCallback;
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if ((packetToRelease != &UpstreamPacket0) &&
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(packetToRelease != &UpstreamPacket1))
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{
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SPI_INTERFACE_FREAKOUT_HAL_ERROR;
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}
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if (PendingFreePacketCallback != NULL)
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{
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tempCallback = PendingFreePacketCallback; //In extreme situations, running this callback can trigger another request for a free packet,
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PendingFreePacketCallback = NULL; //thereby causing GetFreePacket to freak out. So we need to clear the callback indicator first.
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tempCallback(packetToRelease);
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}
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else
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{
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packetToRelease->Busy = NOT_BUSY;
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}
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}
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//Used by USB interface classes only.
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//OK to call when still transmitting another packet.
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//Not OK to call when receiving or waiting for downstream reply.
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HAL_StatusTypeDef Upstream_SendPacket(UpstreamPacketTypeDef* packetToWrite)
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{
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//Sanity checks
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if ((packetToWrite != &UpstreamPacket0) &&
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(packetToWrite != &UpstreamPacket1))
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{
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SPI_INTERFACE_FREAKOUT_HAL_ERROR;
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}
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if ((packetToWrite->Busy != BUSY) ||
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(packetToWrite->Length < UPSTREAM_PACKET_LEN_MIN) ||
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(packetToWrite->Length > UPSTREAM_PACKET_LEN))
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{
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SPI_INTERFACE_FREAKOUT_HAL_ERROR;
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}
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switch (UpstreamInterfaceState)
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{
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case UPSTREAM_INTERFACE_TX_SIZE_WAIT:
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case UPSTREAM_INTERFACE_TX_SIZE:
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case UPSTREAM_INTERFACE_TX_PACKET_WAIT:
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case UPSTREAM_INTERFACE_TX_PACKET:
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if (NextTxPacket != NULL)
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{
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SPI_INTERFACE_FREAKOUT_HAL_ERROR;
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}
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NextTxPacket = packetToWrite;
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break;
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case UPSTREAM_INTERFACE_RX_SIZE_WAIT:
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case UPSTREAM_INTERFACE_RX_SIZE:
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case UPSTREAM_INTERFACE_RX_PACKET_WAIT:
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case UPSTREAM_INTERFACE_RX_PACKET:
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//We can't let the size/packet sequence get out of sync.
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SPI_INTERFACE_FREAKOUT_HAL_ERROR;
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case UPSTREAM_INTERFACE_IDLE:
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UpstreamInterfaceState = UPSTREAM_INTERFACE_TX_SIZE_WAIT;
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CurrentWorkingPacket = packetToWrite;
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SentCommandClass = CurrentWorkingPacket->CommandClass;
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SentCommand = CurrentWorkingPacket->Command;
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if (DOWNSTREAM_TX_OK_ACTIVE)
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{
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Upstream_TxOkInterrupt(); //Manually trigger edge interrupt processing if the line was already asserted
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}
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break;
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default:
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SPI_INTERFACE_FREAKOUT_HAL_ERROR;
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}
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return HAL_OK;
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}
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//Called at the end of the SPI TX DMA transfer,
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//at DMA2 interrupt priority. Assume *hspi points to our hspi1.
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void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
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{
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SPI1_NSS_DEASSERT;
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if ((UpstreamInterfaceState != UPSTREAM_INTERFACE_TX_SIZE) &&
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(UpstreamInterfaceState != UPSTREAM_INTERFACE_TX_PACKET))
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{
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SPI_INTERFACE_FREAKOUT_VOID;
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}
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if (UpstreamInterfaceState == UPSTREAM_INTERFACE_TX_SIZE)
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{
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UpstreamInterfaceState = UPSTREAM_INTERFACE_TX_PACKET_WAIT;
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if (DOWNSTREAM_TX_OK_ACTIVE)
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{
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Upstream_TxOkInterrupt();
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}
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return;
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}
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if (UpstreamInterfaceState == UPSTREAM_INTERFACE_TX_PACKET)
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{
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if ((PendingFreePacketCallback != NULL) && (NextTxPacket == NULL))
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{
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//SPI_INTERFACE_FREAKOUT_VOID; ///////////////////////////////////////!
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}
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Upstream_ReleasePacket(CurrentWorkingPacket);
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if (NextTxPacket != NULL)
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{
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//NextTxPacket has already passed the checks in SendUpstreamPacket.
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//So we just need to pass it to HAL_SPI_Transmit_DMA.
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UpstreamInterfaceState = UPSTREAM_INTERFACE_TX_SIZE_WAIT;
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CurrentWorkingPacket = NextTxPacket;
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NextTxPacket = NULL;
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if (DOWNSTREAM_TX_OK_ACTIVE)
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{
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Upstream_TxOkInterrupt();
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}
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return;
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}
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UpstreamInterfaceState = UPSTREAM_INTERFACE_IDLE;
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if (ReceivePacketCallback != NULL)
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{
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Upstream_CheckBeginPacketReception();
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}
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}
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}
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//Used by USB interface classes.
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//Ok to call when idle or transmitting.
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//Not OK to call when receiving or waiting for downstream reply.
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HAL_StatusTypeDef Upstream_GetPacket(SpiPacketReceivedCallbackTypeDef callback)
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{
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if (ReceivePacketCallback != NULL)
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{
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SPI_INTERFACE_FREAKOUT_HAL_ERROR;
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}
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ReceivePacketCallback = callback;
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return Upstream_CheckBeginPacketReception();
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}
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//Internal use only.
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HAL_StatusTypeDef Upstream_CheckBeginPacketReception(void)
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{
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if ((UpstreamInterfaceState < UPSTREAM_INTERFACE_IDLE) ||
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(UpstreamInterfaceState > UPSTREAM_INTERFACE_RX_SIZE_WAIT))
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{
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SPI_INTERFACE_FREAKOUT_HAL_ERROR;
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}
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if (UpstreamInterfaceState == UPSTREAM_INTERFACE_IDLE)
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{
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UpstreamInterfaceState = UPSTREAM_INTERFACE_RX_SIZE_WAIT;
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}
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if (UpstreamInterfaceState == UPSTREAM_INTERFACE_RX_SIZE_WAIT)
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{
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if (DOWNSTREAM_TX_OK_ACTIVE)
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{
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//UpstreamTxOkInterrupt();
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Upstream_GetFreePacket(Upstream_BeginPacketReception); //Take a shortcut here :)
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}
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}
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return HAL_OK;
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}
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//This is called by EXTI3 falling edge interrupt,
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//indicating that downstream is ready for next transaction.
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void Upstream_TxOkInterrupt(void)
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{
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switch (UpstreamInterfaceState)
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{
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case UPSTREAM_INTERFACE_TX_SIZE_WAIT:
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UpstreamInterfaceState = UPSTREAM_INTERFACE_TX_SIZE;
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SPI1_NSS_ASSERT;
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if (HAL_SPI_Transmit_DMA(&Hspi1,
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(uint8_t*)&CurrentWorkingPacket->Length,
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2) != HAL_OK)
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{
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SPI_INTERFACE_FREAKOUT_VOID;
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}
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break;
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case UPSTREAM_INTERFACE_TX_PACKET_WAIT:
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UpstreamInterfaceState = UPSTREAM_INTERFACE_TX_PACKET;
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SPI1_NSS_ASSERT;
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if ((HAL_SPI_Transmit_DMA(&Hspi1,
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&CurrentWorkingPacket->CommandClass,
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CurrentWorkingPacket->Length)) != HAL_OK)
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{
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SPI_INTERFACE_FREAKOUT_VOID;
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}
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break;
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case UPSTREAM_INTERFACE_RX_SIZE_WAIT:
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Upstream_GetFreePacket(Upstream_BeginPacketReception);
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break;
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case UPSTREAM_INTERFACE_RX_PACKET_WAIT:
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UpstreamInterfaceState = UPSTREAM_INTERFACE_RX_PACKET;
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SPI1_NSS_ASSERT;
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if ((HAL_SPI_Receive_DMA(&Hspi1,
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&CurrentWorkingPacket->CommandClass,
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(CurrentWorkingPacket->Length + 1))) != HAL_OK) //"When the CRC feature is enabled the pData Length must be Size + 1"
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{
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SPI_INTERFACE_FREAKOUT_VOID;
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}
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break;
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default:
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SPI_INTERFACE_FREAKOUT_VOID;
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}
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}
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//Internal use only.
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//Called when we want to receive downstream packet, and a packet buffer has become free.
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void Upstream_BeginPacketReception(UpstreamPacketTypeDef* freePacket)
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{
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if (UpstreamInterfaceState != UPSTREAM_INTERFACE_RX_SIZE_WAIT)
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{
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SPI_INTERFACE_FREAKOUT_VOID;
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}
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UpstreamInterfaceState = UPSTREAM_INTERFACE_RX_SIZE;
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CurrentWorkingPacket = freePacket;
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CurrentWorkingPacket->Length = 0; //Our RX buffer is used by HAL_SPI_Receive_DMA as dummy TX data, we set Length to 0 so downstream will know this is a dummy packet.
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SPI1_NSS_ASSERT;
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if (HAL_SPI_Receive_DMA(&Hspi1,
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(uint8_t*)&CurrentWorkingPacket->Length,
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(2 + 1)) != HAL_OK) //"When the CRC feature is enabled the pData Length must be Size + 1"
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{
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SPI_INTERFACE_FREAKOUT_VOID;
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}
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}
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//Called at the end of the SPI TX DMA transfer,
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//at DMA2 interrupt priority. Assume *hspi points to our hspi1.
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void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
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{
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SpiPacketReceivedCallbackTypeDef tempPacketCallback;
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SPI1_NSS_DEASSERT;
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if ((UpstreamInterfaceState != UPSTREAM_INTERFACE_RX_SIZE) &&
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(UpstreamInterfaceState != UPSTREAM_INTERFACE_RX_PACKET))
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{
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SPI_INTERFACE_FREAKOUT_VOID;
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}
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if (UpstreamInterfaceState == UPSTREAM_INTERFACE_RX_SIZE)
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{
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if ((CurrentWorkingPacket->Length < UPSTREAM_PACKET_LEN_MIN) ||
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(CurrentWorkingPacket->Length > UPSTREAM_PACKET_LEN))
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{
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SPI_INTERFACE_FREAKOUT_VOID;
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}
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UpstreamInterfaceState = UPSTREAM_INTERFACE_RX_PACKET_WAIT;
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if (DOWNSTREAM_TX_OK_ACTIVE)
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{
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Upstream_TxOkInterrupt();
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}
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return;
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}
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if (UpstreamInterfaceState == UPSTREAM_INTERFACE_RX_PACKET)
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{
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UpstreamInterfaceState = UPSTREAM_INTERFACE_IDLE;
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if ((SentCommandClass != (CurrentWorkingPacket->CommandClass & COMMAND_CLASS_MASK)) ||
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(SentCommand != CurrentWorkingPacket->Command))
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{
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SPI_INTERFACE_FREAKOUT_VOID;
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}
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if (ReceivePacketCallback == NULL)
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{
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SPI_INTERFACE_FREAKOUT_VOID;
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}
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//USB interface may want to receive another packet immediately,
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//so clear ReceivePacketCallback before the call.
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//It is the callback's responsibility to release the packet buffer we are passing to it!
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tempPacketCallback = ReceivePacketCallback;
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ReceivePacketCallback = NULL;
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tempPacketCallback(CurrentWorkingPacket);
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}
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}
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//Something bad happened! Possibly CRC error...
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void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
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{
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SPI_INTERFACE_FREAKOUT_VOID;
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}
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