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394 lines
10 KiB
394 lines
10 KiB
/*
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* upstream_spi.c
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*
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* Created on: 24/07/2015
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* Author: Robert Fisk
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*
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* This Source Code Form is subject to the terms of the Mozilla Public
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* License, v. 2.0. If a copy of the MPL was not distributed with this
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* file, You can obtain one at https://mozilla.org/MPL/2.0/.
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*/
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#include "downstream_interface_def.h"
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#include "downstream_spi.h"
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#include "downstream_statemachine.h"
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#include "board_config.h"
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#include "led.h"
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SPI_HandleTypeDef Hspi1;
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DownstreamPacketTypeDef DownstreamPacket0;
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DownstreamPacketTypeDef DownstreamPacket1;
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DownstreamPacketTypeDef* CurrentWorkingPacket;
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DownstreamPacketTypeDef* NextTxPacket = NULL;
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InterfaceStateTypeDef DownstreamInterfaceState = DOWNSTREAM_INTERFACE_IDLE;
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FreePacketCallbackTypeDef PendingFreePacketCallback = NULL; //Indicates someone is waiting for a packet buffer to become available
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SpiPacketReceivedCallbackTypeDef ReceivePacketCallback = NULL; //Indicates someone is waiting for a received packet
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uint32_t TemporaryIncomingPacketLength = 0;
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uint8_t SpiInterruptCompleted = 0;
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HAL_StatusTypeDef Downstream_CheckPreparePacketReception(void);
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void Downstream_PrepareReceivePacketSize(DownstreamPacketTypeDef* freePacket);
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void Downstream_InitSPI(void)
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{
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DownstreamPacket0.Busy = NOT_BUSY;
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DownstreamPacket1.Busy = NOT_BUSY;
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Hspi1.Instance = SPI1;
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Hspi1.Init.Mode = SPI_MODE_SLAVE;
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Hspi1.Init.Direction = SPI_DIRECTION_2LINES;
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Hspi1.Init.DataSize = SPI_DATASIZE_16BIT;
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Hspi1.Init.CLKPolarity = SPI_POLARITY_LOW;
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Hspi1.Init.CLKPhase = SPI_PHASE_1EDGE;
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Hspi1.Init.NSS = SPI_NSS_HARD_INPUT;
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Hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
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Hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
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Hspi1.Init.TIMode = SPI_TIMODE_DISABLED;
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Hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_ENABLE;
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Hspi1.Init.CRCPolynomial = SPI_CRC_DEFAULTPOLYNOMIAL;
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HAL_SPI_Init(&Hspi1);
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}
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//Used by downstream state machine and USB host classes.
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HAL_StatusTypeDef Downstream_GetFreePacket(FreePacketCallbackTypeDef callback)
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{
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if (DownstreamInterfaceState >= DOWNSTREAM_INTERFACE_ERROR)
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{
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return HAL_ERROR;
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}
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//Do we already have a queued callback?
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if (PendingFreePacketCallback != NULL)
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{
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DOWNSTREAM_SPI_FREAKOUT;
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return HAL_ERROR;
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}
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//Check if there is a free buffer now
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if (DownstreamPacket0.Busy == NOT_BUSY)
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{
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DownstreamPacket0.Busy = BUSY;
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callback(&DownstreamPacket0);
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return HAL_OK;
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}
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if (DownstreamPacket1.Busy == NOT_BUSY)
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{
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DownstreamPacket1.Busy = BUSY;
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callback(&DownstreamPacket1);
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return HAL_OK;
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}
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//Otherwise save requested address for when a buffer becomes free in the future
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PendingFreePacketCallback = callback;
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return HAL_OK;
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}
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//Used by Downstream state machine and USB host classes.
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void Downstream_ReleasePacket(DownstreamPacketTypeDef* packetToRelease)
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{
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FreePacketCallbackTypeDef tempCallback;
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if (DownstreamInterfaceState >= DOWNSTREAM_INTERFACE_ERROR)
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{
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return;
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}
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if ((packetToRelease != &DownstreamPacket0) &&
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(packetToRelease != &DownstreamPacket1))
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{
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DOWNSTREAM_SPI_FREAKOUT;
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return;
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}
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if (PendingFreePacketCallback != NULL)
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{
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tempCallback = PendingFreePacketCallback; //In extreme situations, running this callback can trigger another request for a free packet,
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PendingFreePacketCallback = NULL; //thereby causing GetFreePacket to freak out. So we need to clear the callback indicator first.
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tempCallback(packetToRelease);
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}
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else
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{
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packetToRelease->Busy = NOT_BUSY;
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}
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}
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//Used by Downstream state machine and USB classes.
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//Ok to call when idle or transmitting.
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//Not OK to call when receiving or awaiting reception.
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HAL_StatusTypeDef Downstream_ReceivePacket(SpiPacketReceivedCallbackTypeDef callback)
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{
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if (DownstreamInterfaceState >= DOWNSTREAM_INTERFACE_ERROR)
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{
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return HAL_ERROR;
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}
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if ((DownstreamInterfaceState == DOWNSTREAM_INTERFACE_RX_SIZE_WAIT) ||
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(DownstreamInterfaceState == DOWNSTREAM_INTERFACE_RX_PACKET_WAIT) ||
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(ReceivePacketCallback != NULL))
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{
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DOWNSTREAM_SPI_FREAKOUT;
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return HAL_ERROR;
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}
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ReceivePacketCallback = callback;
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return Downstream_CheckPreparePacketReception();
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}
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//Internal use only
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HAL_StatusTypeDef Downstream_CheckPreparePacketReception(void)
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{
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if (DownstreamInterfaceState >= DOWNSTREAM_INTERFACE_ERROR)
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{
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return HAL_ERROR;
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}
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if (DownstreamInterfaceState == DOWNSTREAM_INTERFACE_IDLE)
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{
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DownstreamInterfaceState = DOWNSTREAM_INTERFACE_RX_SIZE_WAIT;
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return Downstream_GetFreePacket(Downstream_PrepareReceivePacketSize);
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}
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return HAL_OK;
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}
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//Internal use only
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void Downstream_PrepareReceivePacketSize(DownstreamPacketTypeDef* freePacket)
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{
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if (DownstreamInterfaceState >= DOWNSTREAM_INTERFACE_ERROR)
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{
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return;
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}
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if (DownstreamInterfaceState != DOWNSTREAM_INTERFACE_RX_SIZE_WAIT)
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{
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DOWNSTREAM_SPI_FREAKOUT;
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return;
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}
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CurrentWorkingPacket = freePacket;
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CurrentWorkingPacket->Length16 = 0;
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if (HAL_SPI_TransmitReceive_IT(&Hspi1,
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(uint8_t*)&CurrentWorkingPacket->Length16,
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(uint8_t*)&CurrentWorkingPacket->Length16,
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2) != HAL_OK) //We only need to read one word, but the peripheral library freaks out...
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{
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DOWNSTREAM_SPI_FREAKOUT;
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return;
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}
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UPSTREAM_TX_REQUEST_ASSERT;
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}
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//Used by Downstream state machine and USB classes.
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//Call when idle or transmitting.
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//It doesn't make sense to call when receiving or awaiting reception.
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HAL_StatusTypeDef Downstream_TransmitPacket(DownstreamPacketTypeDef* packetToWrite)
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{
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if (DownstreamInterfaceState >= DOWNSTREAM_INTERFACE_ERROR)
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{
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return HAL_ERROR;
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}
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//Sanity checks
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if ((packetToWrite != &DownstreamPacket0) &&
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(packetToWrite != &DownstreamPacket1))
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{
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DOWNSTREAM_SPI_FREAKOUT;
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return HAL_ERROR;
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}
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if ((packetToWrite->Busy != BUSY) ||
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(packetToWrite->Length16 < DOWNSTREAM_PACKET_LEN_MIN_16) ||
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(packetToWrite->Length16 > DOWNSTREAM_PACKET_LEN_16))
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{
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DOWNSTREAM_SPI_FREAKOUT;
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return HAL_ERROR;
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}
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if (NextTxPacket != NULL)
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{
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DOWNSTREAM_SPI_FREAKOUT;
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return HAL_ERROR;
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}
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switch (DownstreamInterfaceState)
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{
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case DOWNSTREAM_INTERFACE_TX_SIZE_WAIT:
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case DOWNSTREAM_INTERFACE_TX_PACKET_WAIT:
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NextTxPacket = packetToWrite;
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break;
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case DOWNSTREAM_INTERFACE_IDLE:
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DownstreamInterfaceState = DOWNSTREAM_INTERFACE_TX_SIZE_WAIT;
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CurrentWorkingPacket = packetToWrite;
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if (HAL_SPI_TransmitReceive_IT(&Hspi1,
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(uint8_t*)&CurrentWorkingPacket->Length16,
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(uint8_t*)&TemporaryIncomingPacketLength,
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2) != HAL_OK) //We only need to write one word, but the peripheral library freaks out...
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{
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DOWNSTREAM_SPI_FREAKOUT;
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return HAL_ERROR;
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}
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UPSTREAM_TX_REQUEST_ASSERT;
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break;
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default:
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DOWNSTREAM_SPI_FREAKOUT;
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return HAL_ERROR;
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}
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return HAL_OK;
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}
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//Do stuff at main loop priority after SPI transaction is complete
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void Downstream_SPIProcess(void)
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{
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SpiPacketReceivedCallbackTypeDef tempPacketCallback;
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if (SpiInterruptCompleted == 0)
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{
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return;
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}
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SpiInterruptCompleted = 0;
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UPSTREAM_TX_REQUEST_DEASSERT;
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if (DownstreamInterfaceState >= DOWNSTREAM_INTERFACE_ERROR)
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{
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return;
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}
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//Finished transmitting packet size
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if (DownstreamInterfaceState == DOWNSTREAM_INTERFACE_TX_SIZE_WAIT)
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{
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if (TemporaryIncomingPacketLength != 0)
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{
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//Currently we just freak out if Upstream sends us an unexpected command.
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//Theoretically we could reset our downstream state machine and accept the new command...
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DOWNSTREAM_SPI_FREAKOUT;
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return;
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}
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DownstreamInterfaceState = DOWNSTREAM_INTERFACE_TX_PACKET_WAIT;
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if (HAL_SPI_TransmitReceive_IT(&Hspi1,
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&CurrentWorkingPacket->CommandClass,
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&CurrentWorkingPacket->CommandClass,
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((CurrentWorkingPacket->Length16 < 2) ? 2 : CurrentWorkingPacket->Length16)) != HAL_OK)
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{
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DOWNSTREAM_SPI_FREAKOUT;
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return;
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}
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UPSTREAM_TX_REQUEST_ASSERT;
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return;
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}
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//Finished transmitting packet body
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if (DownstreamInterfaceState == DOWNSTREAM_INTERFACE_TX_PACKET_WAIT)
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{
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Downstream_ReleasePacket(CurrentWorkingPacket);
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if (NextTxPacket != NULL)
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{
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//NextTxPacket has already passed the checks in Downstream_TransmitPacket.
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//So we just need to pass it to HAL_SPI_Transmit_DMA.
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DownstreamInterfaceState = DOWNSTREAM_INTERFACE_TX_SIZE_WAIT;
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CurrentWorkingPacket = NextTxPacket;
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NextTxPacket = NULL;
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if (HAL_SPI_TransmitReceive_IT(&Hspi1,
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(uint8_t*)&CurrentWorkingPacket->Length16,
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(uint8_t*)&TemporaryIncomingPacketLength,
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2) != HAL_OK) //We only need to write one word, but the peripheral library freaks out...
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{
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DOWNSTREAM_SPI_FREAKOUT;
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return;
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}
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UPSTREAM_TX_REQUEST_ASSERT;
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return;
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}
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DownstreamInterfaceState = DOWNSTREAM_INTERFACE_IDLE;
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if (ReceivePacketCallback != NULL)
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{
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Downstream_CheckPreparePacketReception();
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}
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return;
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}
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if (DownstreamInterfaceState == DOWNSTREAM_INTERFACE_RX_SIZE_WAIT)
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{
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if ((CurrentWorkingPacket->Length16 < DOWNSTREAM_PACKET_LEN_MIN_16) ||
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(CurrentWorkingPacket->Length16 > DOWNSTREAM_PACKET_LEN_16))
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{
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DOWNSTREAM_SPI_FREAKOUT;
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return;
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}
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DownstreamInterfaceState = DOWNSTREAM_INTERFACE_RX_PACKET_WAIT;
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if (HAL_SPI_TransmitReceive_IT(&Hspi1,
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&CurrentWorkingPacket->CommandClass,
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&CurrentWorkingPacket->CommandClass,
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((CurrentWorkingPacket->Length16 < 2) ? 2 : CurrentWorkingPacket->Length16)) != HAL_OK)
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{
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DOWNSTREAM_SPI_FREAKOUT;
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return;
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}
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UPSTREAM_TX_REQUEST_ASSERT;
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return;
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}
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if (DownstreamInterfaceState == DOWNSTREAM_INTERFACE_RX_PACKET_WAIT)
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{
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DownstreamInterfaceState = DOWNSTREAM_INTERFACE_IDLE;
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if (ReceivePacketCallback == NULL)
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{
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DOWNSTREAM_SPI_FREAKOUT;
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return;
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}
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//Packet processor may want to receive another packet immediately,
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//so clear ReceivePacketCallback before the call.
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//It is the callback's responsibility to release the packet buffer we are passing to it!
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tempPacketCallback = ReceivePacketCallback;
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ReceivePacketCallback = NULL;
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tempPacketCallback(CurrentWorkingPacket);
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return;
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}
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//case default:
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DOWNSTREAM_SPI_FREAKOUT;
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}
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//Called at the end of the SPI TxRx DMA transfer,
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//at DMA2 interrupt priority. Assume *hspi points to our hspi1.
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//We use TxRx to send our reply packet to check if Upstream was trying
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//to send us a packet at the same time.
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//We also TxRx our packet body because the SPI silicon is buggy at the end of
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//a transmit-only DMA transfer with CRC! (it does not clear RXNE flag on request)
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void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
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{
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SpiInterruptCompleted = 1;
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}
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//Something bad happened! Possibly CRC error...
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void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
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{
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DOWNSTREAM_SPI_FREAKOUT;
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}
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