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/**
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******************************************************************************
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* @file stm32f4xx_hal_rcc_ex.c
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* @author MCD Application Team
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* @version V1.2.0
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* @date 26-December-2014
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* @brief Extension RCC HAL module driver.
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* This file provides firmware functions to manage the following
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* functionalities RCC extension peripheral:
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* + Extended Peripheral Control functions
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*
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f4xx_hal.h"
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/** @addtogroup STM32F4xx_HAL_Driver
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* @{
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*/
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/** @defgroup RCCEx RCCEx
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* @brief RCCEx HAL module driver
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* @{
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*/
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#ifdef HAL_RCC_MODULE_ENABLED
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/** @addtogroup RCCEx_Private_Constants
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* @{
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*/
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#define PLLI2S_TIMEOUT_VALUE 100 /* Timeout value fixed to 100 ms */
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#define PLLSAI_TIMEOUT_VALUE 100 /* Timeout value fixed to 100 ms */
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/**
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* @}
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*/
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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/* Private functions ---------------------------------------------------------*/
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/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
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* @{
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*/
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/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
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* @brief Extended Peripheral Control functions
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*
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@verbatim
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===============================================================================
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##### Extended Peripheral Control functions #####
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===============================================================================
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[..]
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This subsection provides a set of functions allowing to control the RCC Clocks
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frequencies.
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[..]
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(@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
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select the RTC clock source; in this case the Backup domain will be reset in
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order to modify the RTC Clock source, as consequence RTC registers (including
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the backup registers) and RCC_BDCR register are set to their reset values.
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@endverbatim
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* @{
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*/
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#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
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/**
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* @brief Initializes the RCC extended peripherals clocks according to the specified
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* parameters in the RCC_PeriphCLKInitTypeDef.
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* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
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* contains the configuration information for the Extended Peripherals
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* clocks(I2S, SAI, LTDC RTC and TIM).
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*
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* @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
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* the RTC clock source; in this case the Backup domain will be reset in
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* order to modify the RTC Clock source, as consequence RTC registers (including
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* the backup registers) and RCC_BDCR register are set to their reset values.
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*
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
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{
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uint32_t tickstart = 0;
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uint32_t tmpreg = 0;
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/* Check the parameters */
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assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
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/*----------------------- SAI/I2S Configuration (PLLI2S) -------------------------*/
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/*----------------------- Common configuration SAI/I2S ---------------------------*/
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/* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division
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factor is common parameters for both peripherals */
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if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) ||
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(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S))
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{
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/* check for Parameters */
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assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
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/* Disable the PLLI2S */
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__HAL_RCC_PLLI2S_DISABLE();
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/* Get tick */
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tickstart = HAL_GetTick();
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/* Wait till PLLI2S is disabled */
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while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
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{
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if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
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{
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/* return in case of Timeout detected */
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return HAL_TIMEOUT;
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}
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}
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/*---------------------------- I2S configuration -------------------------------*/
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/* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added
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only for I2S configuration */
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if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
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{
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/* check for Parameters */
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assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
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/* Configure the PLLI2S division factors */
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/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) <20> (PLLI2SN/PLLM) */
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/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
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__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
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}
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/*---------------------------- SAI configuration -------------------------------*/
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/* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must
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be added only for SAI configuration */
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if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S))
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{
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/* Check the PLLI2S division factors */
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assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
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assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
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/* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
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tmpreg = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
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/* Configure the PLLI2S division factors */
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/* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
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/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
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/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
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__HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ , tmpreg);
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/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
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__HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
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}
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/* Enable the PLLI2S */
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__HAL_RCC_PLLI2S_ENABLE();
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/* Get tick */
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tickstart = HAL_GetTick();
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/* Wait till PLLI2S is ready */
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while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
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{
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if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
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{
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/* return in case of Timeout detected */
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return HAL_TIMEOUT;
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}
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}
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}
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/*----------------------- SAI/LTDC Configuration (PLLSAI) ------------------*/
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/*----------------------- Common configuration SAI/LTDC --------------------*/
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/* In Case of SAI or LTDC Clock Configuration through PLLSAI, PLLSAIN division
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factor is common parameters for both peripherals */
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if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) ||
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(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC))
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{
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/* Check the PLLSAI division factors */
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assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
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/* Disable PLLSAI Clock */
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__HAL_RCC_PLLSAI_DISABLE();
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/* Get tick */
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tickstart = HAL_GetTick();
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/* Wait till PLLSAI is disabled */
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while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
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{
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if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
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{
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/* return in case of Timeout detected */
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return HAL_TIMEOUT;
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}
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}
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/*---------------------------- SAI configuration -------------------------*/
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/* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must
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be added only for SAI configuration */
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if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI))
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{
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assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
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assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
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/* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
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tmpreg = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
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/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
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/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
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/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
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__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg);
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/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
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__HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
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}
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/*---------------------------- LTDC configuration ------------------------*/
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if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
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{
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assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
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assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
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/* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
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tmpreg = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
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/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
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/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
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/* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
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__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg, PeriphClkInit->PLLSAI.PLLSAIR);
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/* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
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__HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
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}
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/* Enable PLLSAI Clock */
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__HAL_RCC_PLLSAI_ENABLE();
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/* Get tick */
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tickstart = HAL_GetTick();
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/* Wait till PLLSAI is ready */
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while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
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{
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if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
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{
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/* return in case of Timeout detected */
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return HAL_TIMEOUT;
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}
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}
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}
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/*---------------------------- RTC configuration ---------------------------*/
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if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
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{
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/* Enable Power Clock*/
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__HAL_RCC_PWR_CLK_ENABLE();
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/* Enable write access to Backup domain */
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PWR->CR |= PWR_CR_DBP;
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/* Get tick */
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tickstart = HAL_GetTick();
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while((PWR->CR & PWR_CR_DBP) == RESET)
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{
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if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
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{
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return HAL_TIMEOUT;
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}
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}
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/* Reset the Backup domain only if the RTC Clock source selection is modified */
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if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
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{
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/* Store the content of BDCR register before the reset of Backup Domain */
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tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
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/* RTC Clock selection can be changed only if the Backup Domain is reset */
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__HAL_RCC_BACKUPRESET_FORCE();
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__HAL_RCC_BACKUPRESET_RELEASE();
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/* Restore the Content of BDCR register */
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RCC->BDCR = tmpreg;
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}
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/* If LSE is selected as RTC clock source, wait for LSE reactivation */
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if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
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{
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/* Get tick */
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tickstart = HAL_GetTick();
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/* Wait till LSE is ready */
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while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
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{
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if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
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{
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return HAL_TIMEOUT;
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}
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}
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}
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__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
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}
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/*---------------------------- TIM configuration ---------------------------*/
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if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
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{
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__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
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}
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return HAL_OK;
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}
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/**
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* @brief Configures the RCC_OscInitStruct according to the internal
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* RCC configuration registers.
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* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
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* will be configured.
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* @retval None
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*/
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void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
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{
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uint32_t tempreg;
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/* Set all possible values for the extended clock type parameter------------*/
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PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_SAI_PLLSAI | RCC_PERIPHCLK_SAI_PLLI2S | RCC_PERIPHCLK_LTDC | RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC;
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/* Get the PLLI2S Clock configuration -----------------------------------------------*/
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PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
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PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
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PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
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/* Get the PLLSAI Clock configuration -----------------------------------------------*/
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PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN));
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PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
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PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
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/* Get the PLLSAI/PLLI2S division factors -----------------------------------------------*/
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PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLI2SDIVQ));
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PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLSAIDIVQ));
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PeriphClkInit->PLLSAIDivR = (uint32_t)(RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVR);
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/* Get the RTC Clock configuration -----------------------------------------------*/
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tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
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PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
|
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|
|
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|
if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
|
|
|
{
|
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|
PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
|
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|
}
|
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|
else
|
|
|
{
|
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|
PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
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|
}
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}
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#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
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#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\
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defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
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/**
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* @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the
|
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|
* RCC_PeriphCLKInitTypeDef.
|
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|
* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
|
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|
* contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks).
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|
*
|
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* @note A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case
|
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|
* the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup
|
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|
* domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset
|
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|
*
|
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|
* @retval HAL status
|
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|
*/
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HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
|
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|
{
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uint32_t tickstart = 0;
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uint32_t tmpreg = 0;
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|
|
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/* Check the parameters */
|
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assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
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|
|
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|
/*---------------------------- I2S configuration ---------------------------*/
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|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
|
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|
{
|
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|
/* check for Parameters */
|
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|
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
|
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|
assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
|
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|
#if defined(STM32F411xE)
|
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|
assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM));
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#endif /* STM32F411xE */
|
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/* Disable the PLLI2S */
|
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|
__HAL_RCC_PLLI2S_DISABLE();
|
|
|
/* Get tick */
|
|
|
tickstart = HAL_GetTick();
|
|
|
/* Wait till PLLI2S is disabled */
|
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
|
|
|
{
|
|
|
if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
|
|
|
{
|
|
|
/* return in case of Timeout detected */
|
|
|
return HAL_TIMEOUT;
|
|
|
}
|
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|
}
|
|
|
|
|
|
#if defined(STM32F411xE)
|
|
|
/* Configure the PLLI2S division factors */
|
|
|
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) <20> (PLLI2SN/PLLI2SM) */
|
|
|
/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
|
|
|
__HAL_RCC_PLLI2S_I2SCLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SR);
|
|
|
#else
|
|
|
/* Configure the PLLI2S division factors */
|
|
|
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) <20> (PLLI2SN/PLLM) */
|
|
|
/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
|
|
|
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
|
|
|
#endif /* STM32F411xE */
|
|
|
|
|
|
/* Enable the PLLI2S */
|
|
|
__HAL_RCC_PLLI2S_ENABLE();
|
|
|
/* Get tick */
|
|
|
tickstart = HAL_GetTick();
|
|
|
/* Wait till PLLI2S is ready */
|
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
|
|
|
{
|
|
|
if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
|
|
|
{
|
|
|
/* return in case of Timeout detected */
|
|
|
return HAL_TIMEOUT;
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
|
|
|
/*---------------------------- RTC configuration ---------------------------*/
|
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
|
|
|
{
|
|
|
/* Enable Power Clock*/
|
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
|
|
|
|
/* Enable write access to Backup domain */
|
|
|
PWR->CR |= PWR_CR_DBP;
|
|
|
|
|
|
/* Get tick */
|
|
|
tickstart = HAL_GetTick();
|
|
|
|
|
|
while((PWR->CR & PWR_CR_DBP) == RESET)
|
|
|
{
|
|
|
if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
}
|
|
|
}
|
|
|
|
|
|
/* Reset the Backup domain only if the RTC Clock source selection is modified */
|
|
|
if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
|
|
|
{
|
|
|
/* Store the content of BDCR register before the reset of Backup Domain */
|
|
|
tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
|
|
|
/* RTC Clock selection can be changed only if the Backup Domain is reset */
|
|
|
__HAL_RCC_BACKUPRESET_FORCE();
|
|
|
__HAL_RCC_BACKUPRESET_RELEASE();
|
|
|
/* Restore the Content of BDCR register */
|
|
|
RCC->BDCR = tmpreg;
|
|
|
}
|
|
|
|
|
|
/* If LSE is selected as RTC clock source, wait for LSE reactivation */
|
|
|
if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
|
|
|
{
|
|
|
/* Get tick */
|
|
|
tickstart = HAL_GetTick();
|
|
|
|
|
|
/* Wait till LSE is ready */
|
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
|
{
|
|
|
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
|
|
|
}
|
|
|
|
|
|
return HAL_OK;
|
|
|
}
|
|
|
|
|
|
/**
|
|
|
* @brief Configures the RCC_OscInitStruct according to the internal
|
|
|
* RCC configuration registers.
|
|
|
* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
|
|
|
* will be configured.
|
|
|
* @retval None
|
|
|
*/
|
|
|
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
|
|
|
{
|
|
|
uint32_t tempreg;
|
|
|
|
|
|
/* Set all possible values for the extended clock type parameter------------*/
|
|
|
PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_RTC;
|
|
|
|
|
|
/* Get the PLLI2S Clock configuration -----------------------------------------------*/
|
|
|
PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
|
|
|
PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
|
|
|
#if defined(STM32F411xE)
|
|
|
PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM);
|
|
|
#endif /* STM32F411xE */
|
|
|
/* Get the RTC Clock configuration -----------------------------------------------*/
|
|
|
tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
|
|
|
PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
|
|
|
|
|
|
}
|
|
|
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
|
|
|
|
|
|
#if defined(STM32F411xE)
|
|
|
/**
|
|
|
* @brief Select LSE mode
|
|
|
*
|
|
|
* @note This mode is only available for STM32F411xx devices.
|
|
|
*
|
|
|
* @param Mode: specifies the LSE mode.
|
|
|
* This parameter can be one of the following values:
|
|
|
* @arg RCC_LSE_LOWPOWER_MODE: LSE oscillator in low power mode selection
|
|
|
* @arg RCC_LSE_HIGHDRIVE_MODE: LSE oscillator in High Drive mode selection
|
|
|
* @retval None
|
|
|
*/
|
|
|
void HAL_RCCEx_SelectLSEMode(uint8_t Mode)
|
|
|
{
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_RCC_LSE_MODE(Mode));
|
|
|
if(Mode == RCC_LSE_HIGHDRIVE_MODE)
|
|
|
{
|
|
|
SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
|
|
|
}
|
|
|
}
|
|
|
|
|
|
#endif /* STM32F411xE */
|
|
|
|
|
|
/**
|
|
|
* @}
|
|
|
*/
|
|
|
|
|
|
/**
|
|
|
* @}
|
|
|
*/
|
|
|
|
|
|
#endif /* HAL_RCC_MODULE_ENABLED */
|
|
|
/**
|
|
|
* @}
|
|
|
*/
|
|
|
|
|
|
/**
|
|
|
* @}
|
|
|
*/
|
|
|
|
|
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
