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967 lines
29 KiB
967 lines
29 KiB
/**
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******************************************************************************
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* @file stm32f4xx_hal_nor.c
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* @author MCD Application Team
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* @version V1.2.0
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* @date 26-December-2014
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* @brief NOR HAL module driver.
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* This file provides a generic firmware to drive NOR memories mounted
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* as external device.
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*
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@verbatim
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==============================================================================
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##### How to use this driver #####
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==============================================================================
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[..]
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This driver is a generic layered driver which contains a set of APIs used to
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control NOR flash memories. It uses the FMC/FSMC layer functions to interface
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with NOR devices. This driver is used as follows:
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(+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
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with control and timing parameters for both normal and extended mode.
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(+) Read NOR flash memory manufacturer code and device IDs using the function
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HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
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structure declared by the function caller.
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(+) Access NOR flash memory by read/write data unit operations using the functions
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HAL_NOR_Read(), HAL_NOR_Program().
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(+) Perform NOR flash erase block/chip operations using the functions
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HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
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(+) Read the NOR flash CFI (common flash interface) IDs using the function
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HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
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structure declared by the function caller.
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(+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
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HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation
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(+) You can monitor the NOR device HAL state by calling the function
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HAL_NOR_GetState()
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[..]
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(@) This driver is a set of generic APIs which handle standard NOR flash operations.
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If a NOR flash device contains different operations and/or implementations,
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it should be implemented separately.
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*** NOR HAL driver macros list ***
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=============================================
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[..]
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Below the list of most used macros in NOR HAL driver.
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(+) NOR_WRITE : NOR memory write data to specified address
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@endverbatim
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f4xx_hal.h"
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/** @addtogroup STM32F4xx_HAL_Driver
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* @{
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*/
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/** @defgroup NOR NOR
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* @brief NOR driver modules
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* @{
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*/
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#ifdef HAL_NOR_MODULE_ENABLED
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#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private functions ---------------------------------------------------------*/
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/* Exported functions --------------------------------------------------------*/
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/** @defgroup NOR_Exported_Functions NOR Exported Functions
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* @{
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*/
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/** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
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* @brief Initialization and Configuration functions
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*
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@verbatim
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==============================================================================
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##### NOR Initialization and de_initialization functions #####
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==============================================================================
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[..]
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This section provides functions allowing to initialize/de-initialize
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the NOR memory
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@endverbatim
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* @{
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*/
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/**
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* @brief Perform the NOR memory Initialization sequence
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* @param hnor: pointer to the NOR handle
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* @param Timing: pointer to NOR control timing structure
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* @param ExtTiming: pointer to NOR extended mode timing structure
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
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{
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/* Check the NOR handle parameter */
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if(hnor == NULL)
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{
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return HAL_ERROR;
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}
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if(hnor->State == HAL_NOR_STATE_RESET)
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{
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/* Initialize the low level hardware (MSP) */
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HAL_NOR_MspInit(hnor);
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}
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/* Initialize NOR control Interface */
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FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
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/* Initialize NOR timing Interface */
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FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
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/* Initialize NOR extended mode timing Interface */
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FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
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/* Enable the NORSRAM device */
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__FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
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/* Check the NOR controller state */
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hnor->State = HAL_NOR_STATE_READY;
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return HAL_OK;
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}
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/**
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* @brief Perform NOR memory De-Initialization sequence
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* @param hnor: pointer to a NOR_HandleTypeDef structure that contains
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* the configuration information for NOR module.
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
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{
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/* De-Initialize the low level hardware (MSP) */
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HAL_NOR_MspDeInit(hnor);
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/* Configure the NOR registers with their reset values */
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FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
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/* Update the NOR controller state */
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hnor->State = HAL_NOR_STATE_RESET;
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/* Release Lock */
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__HAL_UNLOCK(hnor);
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return HAL_OK;
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}
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/**
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* @brief NOR MSP Init
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* @param hnor: pointer to a NOR_HandleTypeDef structure that contains
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* the configuration information for NOR module.
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* @retval None
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*/
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__weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
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{
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/* NOTE : This function Should not be modified, when the callback is needed,
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the HAL_NOR_MspInit could be implemented in the user file
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*/
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}
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/**
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* @brief NOR MSP DeInit
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* @param hnor: pointer to a NOR_HandleTypeDef structure that contains
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* the configuration information for NOR module.
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* @retval None
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*/
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__weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
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{
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/* NOTE : This function Should not be modified, when the callback is needed,
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the HAL_NOR_MspDeInit could be implemented in the user file
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*/
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}
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/**
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* @brief NOR BSP Wait for Ready/Busy signal
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* @param hnor: pointer to a NOR_HandleTypeDef structure that contains
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* the configuration information for NOR module.
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* @param Timeout: Maximum timeout value
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* @retval None
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*/
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__weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
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{
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/* NOTE : This function Should not be modified, when the callback is needed,
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the HAL_NOR_BspWait could be implemented in the user file
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*/
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}
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/**
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* @}
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*/
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/** @defgroup NOR_Exported_Functions_Group2 Input and Output functions
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* @brief Input Output and memory control functions
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*
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@verbatim
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==============================================================================
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##### NOR Input and Output functions #####
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==============================================================================
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[..]
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This section provides functions allowing to use and control the NOR memory
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@endverbatim
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* @{
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*/
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/**
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* @brief Read NOR flash IDs
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* @param hnor: pointer to the NOR handle
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* @param pNOR_ID : pointer to NOR ID structure
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
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{
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uint32_t deviceAddress = 0;
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/* Process Locked */
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__HAL_LOCK(hnor);
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/* Check the NOR controller state */
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if(hnor->State == HAL_NOR_STATE_BUSY)
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{
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return HAL_BUSY;
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}
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/* Select the NOR device address */
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if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
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{
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deviceAddress = NOR_MEMORY_ADRESS1;
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}
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else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
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{
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deviceAddress = NOR_MEMORY_ADRESS2;
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}
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else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
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{
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deviceAddress = NOR_MEMORY_ADRESS3;
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}
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else /* FMC_NORSRAM_BANK4 */
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{
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deviceAddress = NOR_MEMORY_ADRESS4;
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}
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/* Update the NOR controller state */
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hnor->State = HAL_NOR_STATE_BUSY;
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/* Send read ID command */
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NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA);
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NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055);
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NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x0090);
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/* Read the NOR IDs */
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pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, MC_ADDRESS);
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pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, DEVICE_CODE1_ADDR);
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pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, DEVICE_CODE2_ADDR);
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pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, DEVICE_CODE3_ADDR);
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/* Check the NOR controller state */
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hnor->State = HAL_NOR_STATE_READY;
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/* Process unlocked */
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__HAL_UNLOCK(hnor);
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return HAL_OK;
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}
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/**
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* @brief Returns the NOR memory to Read mode.
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* @param hnor: pointer to the NOR handle
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
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{
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uint32_t deviceAddress = 0;
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/* Process Locked */
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__HAL_LOCK(hnor);
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/* Check the NOR controller state */
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if(hnor->State == HAL_NOR_STATE_BUSY)
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{
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return HAL_BUSY;
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}
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/* Select the NOR device address */
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if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
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{
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deviceAddress = NOR_MEMORY_ADRESS1;
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}
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else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
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{
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deviceAddress = NOR_MEMORY_ADRESS2;
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}
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else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
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{
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deviceAddress = NOR_MEMORY_ADRESS3;
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}
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else /* FMC_NORSRAM_BANK4 */
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{
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deviceAddress = NOR_MEMORY_ADRESS4;
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}
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NOR_WRITE(deviceAddress, 0x00F0);
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/* Check the NOR controller state */
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hnor->State = HAL_NOR_STATE_READY;
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/* Process unlocked */
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__HAL_UNLOCK(hnor);
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return HAL_OK;
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}
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/**
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* @brief Read data from NOR memory
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* @param hnor: pointer to the NOR handle
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* @param pAddress: pointer to Device address
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* @param pData : pointer to read data
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
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{
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uint32_t deviceAddress = 0;
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/* Process Locked */
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__HAL_LOCK(hnor);
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/* Check the NOR controller state */
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if(hnor->State == HAL_NOR_STATE_BUSY)
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{
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return HAL_BUSY;
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}
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/* Select the NOR device address */
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if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
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{
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deviceAddress = NOR_MEMORY_ADRESS1;
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}
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else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
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{
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deviceAddress = NOR_MEMORY_ADRESS2;
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}
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else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
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{
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deviceAddress = NOR_MEMORY_ADRESS3;
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}
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else /* FMC_NORSRAM_BANK4 */
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{
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deviceAddress = NOR_MEMORY_ADRESS4;
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}
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/* Update the NOR controller state */
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hnor->State = HAL_NOR_STATE_BUSY;
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/* Send read data command */
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NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x00555), 0x00AA);
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NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x002AA), 0x0055);
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NOR_WRITE(pAddress, 0x00F0);
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/* Read the data */
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*pData = *(__IO uint32_t *)pAddress;
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/* Check the NOR controller state */
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hnor->State = HAL_NOR_STATE_READY;
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/* Process unlocked */
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__HAL_UNLOCK(hnor);
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return HAL_OK;
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}
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/**
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* @brief Program data to NOR memory
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* @param hnor: pointer to the NOR handle
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* @param pAddress: Device address
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* @param pData : pointer to the data to write
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
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{
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uint32_t deviceAddress = 0;
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/* Process Locked */
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__HAL_LOCK(hnor);
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/* Check the NOR controller state */
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if(hnor->State == HAL_NOR_STATE_BUSY)
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{
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return HAL_BUSY;
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}
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/* Select the NOR device address */
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if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
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{
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deviceAddress = NOR_MEMORY_ADRESS1;
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}
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else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
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{
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deviceAddress = NOR_MEMORY_ADRESS2;
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}
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else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
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{
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deviceAddress = NOR_MEMORY_ADRESS3;
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}
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else /* FMC_NORSRAM_BANK4 */
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{
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deviceAddress = NOR_MEMORY_ADRESS4;
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}
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/* Update the NOR controller state */
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hnor->State = HAL_NOR_STATE_BUSY;
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/* Send program data command */
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NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA);
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NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055);
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NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00A0);
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/* Write the data */
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NOR_WRITE(pAddress, *pData);
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/* Check the NOR controller state */
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hnor->State = HAL_NOR_STATE_READY;
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/* Process unlocked */
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__HAL_UNLOCK(hnor);
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return HAL_OK;
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}
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/**
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* @brief Reads a half-word buffer from the NOR memory.
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* @param hnor: pointer to the NOR handle
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* @param uwAddress: NOR memory internal address to read from.
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* @param pData: pointer to the buffer that receives the data read from the
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* NOR memory.
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* @param uwBufferSize : number of Half word to read.
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
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{
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uint32_t deviceAddress = 0;
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/* Process Locked */
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__HAL_LOCK(hnor);
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/* Check the NOR controller state */
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if(hnor->State == HAL_NOR_STATE_BUSY)
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{
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return HAL_BUSY;
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}
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/* Select the NOR device address */
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if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
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{
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deviceAddress = NOR_MEMORY_ADRESS1;
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}
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else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
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{
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deviceAddress = NOR_MEMORY_ADRESS2;
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}
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else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
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{
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deviceAddress = NOR_MEMORY_ADRESS3;
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}
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else /* FMC_NORSRAM_BANK4 */
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{
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deviceAddress = NOR_MEMORY_ADRESS4;
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}
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/* Update the NOR controller state */
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hnor->State = HAL_NOR_STATE_BUSY;
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/* Send read data command */
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NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x00555), 0x00AA);
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NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x002AA), 0x0055);
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NOR_WRITE(uwAddress, 0x00F0);
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/* Read buffer */
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while( uwBufferSize > 0)
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{
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*pData++ = *(__IO uint16_t *)uwAddress;
|
|
uwAddress += 2;
|
|
uwBufferSize--;
|
|
}
|
|
|
|
/* Check the NOR controller state */
|
|
hnor->State = HAL_NOR_STATE_READY;
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hnor);
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Writes a half-word buffer to the NOR memory. This function must be used
|
|
only with S29GL128P NOR memory.
|
|
* @param hnor: pointer to the NOR handle
|
|
* @param uwAddress: NOR memory internal start write address
|
|
* @param pData: pointer to source data buffer.
|
|
* @param uwBufferSize: Size of the buffer to write
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
|
|
{
|
|
uint32_t lastloadedaddress = 0;
|
|
uint32_t currentaddress = 0;
|
|
uint32_t endaddress = 0;
|
|
uint32_t deviceAddress = 0;
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(hnor);
|
|
|
|
/* Check the NOR controller state */
|
|
if(hnor->State == HAL_NOR_STATE_BUSY)
|
|
{
|
|
return HAL_BUSY;
|
|
}
|
|
|
|
/* Select the NOR device address */
|
|
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
|
|
{
|
|
deviceAddress = NOR_MEMORY_ADRESS1;
|
|
}
|
|
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
|
|
{
|
|
deviceAddress = NOR_MEMORY_ADRESS2;
|
|
}
|
|
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
|
|
{
|
|
deviceAddress = NOR_MEMORY_ADRESS3;
|
|
}
|
|
else /* FMC_NORSRAM_BANK4 */
|
|
{
|
|
deviceAddress = NOR_MEMORY_ADRESS4;
|
|
}
|
|
|
|
/* Update the NOR controller state */
|
|
hnor->State = HAL_NOR_STATE_BUSY;
|
|
|
|
/* Initialize variables */
|
|
currentaddress = uwAddress;
|
|
endaddress = uwAddress + uwBufferSize - 1;
|
|
lastloadedaddress = uwAddress;
|
|
|
|
/* Issue unlock command sequence */
|
|
NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA);
|
|
NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055);
|
|
|
|
/* Write Buffer Load Command */
|
|
NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, uwAddress), 0x25);
|
|
NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, uwAddress), (uwBufferSize - 1));
|
|
|
|
/* Load Data into NOR Buffer */
|
|
while(currentaddress <= endaddress)
|
|
{
|
|
/* Store last loaded address & data value (for polling) */
|
|
lastloadedaddress = currentaddress;
|
|
|
|
NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, currentaddress), *pData++);
|
|
|
|
currentaddress += 1;
|
|
}
|
|
|
|
NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, lastloadedaddress), 0x29);
|
|
|
|
/* Check the NOR controller state */
|
|
hnor->State = HAL_NOR_STATE_READY;
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hnor);
|
|
|
|
return HAL_OK;
|
|
|
|
}
|
|
|
|
/**
|
|
* @brief Erase the specified block of the NOR memory
|
|
* @param hnor: pointer to the NOR handle
|
|
* @param BlockAddress : Block to erase address
|
|
* @param Address: Device address
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
|
|
{
|
|
uint32_t deviceAddress = 0;
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(hnor);
|
|
|
|
/* Check the NOR controller state */
|
|
if(hnor->State == HAL_NOR_STATE_BUSY)
|
|
{
|
|
return HAL_BUSY;
|
|
}
|
|
|
|
/* Select the NOR device address */
|
|
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
|
|
{
|
|
deviceAddress = NOR_MEMORY_ADRESS1;
|
|
}
|
|
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
|
|
{
|
|
deviceAddress = NOR_MEMORY_ADRESS2;
|
|
}
|
|
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
|
|
{
|
|
deviceAddress = NOR_MEMORY_ADRESS3;
|
|
}
|
|
else /* FMC_NORSRAM_BANK4 */
|
|
{
|
|
deviceAddress = NOR_MEMORY_ADRESS4;
|
|
}
|
|
|
|
/* Update the NOR controller state */
|
|
hnor->State = HAL_NOR_STATE_BUSY;
|
|
|
|
/* Send block erase command sequence */
|
|
NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA);
|
|
NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055);
|
|
NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x0080);
|
|
NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA);
|
|
NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055);
|
|
NOR_WRITE((uint32_t)(BlockAddress + Address), 0x30);
|
|
|
|
/* Check the NOR memory status and update the controller state */
|
|
hnor->State = HAL_NOR_STATE_READY;
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hnor);
|
|
|
|
return HAL_OK;
|
|
|
|
}
|
|
|
|
/**
|
|
* @brief Erase the entire NOR chip.
|
|
* @param hnor: pointer to the NOR handle
|
|
* @param Address : Device address
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
|
|
{
|
|
uint32_t deviceAddress = 0;
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(hnor);
|
|
|
|
/* Check the NOR controller state */
|
|
if(hnor->State == HAL_NOR_STATE_BUSY)
|
|
{
|
|
return HAL_BUSY;
|
|
}
|
|
|
|
/* Select the NOR device address */
|
|
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
|
|
{
|
|
deviceAddress = NOR_MEMORY_ADRESS1;
|
|
}
|
|
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
|
|
{
|
|
deviceAddress = NOR_MEMORY_ADRESS2;
|
|
}
|
|
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
|
|
{
|
|
deviceAddress = NOR_MEMORY_ADRESS3;
|
|
}
|
|
else /* FMC_NORSRAM_BANK4 */
|
|
{
|
|
deviceAddress = NOR_MEMORY_ADRESS4;
|
|
}
|
|
|
|
/* Update the NOR controller state */
|
|
hnor->State = HAL_NOR_STATE_BUSY;
|
|
|
|
/* Send NOR chip erase command sequence */
|
|
NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA);
|
|
NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055);
|
|
NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x0080);
|
|
NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA);
|
|
NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055);
|
|
NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x0010);
|
|
|
|
/* Check the NOR memory status and update the controller state */
|
|
hnor->State = HAL_NOR_STATE_READY;
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hnor);
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Read NOR flash CFI IDs
|
|
* @param hnor: pointer to the NOR handle
|
|
* @param pNOR_CFI : pointer to NOR CFI IDs structure
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
|
|
{
|
|
uint32_t deviceAddress = 0;
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(hnor);
|
|
|
|
/* Check the NOR controller state */
|
|
if(hnor->State == HAL_NOR_STATE_BUSY)
|
|
{
|
|
return HAL_BUSY;
|
|
}
|
|
|
|
/* Select the NOR device address */
|
|
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
|
|
{
|
|
deviceAddress = NOR_MEMORY_ADRESS1;
|
|
}
|
|
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
|
|
{
|
|
deviceAddress = NOR_MEMORY_ADRESS2;
|
|
}
|
|
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
|
|
{
|
|
deviceAddress = NOR_MEMORY_ADRESS3;
|
|
}
|
|
else /* FMC_NORSRAM_BANK4 */
|
|
{
|
|
deviceAddress = NOR_MEMORY_ADRESS4;
|
|
}
|
|
|
|
/* Update the NOR controller state */
|
|
hnor->State = HAL_NOR_STATE_BUSY;
|
|
|
|
/* Send read CFI query command */
|
|
NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0055), 0x0098);
|
|
|
|
/* read the NOR CFI information */
|
|
pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, CFI1_ADDRESS);
|
|
pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, CFI2_ADDRESS);
|
|
pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, CFI3_ADDRESS);
|
|
pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, CFI4_ADDRESS);
|
|
|
|
/* Check the NOR controller state */
|
|
hnor->State = HAL_NOR_STATE_READY;
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hnor);
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup NOR_Exported_Functions_Group3 Control functions
|
|
* @brief management functions
|
|
*
|
|
@verbatim
|
|
==============================================================================
|
|
##### NOR Control functions #####
|
|
==============================================================================
|
|
[..]
|
|
This subsection provides a set of functions allowing to control dynamically
|
|
the NOR interface.
|
|
|
|
@endverbatim
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Enables dynamically NOR write operation.
|
|
* @param hnor: pointer to the NOR handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
|
|
{
|
|
/* Process Locked */
|
|
__HAL_LOCK(hnor);
|
|
|
|
/* Enable write operation */
|
|
FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
|
|
|
|
/* Update the NOR controller state */
|
|
hnor->State = HAL_NOR_STATE_READY;
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hnor);
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Disables dynamically NOR write operation.
|
|
* @param hnor: pointer to the NOR handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
|
|
{
|
|
/* Process Locked */
|
|
__HAL_LOCK(hnor);
|
|
|
|
/* Update the SRAM controller state */
|
|
hnor->State = HAL_NOR_STATE_BUSY;
|
|
|
|
/* Disable write operation */
|
|
FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
|
|
|
|
/* Update the NOR controller state */
|
|
hnor->State = HAL_NOR_STATE_PROTECTED;
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hnor);
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup NOR_Exported_Functions_Group4 State functions
|
|
* @brief Peripheral State functions
|
|
*
|
|
@verbatim
|
|
==============================================================================
|
|
##### NOR State functions #####
|
|
==============================================================================
|
|
[..]
|
|
This subsection permits to get in run-time the status of the NOR controller
|
|
and the data flow.
|
|
|
|
@endverbatim
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief return the NOR controller state
|
|
* @param hnor: pointer to the NOR handle
|
|
* @retval NOR controller state
|
|
*/
|
|
HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
|
|
{
|
|
return hnor->State;
|
|
}
|
|
|
|
/**
|
|
* @brief Returns the NOR operation status.
|
|
* @param hnor: pointer to the NOR handle
|
|
* @param Address: Device address
|
|
* @param Timeout: NOR programming Timeout
|
|
* @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
|
|
* or HAL_NOR_STATUS_TIMEOUT
|
|
*/
|
|
HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
|
|
{
|
|
HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
|
|
uint16_t tmpSR1 = 0, tmpSR2 = 0;
|
|
uint32_t tickstart = 0;
|
|
|
|
/* Poll on NOR memory Ready/Busy signal ------------------------------------*/
|
|
HAL_NOR_MspWait(hnor, Timeout);
|
|
|
|
/* Get the NOR memory operation status -------------------------------------*/
|
|
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
while((status != HAL_NOR_STATUS_SUCCESS ) && (status != HAL_NOR_STATUS_TIMEOUT))
|
|
{
|
|
/* Check for the Timeout */
|
|
if(Timeout != HAL_MAX_DELAY)
|
|
{
|
|
if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
|
|
{
|
|
status = HAL_NOR_STATUS_TIMEOUT;
|
|
}
|
|
}
|
|
|
|
/* Read NOR status register (DQ6 and DQ5) */
|
|
tmpSR1 = *(__IO uint16_t *)Address;
|
|
tmpSR2 = *(__IO uint16_t *)Address;
|
|
|
|
/* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
|
|
if((tmpSR1 & 0x0040) == (tmpSR2 & 0x0040))
|
|
{
|
|
return HAL_NOR_STATUS_SUCCESS ;
|
|
}
|
|
|
|
if((tmpSR1 & 0x0020) == 0x0020)
|
|
{
|
|
status = HAL_NOR_STATUS_ONGOING;
|
|
}
|
|
|
|
tmpSR1 = *(__IO uint16_t *)Address;
|
|
tmpSR2 = *(__IO uint16_t *)Address;
|
|
|
|
/* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
|
|
if((tmpSR1 & 0x0040) == (tmpSR2 & 0x0040))
|
|
{
|
|
return HAL_NOR_STATUS_SUCCESS;
|
|
}
|
|
if((tmpSR1 & 0x0020) == 0x0020)
|
|
{
|
|
return HAL_NOR_STATUS_ERROR;
|
|
}
|
|
}
|
|
|
|
/* Return the operation status */
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
|
|
#endif /* HAL_NOR_MODULE_ENABLED */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|