module simple_filter (input CLK, input RESET, input IN, output OUT);

  reg out;
  parameter FLT_CONST = 3'd7; //  IF MODIFY THIS PLEASE MODIFY COUNTER!
  reg [2:0] counter;

  always@(posedge CLK or negedge RESET) begin
    if (RESET == 0)  begin
      counter = 0;
      out = 1;
    end
    else begin
      if (counter != 0)	begin
  			counter = counter - 1;
  			if (counter == 0)	begin
  				if (out != IN)
  					out = IN;
  			end
  		end
  		else	begin
  			if (out != IN)
  				counter = FLT_CONST;
  		end
    end
  end

  assign OUT = out;

endmodule
