module ram(input clk, wen, input [8:0] waddr, input [7:0] wdata, input [8:0] raddr, output [7:0] rdata);
  reg [7:0] mem [511:0];
  reg [7:0] r_data;
  reg [7:0] w_data;
  reg [7:0] w_addr;
  reg last_we;
  initial mem[0] = 255;
  always @(posedge clk) begin
    if (wen)  begin //((last_we == 0) && (wen == 1)) begin
      //w_data = wdata;
      //w_addr = addr;
      //mem[w_addr] <= w_data;
      mem[waddr] <= wdata;
    end
    r_data <= mem[raddr];
    //last_we = wen;
  end

  assign rdata = r_data;

endmodule
