From 90fc7379fd1ca04a418c34868836e45ca19c7875 Mon Sep 17 00:00:00 2001 From: Ivan Olenichev Date: Wed, 24 Oct 2018 18:58:40 +0600 Subject: [PATCH] Firmware emulates little i2c energy-dependend memory --- i2c_flash/.sconsign.dblite | Bin 0 -> 4362 bytes i2c_flash/apio.ini | 3 + i2c_flash/hardware.asc | 5969 ++++++++++++++++++++++++++++++++++++ i2c_flash/hardware.bin | Bin 0 -> 32220 bytes i2c_flash/hardware.blif | 1161 +++++++ i2c_flash/i2c_slave.v | 173 ++ i2c_flash/inouts.pcf | 26 + i2c_flash/ram.v | 20 + i2c_flash/top.v | 112 + i2c_flash/uart.v | 48 + 10 files changed, 7512 insertions(+) create mode 100644 i2c_flash/.sconsign.dblite create mode 100644 i2c_flash/apio.ini create mode 100644 i2c_flash/hardware.asc create mode 100644 i2c_flash/hardware.bin create mode 100644 i2c_flash/hardware.blif create mode 100644 i2c_flash/i2c_slave.v create mode 100644 i2c_flash/inouts.pcf create mode 100644 i2c_flash/ram.v create mode 100644 i2c_flash/top.v create mode 100644 i2c_flash/uart.v diff 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z_XEPKIc(Co^vAPQiGp6LAQ$mEF@WG4R*nUM+xdRbvGqi0I>Z#=|B-SsY**!ij>#hs*XfFawTI2X57I2w%SeXbriSUwvo&y= z*j*#<^FLwnaNooPs&J~K20<AfA^nwaR)JuKJbD2Dtn z@96wbd}l`Z`l26i)fhUt{b61r3T%2NG&!Y-_AG&mi=KV{4oy;@QvoLcUX*k<`G&&m zV{Ody~od_)42<*VC)6O!maOb}>@=gR0fnL$s z4|Ect6M+REfzEzl!KXkc0G$Z*I@W&R+G{%j=|rFtfrS`>&VFDa&U$Ceod_f%(Cb?J jfrO+(bRy7+z=DZDXFsrDrn)oGP6V=1 - DATA TRANSMISSION +// RECEIVED BYTES MUST READ WHEN WR POSEDGE, ADRESS NOT READING ###AND BYTE COUNTER >=1 (BYTE COUNTER = 0 - ADRESS) +// BYTES TO TRANSMIT MUST WRITE WHEN WR POSEDGE, BYTE COUNTER CAN BE ZERO +// (FIRST BYTE TRANSMITTED AFTER ADRESS). +// LAST BYTE HAS NO WR ####BUT LAST BYTE NOT TRANSMITTED (DECAUSE MASTER STOPS TRANSMIT) + + parameter I2C_ADRESS = 7'h34; + parameter MAX_I2C_TRANSACTION_EXP2 = 9; // !!! - FOR LIMIT BYTES TO TX/RX (WITH ADRESS) + + reg SDA_IN, SDA_DIR, SDA_OUT; + initial begin + SDA_OUT = 0; + end + + reg SCLD, SDAD; + + reg SCL_LAST, SDA_LAST; + reg i2c_state_machine; + initial begin + SCL_LAST = 1; SDA_LAST = 1; i2c_state_machine = 0; + end + reg is_read; + reg [3:0] i2c_bit_counter; + //reg [7:0] received_byte; + reg [7:0] byte_to_transmit; + reg [(MAX_I2C_TRANSACTION_EXP2-1):0] byte_counter; + //reg is_for_me; + reg is_ack; + reg wr;//reg ack_master_ctrl; + + // FILTER + reg SCLF, SDAF; + reg [3:0] scl_cnt, sda_cnt; + + always@(negedge CLK) begin + SCLF = SCL; + SDAF = SDA_IN; + end + + always@(posedge CLK) begin + if (scl_cnt != 0) begin + scl_cnt = scl_cnt - 1; + if (scl_cnt == 0) begin + if (SCLD != SCLF) + SCLD = SCLF; + end + end + else begin + if (SCLD != SCLF) + scl_cnt = 3'd7; + end + if (sda_cnt != 0) begin + sda_cnt = sda_cnt - 1; + if (sda_cnt == 0) begin + if (SDAD != SDAF) + SDAD = SDAF; + end + end + else begin + if (SDAD != SDAF) + sda_cnt = 3'd7; + end + // END OF FILTER + + //SDA_IN = SDA; // FOR IVERILOG + if ((SDAD == 0) && (SDA_LAST == 1) && (SCLD == 1)) begin + i2c_state_machine = 1; + i2c_bit_counter = 4'd8; + byte_counter = 9'd0; + is_read = 0; + //is_for_me = 1; // RESETS TO ZERO WHEN ADRESS CHECKING + SDA_DIR = 0; + is_ack = 0; + //ack_master_ctrl = 1; + wr = 0; + end + if ((SDAD == 1) && (SDA_LAST == 0) && (SCLD == 1)) begin + i2c_state_machine = 0; + SDA_DIR = 0; + wr = 0; + end + if (i2c_state_machine/* && is_for_me*/) begin + if (!is_read) begin + if (i2c_bit_counter > 0) begin + if ((SCL_LAST == 0) && (SCLD == 1)) begin + RECEIVED_BYTE[i2c_bit_counter-1] = SDAD; + i2c_bit_counter = i2c_bit_counter - 1; + end + end + else begin + if ((SCL_LAST == 1) && (SCLD == 0) && (is_ack == 0)) begin + if (byte_counter == 0) begin + if (RECEIVED_BYTE[7:1] != I2C_ADRESS) + i2c_state_machine = 0; //is_for_me = 0; + is_read = RECEIVED_BYTE[0]; + end + else begin + // EMIT SIGNAL OF BYTE RECEIVING + end + if (byte_counter != (2^MAX_I2C_TRANSACTION_EXP2 - 1)) + byte_counter = byte_counter + 1; + SDA_DIR = i2c_state_machine; //is_for_me; + is_ack = i2c_state_machine; //1; + //if (is_read) begin + // i2c_bit_counter = 8; + //end + end + else if ((SCL_LAST == 0) && (SCLD == 1) && (is_ack == 1) && (byte_counter > 1)) + wr = 1; + else if ((SCL_LAST == 1) && (SCLD == 0) && (is_ack == 1)) begin + is_ack = 0; + SDA_DIR = 0; + i2c_bit_counter = 4'd8; + wr = 0; + end + end + end + else begin // IS_READ + if (i2c_bit_counter > 0) begin + if ((SCL_LAST == 1) && (SCLD == 0)) begin + wr = 0; + SDA_DIR = (BYTE_TO_TRANSMIT[i2c_bit_counter-1] ^ 1) /*& is_for_me & ack_master_ctrl*/; + i2c_bit_counter = i2c_bit_counter - 1; + is_ack = 0; + end + end + else begin + if ((SCL_LAST == 1) && (SCLD == 0) && (is_ack == 0)) begin + SDA_DIR = 0; + is_ack = 1; + end + else if ((SCL_LAST == 0) && (SCLD == 1) && (is_ack == 1)) begin + i2c_bit_counter = 8; + i2c_state_machine = (SDAD ^ 1) | SDA_DIR; //ack_master_ctrl = SDAD+1; // MAYBE TRANSMIT BYTE REPEAT + wr = (SDAD ^ 1) | SDA_DIR; + if (byte_counter != (2^MAX_I2C_TRANSACTION_EXP2 - 1)) + byte_counter = byte_counter + 1; + // EMIT SIGNAL OF BYTE TO TRANSMIT + end + end + end + end + SCL_LAST <= SCLD; + SDA_LAST <= SDAD; + //SDA_OUT = (SDA_DIR ^ 1) & SDA; // FOR IVERILOG + end + + assign IS_TRANSMISSION = i2c_state_machine; + //assign SDA = SDA_DIR ? 1'b0 : 1'bz; + assign IS_ACK = is_ack; + assign IS_READ = is_read; + assign WR = wr;//assign ACK_MASTER_CTRL = ack_master_ctrl; + //assign RECEIVED_BYTE = received_byte; + //assign BYTE_TO_TRANSMIT = byte_to_transmit; + assign COUNTER = byte_counter; + + SB_IO #( + .PIN_TYPE(6'b 1010_01), + .PULLUP(1'b 0) + ) led_io ( + .PACKAGE_PIN(SDA), + .OUTPUT_ENABLE(SDA_DIR), + .D_OUT_0(SDA_OUT), + .D_IN_0(SDA_IN) + ); + +endmodule diff --git a/i2c_flash/inouts.pcf b/i2c_flash/inouts.pcf new file mode 100644 index 0000000..b1d92eb --- /dev/null +++ b/i2c_flash/inouts.pcf @@ -0,0 +1,26 @@ +set_io LED1 99 +set_io LED2 98 +set_io LED3 97 +set_io LED4 96 +set_io LED5 95 + +#set_io SCLM 78 # J2, 1 +#set_io SDAM 87 # J2, 7 +set_io ACK 81 # J2, 4 + +#set_io SCLTGL01 80 # J2, 3 +#set_io SDAOUTM 79 # J2, 2 +#set_io SCLTGL 79 # J2, 8 + +set_io CLK 21 +set_io SCL 90 # J2, 9 +set_io SDA 91 # J2, 10 + # GND - J2, 11 + +set_io COM_TX 8 +set_io COM_RX 9 +set_io COM_DCD 1 +set_io COM_DSR 2 +set_io COM_RTS 4 # IS CTS IN FT2232 SIDE + +#set_io SDA_CTRL 88 # J2, 8 diff --git a/i2c_flash/ram.v b/i2c_flash/ram.v new file mode 100644 index 0000000..bc09520 --- /dev/null +++ b/i2c_flash/ram.v @@ -0,0 +1,20 @@ +module ram(input clk, wen, input [8:0] addr, input [7:0] wdata, output [7:0] rdata); + reg [7:0] mem [0:255]; + reg [7:0] r_data; + reg [7:0] w_data; + reg [7:0] w_addr; + reg last_we; + initial mem[0] = 255; + always @(posedge clk) begin + if ((last_we == 0) && (wen == 1)) begin + w_data = wdata; + w_addr = addr; + mem[w_addr] <= w_data; + end + r_data <= mem[addr]; + last_we = wen; + end + + assign rdata = r_data; + +endmodule diff --git a/i2c_flash/top.v b/i2c_flash/top.v new file mode 100644 index 0000000..0b92f5c --- /dev/null +++ b/i2c_flash/top.v @@ -0,0 +1,112 @@ + +module top (input CLK, output LED1, LED2, LED3, LED4, LED5, + input SCL, inout SDA, output ACK, + input COM_RX, output COM_TX, COM_DCD, COM_DSR, COM_RTS); + + reg [7:0] I2C_TX; // TRANSMITTED TO MASTER + initial begin + I2C_TX = 22; + end + wire [7:0] I2C_RX; // RECEIVED FROM MASTER + wire [7:0] RAM_RD; + wire I2C_TRANS, I2C_READ, I2C_ACK, I2C_ACK_MSTR_CTRL, I2C_WR; + wire [9:0] I2C_COUNTER; + i2c_slave I2C (CLK, SCL, SDA, I2C_TRANS, I2C_READ, I2C_ACK, I2C_WR, //I2C_ACK_MSTR_CTRL, + I2C_RX, I2C_TX, I2C_COUNTER); + + reg UART_WR, UART_DTR, UART_RTS, UART_DCD; + reg [7:0] UART_TX_DATA; + wire UART_ACTIVE, UART_TX_LINE; + reg [23:0] uart_counter; + initial begin + UART_WR = 0; + UART_TX = 1; + UART_RTS = 1; + UART_DTR = 0; + UART_DCD = 0; + end + uart UART (CLK, UART_WR, UART_TX_DATA, UART_ACTIVE, UART_TX_LINE); + + reg wr_old; + reg [7:0] ram_adress; + reg RAM_W; + initial begin + ram_adress = 0; + RAM_W = 0; + end + ram RAM (CLK, RAM_W, ram_adress, I2C_RX, RAM_RD); + + + + always @ (posedge CLK) begin + if ((wr_old == 0) && (I2C_WR == 1) && I2C_READ) begin + //I2C_TX = I2C_TX + 5; + // READ + I2C_TX = RAM_RD; // READ FROM CURRENT ADRESS + //ram_adress <= ram_adress + 1; // AND INCREMENT ADRESS (ASSIGNED IN THE NEXT TACT) + UART_WR = 1; + UART_TX_DATA = I2C_TX; + end + else if ((wr_old == 0) && (I2C_WR == 1) && (I2C_READ == 0)) begin + // RAM MODULE WRITES TO RAM IN THE CURRENT ADRESS + if (I2C_COUNTER == 2) + ram_adress = I2C_RX; + else begin + RAM_W = 1; + //ram_adress <= ram_adress + 1; // ONLY INCREMENT ADRESS IN THE NEXT TACT + end + UART_WR = 1; + UART_TX_DATA = I2C_RX; + end + else if ((wr_old == 1) && (I2C_WR == 0)) begin + RAM_W = 0; + UART_WR = 0; + if ((I2C_COUNTER != 2) || (I2C_READ == 1)) + ram_adress <= ram_adress + 1; // ONLY INCREMENT ADRESS IN THE NEXT TACT + end + wr_old = I2C_WR; +/* + uart_counter = uart_counter + 1; + if (uart_counter == 12000000) begin + uart_counter = 0; + UART_TX_DATA = UART_TX_DATA + 1; + UART_WR = 1; + UART_RTS = UART_RTS ^ 1; + if (UART_RTS) + UART_DTR = UART_DTR ^ 1; + if (UART_DTR == 1) + UART_DCD = UART_DCD ^ 1; + end + else if (uart_counter == 5) + UART_WR = 0;*/ + end + + assign I2C_W = I2C_WR & (I2C_READ ^ 1); + + assign LED5 = I2C_TRANS; + //assign LED5 = COM_RX; + assign LED1 = ram_adress[0];//I2C_RX[0]; + assign LED2 = ram_adress[1]; + assign LED3 = ram_adress[2]; + assign LED4 = ram_adress[3]; + assign ACK = I2C_READ;//I2C_WR; //I2C_ACK; + + assign COM_TX = UART_TX_LINE;//COM_RX; + //assign COM_RTS = I2C_READ; + assign COM_RTS = I2C_READ;//UART_RTS; + assign COM_DSR = I2C_TRANS | UART_ACTIVE;//UART_DTR; + //assign COM_DCD = UART_DCD; + +/* reg [24:0] counter; + + always @ (posedge CLK) begin + counter = counter + 1; + end + + assign LED1 = ~counter[24] & ~counter[23]; + assign LED2 = ~counter[24] & counter[23]; + assign LED3 = counter[24] & ~counter[23]; + assign LED4 = counter[24] & counter[23]; + assign LED5 = counter[23];*/ + +endmodule //top diff --git a/i2c_flash/uart.v b/i2c_flash/uart.v new file mode 100644 index 0000000..33abf9e --- /dev/null +++ b/i2c_flash/uart.v @@ -0,0 +1,48 @@ + +module uart ( input CLK, input TX_SIGNAL, input [7:0] TX_BYTE, + output TX_ACTIVITY, output TX_LINE); + +parameter CLK_DIV = 13; +reg TX_sig_last; +reg [3:0] tx_bit_counter; +reg [3:0] tx_clk_counter; // MUST CONTAIN CLK DIV +reg [7:0] tx_data; +reg tx_activity; +reg tx_line; +initial begin + TX_sig_last = 0; + tx_line = 1; +end + +always @ (posedge CLK) begin + if (tx_activity) begin + tx_clk_counter = tx_clk_counter - 1; + if (tx_clk_counter == 0) begin + tx_clk_counter = CLK_DIV; + if (tx_bit_counter == 0) + tx_activity = 0; + else begin + tx_bit_counter = tx_bit_counter - 1; + if (tx_bit_counter > 0) + tx_line = tx_data[8-tx_bit_counter]; + else + tx_line = 1; // STOP_BIT + end + end + end + else begin + if ((TX_SIGNAL == 1) && (TX_sig_last == 0)) begin + tx_data = TX_BYTE; + tx_activity = 1; + tx_bit_counter = 9; // NO PARITY, STOP 1 BIT + tx_clk_counter = CLK_DIV; + tx_line = 0; // START BIT + end + end + TX_sig_last = TX_SIGNAL; +end + +assign TX_LINE = tx_line; +assign TX_ACTIVITY = tx_activity; + +endmodule