.device 1k
.io_tile 1 0
000000000000000010
000111010000000000
000000000000000000
000000000000000001
000000000011000001
000000000001000000
001100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000010
000000000001000000
000000000000000000
000001110000000001
000000000000000001
000000000000000000
.io_tile 2 0
000000000000000010
000000000000000000
000000000000000000
000000000000000001
000001011010000001
000000000001000000
001100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.io_tile 3 0
000000000000000000
000000000000000000
000000000000010000
000000000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.io_tile 4 0
000000000000000000
000100000000000000
100000000000000000
000000000000000001
000000000000000000
000000000000000000
001000000000000000
000000000000000000
000000000000000000
100000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000001
000000000000000000
000000000000000000
.io_tile 5 0
000000000000100000
000100000000000000
100000000000000000
000000000000000001
000000000000000000
000000000000000000
001000000000010000
000000000000000000
000000000000000000
100000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000001
000000000000000000
000000000000000000
.io_tile 6 0
000001110000011000
000100001000000000
000000000000010000
000000000000000000
000000000000000100
000000000000000000
001000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.io_tile 7 0
000000000000000000
000100000000001000
000000000000000000
000000000000000000
000000000000000100
000000000000001100
000000000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
010000000000000000
000000000000000000
000001110000000001
000000000000000000
000000000000000000
.io_tile 8 0
000000000000000000
000100000000001000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
010000000000000000
000000000000000000
000000000000000001
000000000000000000
000000000000000000
.io_tile 9 0
000000000000000000
000100000000000000
000000000000010000
010000000000000001
000000000000000000
000000000000000000
001000000000000000
000000000000000000
000000000000000000
010000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000001
000000000000000000
000000000000000000
.io_tile 10 0
000000000001000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.io_tile 11 0
000000000000000000
000000000001000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000100000000001000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.io_tile 12 0
000000000000000000
000000000001000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000100000000001000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.io_tile 0 1
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.logic_tile 1 1
100000000000000000000000001000000000000000000101000001
000000000000000000000000000001000000000010000000000000
101000000000001000000000000000000000000000000000000000
100000000000001111000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000001111000000000000000000000000000000000000
000000000000000000010000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000001000000000000000000110000000
000000000000000000000000000101000000000010000000000110
.logic_tile 2 1
000000000000000000000000000000000000000000000000000000
000000000000000111000000000000000000000000000000000000
101000000000000111100000010000000000000000000000000000
100000000000000000000010000000000000000000000000000000
010000000000000011000010000001100000000000000010000100
110000000000000111000000000001000000000001000000000001
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000010100000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000001101000000000001100100000000
000000000000000000000000001001001010000010100000000001
010000001110000000000000000000000000000000000000000000
100000000000000000000000000000000000000000000000000000
.ramb_tile 3 1
000000001110000000000000000000000000000000
000000010001010000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000001000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000010000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
.logic_tile 4 1
001000000000000001000000000101000000000000001000000000
000000000000000001100000000000100000000000000000001000
000000000000001000000111100011000000000000001000000000
000000000000001111000100000000000000000000000000000000
000000000000000000000010000101100000000000001000000000
000000000000000000000110010000000000000000000000000000
000000000000001000000000000101000000000000001000000000
000000000000000111000000000000100000000000000000000000
000000000000000000000000000001100000000000001000000000
000000000000001111000000000000100000000000000000000000
000000000000000000000000000001000000000000001000000000
000000000000000000000000000000001111000000000000000000
000000000000000000000000000001000000000000001000000000
000000000000000000000010000000000000000000000000000000
000000000000000000000000000001100000000000001000000000
000010000000000000000000000000000000000000000000000000
.logic_tile 5 1
000000000000000000000000000011000001000000000000000000
000000000000000000000000001111101011000000100000000000
101001000001001000000010101001100001000000010001000000
100010000000000001000100000111001001000000000000000000
010000000100000000000010000000000000000000000000000000
000000000000000000000100000000000000000000000000000000
000000000100000000000110000101000001000000000001000000
000000000000001001000000000011101010000010000000000000
000000000000000111000111110011000001000000000000000000
000000000000000000100110101011101011000000100000000000
000000000000000000000000000101100000000010000000000000
000000000000000000000000001011100000000000000000000000
000000000000000000000010100000000000000000000000000000
000000000000000000000100000000000000000000000000000000
010000000000000000000000000101100000000000000100000000
000000000000001101000000001011100000000011000000000101
.logic_tile 6 1
000000000000001111100000010111101101001000000001000001
000000100000000101100010000001111011000000000000000001
000000000000000101100010000000000000000000000000000000
000010000000000000000100000000000000000000000000000000
000000000000001111100000011011000000000000000000000000
000000000000000101100010001101100000000010000000000000
000000000000000101100010000011001101000001000000000100
000000001010000000000100000101011001000000000010000000
000000000000000000000010000000000000000000000000000000
000000000000001101000110010000000000000000000000000000
000000000000000000000000000011101001100000000000100001
000000000000000000000010110001111000000000000000000001
000000000000000000000000000111101011100000000001000000
000000000000000000000000000101111010000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000010110000000000000000000000000000
.logic_tile 7 1
000001000000100001100000011001000000000001000000000000
000000000000000000000010000001000000000011000000000000
101000000001001001100000000101101100001100110000000000
100000000000000001000000000000100000110011000000000000
010000000000101000000110010001101110001100110000000000
110000000000010001000011100000011100110011000000000000
000000000000001001100110011111100000000011100000000000
000000100000100001000010000101101011000001110000000000
000001000100001000000000011101100001000010000000000000
000000000000000011000010101101101010000000000000000000
000000100000000000000000001001000000000001000100000000
000000000000000000000000000101100000000011000100000000
000000000000000000000000000000000000000000000100000000
000000000000000000000010101011000000000010000100000010
010000000110000000000110100000000000000000000100000000
100000000000000000000000000101000000000010000100000000
.logic_tile 8 1
000000000000001111100011000111100000000000000000000000
000000000000000101000010010001000000000001000000000001
101000000001010011100111110111111110010100000000000000
100000000000100000100110110001011010110000000000000000
010000000000001001100000011001100000000011000000000000
010000000000001111000010101101000000000000000000000000
000000000000000001100110111111011010011100000000000000
000000000000000011000010001101001001101000000000000000
000000000000000000000000010101011001000100100000000000
000000000000000000000010001011111001000000000000000000
000000000000000000000111001101000000000010000000000000
000000000000000000000000000101000000000000000000000000
000000000010000111000110100011100000000010000000000000
000010000000000000000000001111100000000000000000000000
010010000000001111100111001000000000000000000101000010
100001000000000001000000001001000000000010001100000000
.logic_tile 9 1
000000001110001111000011000111011101000000010000000000
000000000000000111000011011011011111000000000000000010
000001000000001111100111110000000000000000000000000000
000011100000000001000111000000000000000000000000000000
000000000000000001000011000111111000000001010000000000
000000000000000000000011011111101100000010010000000000
000000000000000001000000001001101111101000000000000000
000100000000000111100010011001101010001100000000000000
000011000000000011100000001011100001000000010000100000
000000000000001111000011111011001010000000000000000000
001000000000001111100111000101011100000110100001000000
000000000000001011000011111111101011001111110000000000
000000000000001001000010010011001000010100100001000000
000000000000001011100110000001011001101000100000000000
000010000000000000000011100101011001001001010001000000
000111100000000000000110000001001011010110100000000000
.ramb_tile 10 1
000000000000000000000000000000000000000000
000000010000000000000000000000000000000000
000010100000000000000000000000000000000000
000001000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
001000000100000000000000000000000000000000
000000100000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000010000000000000000000000000000
000000000000100000000000000000000000000000
.logic_tile 11 1
000000000010000111000111100001001100101010100000000000
000000000000000111100111100001001100011010010001000000
101000000000000000000110010111100000000000000000000010
100000000000000000000010111101000000000010000000000000
010000100000000000000111000000000000000000000000000000
110001000000000011000011000000000000000000000000000000
000001000000000000000000000111100001000000010010000001
000000000000001011000010111011101011000010000000000000
000000001000001011100111001101001001000000110000100000
000000000000001011100100001011011001000000010000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000011110000000000000000000000000000
000000001010000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
010000001100000101100111101001000001000001100100000100
100000000000000000000100001001101010000010100000000000
.logic_tile 12 1
000000000000000000000000010011100000000000001000000000
000000000000000000000011110000100000000000000000001000
000101000000000000000111100001000000000000001000000000
000000100000000000000100000000101111000000000000000000
000000000000000000000000000111100000000000001000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000011100000000000001000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000001100000000000001000000000
000000000000000000000000000000100000000000000000000000
000000000000000000000011100000001000111100000000000000
000000000000000011000100000000000000111100000000000000
000000000000000000000000010000000000000000000000000000
000000000000000000000010110000000000000000000000000000
000000000000001000000000000000000000000000000000000000
000000000000000111000000000000000000000000000000000000
.io_tile 13 1
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.io_tile 0 2
000000000000000000
000000000000000000
000000000000000000
000000000000011000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.logic_tile 1 2
000000000010000000000000000011100000000000001000000000
000000000000000000000000000000000000000000000000001000
000000000000001000000000000001100000000000001000000000
000000000000000011000000000000001011000000000000000000
000000000000000000000000000000000000000000001000000000
000000000110000000000010010000001110000000000000000000
000000000000000000000000000000000000000000001000000000
000000000000000000000000000000001100000000000000000000
000000000000100011000000000000000000000000001000000000
000000000001000111100000000000001100000000000000000000
000000000000000001000000000000000000000000001000000000
000000000000000000000000000000001110000000000000000000
000000100000000101000000000000001000111100000000000001
000000000000001011000000000000000000111100000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.logic_tile 2 2
000000000000001000000000000011000000000000001000000000
000000000000001111000000000000000000000000000000001000
000000000000001111100000000001100000000000001000000000
010000000000000111100000000000001110000000000000000000
000000000001000101000000000000000000000000001000000000
000000000000000000100000000000001111000000000000000000
000000000000000000000000000000000000000000001000000000
000000000000000000000000000000001111000000000000000000
000000000000100011000000000000000000000000001000000000
000000000001010000100000000000001010000000000000000000
000000000000000000000000000000000001000000001000000000
000000000000000000000000000000001111000000000000000000
000000001110001000000011010000000000000000001000000000
000000000000001011000111000000001000000000000000000000
000000000000000000000000000000000001000000001000000000
000000000000000000000011100000001000000000000000000000
.ramt_tile 3 2
000000000000100000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000010000000000000000000000000000000000000
000001000000000000000000000000000000000000
000000000000100000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
.logic_tile 4 2
000000000000000001000010000000001000111100000001000000
000000000000000000000010000000000000111100000000010000
000000000000000001100111100101011010000000000001000000
000000000000001101000010010001111110001000000000000000
000000000000000001000010000001111101100000000010000000
000000000000000000100100000111011001000000000000000000
000000000000000000000010001011100000000001000000000000
000000000000000000000110011101100000000000000000000000
000000000000000011100000001001101000000001000000000000
000010000000000011000000001001111010000000000000000001
000000000110000011000110011001100001000000000000000000
000000000000000000000010001001001100000000100000000000
000000000000000101100000000001001110001000000000000000
000000000000000011000011000101111100000000000000000000
000000000000000000000000000101001000000000000000000000
000000000000000000000000000001111100100000000000000000
.logic_tile 5 2
000000000000000001000110111011111101100000000000000000
000000000000000000100010000011011101000000000000000000
000000000000001101000110001011000000000000000000000000
000000000000000101000000000001101101000010000000000000
000001000000000000000000000001001100000000010000000000
000000000000000000000000000011011101000000000000000000
000010100000000001100000000101100001000000010001000000
000000000000010000000000001001001001000000000000100000
000000000000001000000010101001100000000000010000000100
000000001110000111000110110001101001000000000000000000
000000000000000101000010101011000000000000010000000000
000000000000001101100110110001101101000000000000000000
000000000000000000000000001011111101000000000000000000
000000000000000000000000000011011101000001000000000000
000000000000000101000010101111111111000000000000000000
000000000000001101100110110111011111000000100000000000
.logic_tile 6 2
000000000110001000000000000011101011100000000001000001
000000000000000101000011100101101001000000000000000000
101000000001010001000000001011100001000000000000000000
100010100000001111100011000011101111000000100000000000
110000000000001001110000011101101010100000000010000001
110000000000000101000010101111111000000000000000000001
000000000000000000000000000000000000000000000100100100
000000001100000000000011001111000000000010000000000000
000000000000000000000011000000000000000000000100000100
000000000001000000000000001001000000000010000000000000
000000000000000001100111001000000000000000000100000010
000000000000000000100011110001000000000010000000000000
000000000000000000000010100000000000000000000000000000
000010000000000000000010010000000000000000000000000000
010010000000000000000111000000000000000000000100000010
010001000000000000000010001011000000000010000000000101
.logic_tile 7 2
000000000000000101000111110001011010000011100001000000
000000000000000000100111101001011101000001010000000000
101000000000001111100000000000000000000000000000000000
100000000000001111100000000000000000000000000000000000
010000001100000000000010101101100000000000000000000000
110000000000000000000100001101000000000010000000000000
000001000000001000000111010111001101000010110001000000
000010100000000001000110001111001000000011010000000000
000000000000001000000000010000000000001100110000000000
000000000000001001000010000000000000110011000000000000
000010100000000000000000000111000000001100110000000000
000001001110000001000000000000100000110011000000000000
000010000000000001000011101111111000000001000000001000
000001000000000000100110000011000000000100000000000000
010000000000000000000000000000000000000000000100000010
010000000000001001000000001001000000000010000000000001
.logic_tile 8 2
000000000000000101100110010011100000000000001000000000
000000000000000000100011110000100000000000000000001000
000000000000001001100110000011100001000000001000000000
000000000000000001000010010000101111000000000000000000
001000000000001111100010100000001000111100000000000000
000000000000000111100010000000000000111100000000000000
000000001000000011000000000111001010101000000000000000
000000000000000011100000000101101100001100000000000000
000000000000000111000000001101100000000010000000000000
000000000000000000100000001001000000000000000000000000
000000000000000000000110010101100000000010000000000000
000000000000000000000110011001000000000000000000000000
000000000000000000000010001001111000000011100010000010
000000000000000000000100000001011011000001010010000001
000000000000000000000000010111001000101000000000000000
000000000000000000000011101101111000001100000000000000
.logic_tile 9 2
000000001101011000000111110101111011000001010000000010
000000000000001111000110001001011000000011100000000000
101000000001001111100111101101000000000010000000000000
100000000110000001100111111001000000000000000001000000
110000000001000111000000001001100001000000010000000000
100000000010000000000011010011001111000010000000000100
000110100000000011100000000001000001000001000000000000
000101000000000011000011011101101011000011000000000000
000001000000000000000000001011100000000000000000000000
000010000000000000000000000011000000000010000000000000
000100000001000001100000000001100000001100110000000000
000000100000001111000000000000100000110011000000000000
000000100000000000000000000000000000000000000100000000
000000000000000000000000000001000000000010000000000010
010000000001000000000011000000000000000000000100000000
110000000000000000000100001001000000000010000000100000
.ramt_tile 10 2
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000001000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000010000000000000000000000000000000
001000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000001000000000000000000000000000000000000
000010100000000000000000000000000000000000
001000000001000000010000000000000000000000
000000000000100000000000000000000000000000
000000000000000000000000000000000000000000
000000000001000000000000000000000000000000
.logic_tile 11 2
100000000000001000000000000000000000000000000100000000
000000000000000011000000000111000000000010000000100000
101001000000000000000000000000000000000000000000000000
100000101000000000000010010000000000000000000000000000
000000000001010000000000001000000000000000000100000100
000000000000000001000000001001000000000010000000100001
000000000000011000000000000000000000000000000110000000
000000000000001011000000000101000000000010000000000001
000000000000000000000000000000000000000000000000000000
000000001110000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000111000000000000000000000000000111000000
000000000000000000100000000001000000000010000000000000
000000000000000000000000001000000000000000000101000000
000000000000000000000000000101000000000010000000100010
.logic_tile 12 2
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000001000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000001100100000000000000000000000000000000000000000
000000000001010000010000000000000000000000000000000000
010100000000000000000000000000000000000000000000000000
010000000000000000000000000000000000000000000000000000
000001000000100000000000000000000000000000000000000000
000010100001000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000100000000000000001000000000000010000001000010
000000000000000000000000000001000000000000000000000000
.io_tile 13 2
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.io_tile 0 3
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.logic_tile 1 3
000000000001000001100000010000000000000000000000000000
000000000000000000000011000000000000000000000000000000
101000000000000000000000000111100001001100110000000000
100000000000000000000000000000001100110011000000000000
011000000000000111000111101011101110010101100101000000
010000000000000000100000001011011110101001100000000000
000000000000000000000000001101000000000001100100000000
000000000000001101000000000101001111000010100000000001
000001000000000000000000000000000000000000000000000000
000000100000000000000000000000000000000000000000000000
000000000000000001000000000000000000000000000000000000
000000000000000000100010100000000000000000000000000000
000000000000000111000000010000000000000000000000000000
000000000000000000000010110000000000000000000000000000
000000000000000111000000000101000000000001100100000001
000000000000000000000000000001101111000010100000000000
.logic_tile 2 3
000010100010000000000011000000001000111100000000000000
000000000000000000000000000000000000111100000000010000
101000000000000111100000010000000000000010000000000000
100000001110000000000010001001000000000000000000000000
010100000000000000000000000000000000000000000000000000
000100000000000000000000000000000000000000000000000000
000000000000000000000000001111000000000001000000000000
000000000000000000000010000001000000000000000000000001
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000111100000000101100001001100110101000000
000000000000000000000000000000101001110011000000000101
010010000000000000000000000000000000000000000000000000
000001000000000000000000000000000000000000000000000000
.ramb_tile 3 3
000001000000000000000000000000000000000000
000010110000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000100000000000000000000000000000000000
000001001010000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
.logic_tile 4 3
001000000000000000000110010101000000000000001000000000
000000000000000000000010000000000000000000000000001000
101000000000001001100110010000000001000000001000000000
100000000000000001000010000000001011000000000000000000
011000000000000000000000000000001000001100111101000000
000000000000000011000000000000001001110011000000000100
000000000000000000000000000000001000001100111110000000
000000000000000000000010000000001001110011000000000000
000000000000000000000000000000001001001100111110000000
000000000000000000000000000000001000110011000000000000
000000000000000000000000000000001001001100111110000010
000000001000000000000000000000001000110011000000000000
000000000000000000000000000000001001001100111100000000
000000000000000000000000000000001001110011000000100000
010001000000000000010000000000001001001100111101000000
000010100000000000000000000000001001110011000000000010
.logic_tile 5 3
000010100001010101000110010001000001000000010000000001
000010000010010000000011011111001101000000000001000000
101001001100001001100110010101100001000000010000000000
100000100000000101000010101001101110000000000000000000
111000100000100011000010000011001011001000000001000000
010000000001010001000011111111011110000000000010000000
000000001100000001100011011111101011000100000000000000
000000000000000001000010100011101011000000000000000000
000000000110000001100011111011001010000000000000000000
000000100000000000000111100101101001000010000000000100
000000000000000111100111111101000001000010000000000000
000000000000000000000010001111101010000000000000000000
000000000000000001000110001011101111010000000000000000
000010001010000000100111110001111001000000000000000000
010001100000100111000111101111000001000001100100000000
100011100001011111100011111001001000000010100000000001
.logic_tile 6 3
000000000000000001000011110101100000000000010000000000
000001001100001111000010001101001001000000000000000010
101000000000001001100010010001100001000000000000000000
100000000000001111000110000001101000000000010000000001
110010100000000111100110010111011100100010000000000000
110000000001010111010011110101001101000100010000000000
000000000000001111000110001001111101100010000000000000
000000000000000001000110111001011101001000100000000000
000000000000000011000111100011001100100010000000000000
000000000100000000100110010001101110000100010000000000
000010101100000011100111000111111011000010000000000000
000001000000000111000111101001001011000000000000000000
000001000000000011100110101111101011000010000000000000
000010100000000011000000001111101011000000000000000000
110000000000000011100111000000000000000000000100000100
010010000000000000000111101101000000000010000000000000
.logic_tile 7 3
000010001001010011100111011011001001101011010000000000
000001000000100000000010000001011110010111010000000000
000010001010001001100011110101100001000011000000000000
000000000000000001000011000101001001000010000000000000
000000001100001000000111000111011100100010000000000000
000000000000000001010010010111001101000100010000000000
000001000010001011000110010101100001000001010000000000
000010000000001011100010011011101010000001100000000000
000000100000101111100111000000000000001100110000000000
000001001101000101100110010000000000110011000000000000
000001000000000001100000000011000000000000000000000000
000000100000000000100000001101000000000010000000000000
000001001110110011000000000001100001000000010001000000
000000101110111111010000001101001010000000110000000000
000000001010000001100000001001101000100000000000000000
000000000000000000000000001101111000000000000000000000
.logic_tile 8 3
000000000000000111100011011001111011101010100000000000
000000001110000001100110001111101010011010010000000010
101000000000000000000110010001001100010100000000000001
100000000000000000000011100101001100110000000000000000
010000000100000001000110101011100001000001010000000000
000000000000000001100110001011101010000010010000000000
000000001010001111100111100011100000000001010100000100
000000000000000111100100001011001001000001100000000100
000000000000001111000111100101000000000001010101000000
000000001100001111100100001101001100000001100000000001
000000000000001000000110110101001110111100100100100000
000000000000000011000111110001001110111101010000000000
000000000000001101100000011101000001000001010100000101
000000000000000101000011001001101011000001100000000000
000000000000000000000110101001000000000001010110000000
000000000000000000000100000101101111000001100001000000
.logic_tile 9 3
000100100001000001100010110101100000000001000000000000
000101000000101001000011110001001110000011000000000000
101100000000000001000111101111000001000000010000000000
100000000000001101100000000111101001000010000000000100
010000000000000101000111001101011011010100000000000001
010000001100000011000110100101011000111000000000000000
000000000001000001100010000011011100110011110001000001
000000000000001101000011000001101001010010100000000000
000000000001001001100011010011001101000011100000000000
000000001100100111000011101101101011000001110000000000
000100000000011111000000010101000000000000000000001000
000000000110010001100011111101000000000000010000000000
000000000001011111100011101001111100000001010000000000
000000000000101101000000001011001100000010010000100000
010000001110000000000000000000000000000000000100000010
100000000000001111000000000111000000000010001110000000
.ramb_tile 10 3
000001000000000000000000000000000000000000
000000110000000000000000000000000000000000
000001000000000000000000000000000000000000
000010100000000000000000000000000000000000
000000000000010000000000000000000000000000
000000000000100000000000000000000000000000
000010100000000000000000000000000000000000
000000000000000000000000000000000000000000
000010100000000000000000000000000000000000
000001001110000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000001100000000000000000000000000000
000000000001000000000000000000000000000000
.logic_tile 11 3
100000000000000000000000000000000000000000000101000000
000000000000000000000000000101000000000010000000000000
101001000000101000000000000000000000000000000100000000
100000100011010111000000000101000000000010000000000100
000000000100000001000000000000000000000000000000000000
000000000000001111000000000000000000000000000000000000
000001000000100000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000010000000000000000000000000000000000000000
000000000000100000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000001100000000000000000000000000000000000000000000
000000000000010000000000001000000000000000000101000001
000000000000100000000000000001000000000010000000000000
000000000001010000000000000000000000000000000000000000
000100000000100000000000000000000000000000000000000000
.logic_tile 12 3
001000000010000111100000000001000000001100110000000000
000000000000010000100011110000000000110011000010000000
101000000000100000000000001000000000000000000110000000
100000000000000000000000000101000000000010000000100000
010000000000000111000000000000000000000000000100000010
010000000000000000000000000101000000000010000000000000
000000000000000000000000000000000000000000000000000000
000001001000001011000000000000000000000000000000000000
000000000000000000000000000000000000000000000100000000
000000000000000000000000000111000000000010000000100000
000000000100010000000000000000000000000000000000000000
000000000001010000000000000000000000000000000000000000
000000000000000101000000000000000000000000000000000000
000000000000000000100000000000000000000000000000000000
010000000000000000000000000000000000000000000000000000
100000000000000000000000000000000000000000000000000000
.io_tile 13 3
000000000000000000
000111110001011000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000100000000001000
000000000000000000
000000000000000000
000100000000000000
000000000000000010
000000000001000000
000000000000000000
000000000000000001
000000000000000001
000000000000000000
.io_tile 0 4
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.logic_tile 1 4
000000000000000101000010000101100000000000001000000000
000000000000000000100000000000100000000000000000001000
000000000000000000000000000000000001000000001000000000
000000000000001101000000000000001110000000000000000000
000000000000000001000000000000001000001100111000000001
000000000000000000100000000000001010110011000000000000
000000000000000000000000000000001000001100111000000000
001000000000000000000010110000001000110011000000000000
000100000000000000000000000000001001001100111000000000
000000000000000000000000000000001100110011000000000000
000000000000000000000000000000001000001100111000000000
000000000000001011000000000000001001110011000000000000
000000000000000000000000000000001001001100111000000000
000000000000000000000000000000001000110011000000000000
000000000000001000000000000000001000111100000001000000
000000000000000011000000000000000000111100000000000000
.logic_tile 2 4
010000000000000111100010000000000000000000000000000000
001000000000000101000011010000000000000000000000000000
101000000000001011100110000000000000000010000000100000
100000000000001111100000000011000000000000000000000000
010000000000000011000000000101000001000000110000000001
001000000000000111000000000001001010000000010000000000
000000000000000011100011000000001011001100110000000000
001000001110000000000000000000001101110011000010000000
000000000000000111100000001000000000000010000000000000
000000000000000000000011101111000000000000000000100000
000000000000000000000010100101111000110000000000000000
000000000000000000000100001111101001100000000000000000
000000000000000000000000000001011000111010100000001000
000000000000000000000011101011000000111001010000000000
010010000000000000000010000000001001001100110100000000
000001000000000000000100000000011001110011000001000000
.ramt_tile 3 4
000001000000000000000000000000000000000000
000000100000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000001010100000000000000000000000000000
000000000001000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
.logic_tile 4 4
010000000000001001100110010000001000001100111100000000
001000000000000001000010000000001000110011000000010010
101000000000001001100000010000001000001100111100000000
100000000000000001000010000000001000110011000000000010
010000000000000000000000000000001000001100111100000100
000000000000000000000000000000001001110011000000000001
000010000000000000000000000000001000001100111100000100
001001000000000000000000000000001001110011000000000110
000000000000000000000000000000001001001100111100100000
000000000000000000000000000000001000110011000000000000
000000000000000000000000000000001001001100111100000000
000000000000000000000000000000001000110011000000000000
000000000000000000000000000000001001001100111100000001
000000000000000000000000000000001001110011000000000000
010001000000000000000000000000001000111100000000100000
000000100000000000000000000000000000111100000000000000
.logic_tile 5 4
010010100000000001000011010001111010010110100000000000
001000000000001011100111110111111010001001010000000000
101000000000000011100010010001101000110000000000000000
100000000000001011100111010001011110100000000000000010
110000000000001011000010000101000001000010100000000000
111000000000000001000011100011001101000001100000000100
000000000000000101100010110111111011000100000000100000
001000000000001011000010001001001101000000000000000010
000000000000001111000111111111111100111010100000000100
000000000000000111000110101101001011111001010000000000
000000000000000001000011101001100000000011110011000001
000000000000000000000110000001101100000001110000000000
000000000000001001000011000101100000000000110000000000
000000000000000101100100000011001101000000010000000000
000000000000001011100000000001000000000001100100000000
000000100000001111000000001011001011000010100010000000
.logic_tile 6 4
000000000000001111000000010111011011000000100000000000
000000000000001101000011111001001010000000110000000000
101000000000000000000010100001011001000110100001000000
100000000010001111000110010111011001001111110000000000
010000000000000000000110001001011100000110100000000000
110000000000001001000100001111001101001111110000000000
000000000000001001100111001011111011000110100001000000
001000000000000001000110010011111011001111110000000000
000000000001000011100011111111000000000001000000000000
000000000000100000000010110111100000000000000000000000
000000000000101011100000010001111000000110100000000000
000000000001000011100010110101011100001111110000000000
000100001110001000000010000000000000000000000100000000
000100000000000011000111001111000000000010000000100000
110001001100000011100011000000000000000000000100000010
010000100000000000100000001011000000000010000000000000
.logic_tile 7 4
000001000000000000000111100011000000000000001000000000
000010101000000111000000000000100000000000000000001000
000100000000001011000110000111100001000000001000000000
000000001110000011100000000000001100000000000000000000
000000000000100011000110000000001000111100000000000000
001000000010010000100000000000000000111100000000000001
000010000000001001000000010101101111110000000000000000
001001000000000001100011111001001001100000000000000000
000000000000001011100011001101100000000001000000000000
000000000001010011000100000011100000000000000000000000
000000000000000011100011101001001111000110100000000000
000000000000000111100000000111011101001111110001000000
000000000000000101000011001111001100111010100000100000
000000001000000111000000000001001011111001010000000000
000100000000000001000000001011001011000100000000000000
000100000000000111000000000001001010001100000000000000
.logic_tile 8 4
000001000000001001100011100001101011100010000000000000
001000000000000001000010010111111001000100010000000000
101000000000001101100111110111111000100010000000000000
100000000000001011100011101011101100001000100000000000
011000000000000111100111110001100000000011000000100000
011000000000000000100111110011001101000010000000000000
000000000000001000000010010001000001000000010000000100
001000000000000001000010110001001010000000000000000000
000000000000001111100011110111111011100010000000000000
000000000000000101100011101101011011000100010000000000
000000000000001001000000000011100000000000000001000000
000000001100001011100010010111000000000001000010000000
000000000000000001000000001001011010000110100000000000
000000000000000011100000001011111010001111110001000000
010010100000001000000010001000000000000000000100100000
100001000000001011000100000011000000000010000000100000
.logic_tile 9 4
000000000000000000000010101001000001000001010000000000
000000000000000011000111100101101000000011000000000000
101010100000000111100000011101111000000001000000000000
100001001010001001100010111101001011000100000001000000
010000000000000000000000010011000000001100110000000000
011000000000000000000010000000100000110011000000000000
000000000110010111100000010001011001000011100000000010
001000000000101011100010110111011010000001110000000000
000000000000000000000111001001111101000010110000000000
000000001100000011000100001001011000000011010000000000
000000001001010011100111100011011101010111100000000000
000000000000100000100110011111011111101101010000100000
000000000000000000000000000000000000001100110000000000
000000000000001111000011100000000000110011000000000000
010000000000000000000000011000000000000000000100000010
101000000000000000000010000011000000000010000001000000
.ramt_tile 10 4
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000011100000000000000000000000000000000000
000010101010000000000000000000000000000000
000001000000000000000000000000000000000000
000010001110000000000000000000000000000000
000000000111010000000000000000000000000000
000000000110100000010000000000000000000000
000010001010000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
.logic_tile 11 4
000000000000000001100000000011101111000010000000000000
001000000000000000000010001101101010000000000000000000
101000001110101001000000010011000000000000000000000100
100100000001010001000011100011000000000001000000000000
110000001010001011000011001011100001000001010001000001
011000000000000001000000001001001100000010010000000000
000000001110000111100000001111100001000000000010000001
001010100000100000000011001101001000000000100000000100
010000000000000011100110110011011110000010000000000000
100000100000000111000011001001111110000000000000000000
000001000000001011100110100001100000000001000010000000
000000100000001011000000000101000000000000000000000000
000000000000001101100000000000000000000000000100000000
000000000000000101000000000101000000000010000010000100
010000000000100011000000010000000000000000000100000000
100000000000000000000010100001000000000010000000000100
.logic_tile 12 4
000010000000001111100000000000000000000000000100000000
000000000000000011100011100111000000000010000010000000
101000000000000000000000001000000000000000000110000000
100000000000000000000000000011000000000010000000000000
010100000000000101100000000000000000000000000101000000
011000001110000000000011000101000000000010000001000000
000001000001000000000000000000000000000000000101000000
001010000000000000000000000011000000000010000000000000
000000100000000111000000000000000000000000000110000000
001000000000000011000000000011000000000010000001000000
000000000100100011100000000000000000000000000100000000
000000001101010000100000001101000000000010000001000100
000000000000000011000000000000000000000000000100100000
000000000000000000100000000001000000000010000000000000
010000000000000000000000000000000000000000000100000000
100000000000000000000000000001000000000010000000100000
.io_tile 13 4
000000000000011010
000100000000000000
000000000000010000
000000000000000001
000000000001000001
000000000001000000
001100000000000000
000000000000000000
000010000000000000
000111010000000000
000000000011000010
000000000001000000
000001011000000000
000000000001100001
000000000000000001
000000000000000000
.io_tile 0 5
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000001100000
000000000000000000
000000000000000000
.logic_tile 1 5
010000000010001111000110010101001111001100110000000000
001000000000010001100011100000001001110011000000000000
000000000000000001000000000101100000000000000000000000
000000000000000001000011100011000000000001000000000000
000000000000001000000000000001100001000000010000000000
000000000000100111000000001001001000000000110010000000
010000000000000001000000000111011001001100110000000000
101000001110000000100011100000111011110011000000000000
010000000000000011000010000011000000000000000000000000
000000000000010000100100000111100000000001000000000000
000000000000000000000000000000000000000010000000000010
000000000000000000000000000001000000000000000000000010
000001000000000011000111100001000000000000000000000000
000010000001001011100000000111100000000001000000000010
000000000000100000000000000001000000000000000000000000
000000001111010000000000000011000000000001000000000000
.logic_tile 2 5
000000000000001111000010000111101010111010100000000000
000001000000000001100011000011001010111001010000000000
101000000000000011000111100111101000001100110000000100
100000000000001001000011110000011001110011000000000000
110000000001010011000110000000000000000000000000000000
011000000000001111000000000000000000000000000000000000
000000000000000000000111101011111001111010100000000000
001000000000000111000000000101011000111001010000000000
000000001100100011100000001011000000000000000000000001
000000000001001111000011110001001110000001000000000000
000010100000000001100000001001000001000001100100000000
000001000000000111100000001111001001000010100000000000
000000000000000011100110000001000001000001100100000000
000000000000000000100100001111001011000010100000000010
000000000000000111000000011101000001000001100100000000
000000000000000111100010010011101001000010100000000000
.ramb_tile 3 5
000000000000000111000011101101000000000000
000000000000000111000000001111100000000001
101000000000000011100010000000000000000000
100000000000000000100100000001000000000000
000000000000100000000000011001100000100000
000000001000000000000011111011100000000000
000000000000000000000000010000000000000000
001000000110000000000011111001000000000000
000000000000000000000000000101100000000000
000000000000000000000000001111100000000001
000000000000000101000000000000000000000000
000010100000000111100010110111000000000000
000000000000000000000111100001100000000010
000000000000000001000000000001000000000000
110000000000100000000010101000000000000000
010000000001000000010100000011000000000000
.logic_tile 4 5
000000000000001001000000000001100000000000001000000000
001000100000001111100010000000100000000000000000001000
101001000000100000000010100101100001000000001000000000
100010101001000000000100000000001101000000000000000000
010000000000000000010111100101101001001100111000000001
011000000000000000000010000000101101110011000000000000
000000000000100101000000000000001000111100000001000000
001000001011000000100010110000000000111100000000000000
000000000000100000000000000000000000000010000000000000
000000000000000000000000000001000000000000000001000001
000000000000000000000010000000000000000000000110000000
000000000000000000000010000001000000000010000000000000
000000000000000000000000000000000000000000000100100000
000000000000000000000000001101000000000010000000000001
010010000000000000000000000000000000000000000100000000
100000000000000000000000001101000000000010000010000000
.logic_tile 5 5
000000000000000001100110110111101101000110100000000000
000000000000000001000111010001111001001111110000000000
101000000000011111100010101001101100000100000000000000
100000001100001011000111101001001001001100000000000000
110010100000001011000111101011001011000010000001000000
111001000000001011000110001111111011000000000000000000
000000000000000011100011001101001000110000000001000000
001000000110000111100100000001111100100000000000000000
000000000011011011000011110111101101100010000000000000
000000001010100001000111101011011111001000100000000000
000000000000000111100111001101001010110000000000100000
000000000000001111100000000101101000100000000000000000
000000000000000000000111001011101011100010000001000000
000000000010000000000000000011111011000100010000000000
000000000010001000000110101101100000000001100100000000
000000001110000011000010000011001010000010100001000000
.logic_tile 6 5
000010000000010001100111101001000000000001000000000000
000001000000101001000011111101000000000000000010000010
101001001100001001100000001101101100000010000000000000
100011100000000101000010010101011111000000000000000000
010000100000000000000110011001100000000000010000000000
011001000000000000000010110001001011000000000000000000
000000000000001111100011001011111011100010000000000000
001000000000001011000011001011001010000100010000000000
000000000000001000000000000001001010000110100000000000
000000000000000011000011010011111111001111110000000000
000001000001001000000111001001101100100010000000000000
000000100000001101000000001111111111000100010000000000
000000000000100000010010010000000000000000000100000000
000000000001010000000011010001000000000010000000100000
010010100000000000000000011000000000000000000100000000
100000000000000000000011001101000000000010000000000000
.logic_tile 7 5
000001000000000011000000000101001100010000000000000001
000000100000000011100011100001111001110000000000000000
101000000000001000000000000101100000000001000000000000
100000000000000101010000001111100000000000000000000000
110000000000000000000000010101001101000000100000000000
011000000000001101010010100111001000000000110000100000
000000000110000001100110000000000000000000000100000101
001000000000101001100000000001000000000010000000000001
000000000000000001100111001000000000000000000100000010
000000001000000000000011110101000000000010000000000000
000000000000000000000011111000000000000000000100000101
000000000000000000000111111011000000000010000001000000
000000000000000011000000011000000000000000000100000000
000010000000000000100011011011000000000010000000000010
010000000110000000000000001000000000000000000100000001
100000000000000000000000000101000000000010000000000000
.logic_tile 8 5
000010100000001000000011110111000000000001000001000000
000000000010000011000111101101100000000000000000000000
101000000000000000000111010001011101000110100000000000
100000000000000000000111011011001001001111110000000000
110000001010000011100010001101000001000001010000100000
011000000000101011000100001001001010000010010000000000
000010000000001111100111010001001011000110100001000000
001000000000000111000110101011101001001111110000000000
000000000000010000000111000101101111000110100000000000
000001000000101001000111111111101011001111110001000000
000001000000000101100000001011011100100010000000000000
000010100000000111100000000101001110000100010000000000
000000000110000000000111001011101001010000000000000000
000000000000001001000111100111011111110000000000000010
010010100000001001100110101000000000000000000101000000
100001000001000011000100000111000000000010000000000000
.logic_tile 9 5
010000000000001101100111000001011000001100110000000000
001010100000001111100000000000000000110011000001000000
101000000010101111000111110101100000000010000010000000
100000000001010111000011011111001001000000000000000000
010000100000100011100000011101100001000000000000000000
000000000001000011100011011011101110000001000000000000
000000001010000011100000011000000000000010000100100000
001000001110000000100011101011000000000000000000000000
000000000000000011000011000101000000000001010100000000
000000000110001011100100000011001010000001100001000000
000010100000000001000010001001100000000001010110000000
000001000000000000100010001001001100000001100000000001
000000000000000000000011011111101010111110100100000000
000000000000000000000010001001011111111100010000000001
000000000000001111000000000001000001000001010101000000
001000000000001011000000001011001100000001100000000000
.ramb_tile 10 5
000000000000000011100000000101000000001000
000000001010000000000000001011000000000000
101000000000100000000011101000000000000000
100001000001010000000000001011000000000000
000000000001011000000000001101100000000000
000000000001001111000000001011000000100000
000000000000001000000000001000000000000000
001000000000000101000000000011000000000000
000001000000000000000010000011000000000000
000010100000000000000111100111100000000010
000000000000000101000111000000000000000000
000000000000000000000110010001000000000000
000000000000000001000000001001100000000000
000000000000000000100000001111100000001000
110000000000000101100010101000000000000000
110000000000000111100000000111000000000000
.logic_tile 11 5
010000000000001111100111101111000000000010110000100000
001000000000001111100111001001101100000001010001000100
101000001111000001000010000011000001000000110000000000
100000000000000001000010001111001001000000100001000001
010000000000000000000110000001000000000001010001000001
000000000000000000000010000001001110000010010000000000
010000000000000001100000011011000000000001010000000000
011000000000000000000010001011101100000010010000000001
010000000001010011100000000111000000000001010000000000
001000000000100111000010111001001110000010010001000000
010000001110000000000110001001100001000001010000000000
100100000000000000000000001101001000000010010000000001
010001000000100011100000001000000000000000000100100000
100000000000011101000011000101000000000010000000000000
000000000000000000000000000101000000000001010100000100
001000000000000000000000001101101001000001100000000000
.logic_tile 12 5
010000000000001101000000011101100001000010000000000000
001000000100000001100010001101101010000000000000000000
101000000010001011100000010001100000000001000000000000
100000000001011111000011110101100000000011000000000000
110000000000001101000111100001011001000100100000000000
011000000000000001110000001111001000000000000000000000
000000000000001001100110010001000000000000000000000100
001010000000001111000010000011100000000001000000000000
000001000000000001100000010101100000000011100000000010
000010101100000000000011000001001011000001110000000000
000000000000000000000000000101000000000001000100000010
000010000000010000000000000101000000000011000100000000
000000000000100000000110100000000000000000000100000100
000000000001010000000100001111000000000010000100000000
010000100000100000000000000000000000000000000101000100
101000000001010000000000000011000000000010000100000000
.io_tile 13 5
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.io_tile 0 6
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.logic_tile 1 6
000000000000000101000011111111000001000010000000000000
000000000000000001000110001011001011000000010000000010
101000000000000001000000001101100000000000000000000000
100000000000001001100000001111000000000001000000000010
110000000000100000000010001111000000000010000000100000
010000000001010000000100001011000000000000000000000000
000000000000000111000111000001100001000001010110000000
000000000000000101000100000011001100000010010001000000
000000000000110001100000000001100001000001010100100100
000000000000001011000010000011001110000010010000000100
000000000000000011000000001101000001000001010110000000
000000000000000000100011000101101100000010010010000000
000000000001000000000000000001000001000001010110000000
000000000000101111000000001001101110000010010000000100
000000000000000011000000000001000001000001010111000001
000000000000000000100011000001001100000010010000000000
.logic_tile 2 6
000000000000101001100000010001100001001100110001000000
000000000001000101000011100000001111110011000000000000
101000000000001111100011010101111010010110100000000000
100000000000000001100010101101101110100001010000000000
010000000000000000010011000101100001000000100010000000
010000000000000000000011000011101001000001000000000000
000000000000000001000011000000001101001100110000000000
000000000000000000100011010000011100110011000000000000
000000000010000011100011101111011000101110100000001000
000000000000001111000011010111010000101101010000000000
000000000001000001100110011001111100010001010100000000
000000000000000000000111001011011101010010100000000000
000100100000000000000011100001001100010001010100000000
000100001000001111000000000001001111010010100000000001
000001000000000111000110011101011100010001010100100100
000011100000000000000010011111111101010010100000000000
.ramt_tile 3 6
000000000000000000000010001001100000000010
000000010000000000000000001101100000000000
101001000000000101100111111000000000000000
100000110000101011000010100101000000000000
000000000001000000000000001011100000100000
000000001100100000000011001001100000000000
000000000000001000010110100000000000000000
000000000000000011000000001101000000000000
000010000000000000000000011011100000100000
000001000000000000000011100001000000000000
000000000000000001100110001000000000000000
000000000000000000100100001111000000000000
000000000000000000000000000001000000100000
000000000000000000000000001011100000000000
110000000000000111000000011000000000000000
110000000000000000100011110001000000000000
.logic_tile 4 6
000000000000001001100000010001100000000001000000000000
000000000000000001000010001001101101000000100000000100
101001000001000001100110000111111110001100110000000000
100000100000000000000000000000100000110011000000000000
010000001101011111100111000101000001000010000000000000
110000000000100001100110100111101010000000000000000000
000000000000000101100010001011101011101000000000000000
000000000000000000100000000011101110110100000001000000
000000000000000000000000010111100001000011110100000100
000000000000000001000011110001101010000010110000000000
000000100000000111000000011111100001000000010100000000
000000000000000000000011001111101000000010000001000000
000000000001000001100000000111100000000011110100000000
000000000000100000000000000001101100000010110000000000
010000000000001111100110010101100000000011110100000000
100000000010001111100011010101101000000010110000000000
.logic_tile 5 6
000000000001011111100111111111011100111010100000100000
000000000010100111100010001011101001111001010000000000
101000000000000111000000000011100000001100110000000000
100000000000001001000000000000000000110011000000000000
010000000000000001100011101101011010110000000000000000
110000000000000011000100001011001110100000000000000000
000000000000000001100011011001011011000100000000000100
000000000000000011000011111111001000001100000000000000
000000000000001000000000010001011011101110100000100000
000000000100001011000011100101011011101101010000000000
000000000000000001000111000011001100000110100000000000
000000000000000001100110110111101001001111110000000000
001000000000000101100000001000000000000000000100000000
000001000000100101000010100001000000000010000001000000
010000000000000000000000011000000000000000000100000000
100000000000000000000010001011000000000010000001000000
.logic_tile 6 6
000000000000100101100010100111111101000110100000000000
000001000000011101100110010001001001001111110000000001
101000100000001001100111111011001000000100000000000000
100000000000000001000011111111011001001100000000000000
110001000000000001000110001101001101111010100000000000
010010100000001101100010110101111000111001010000000100
000000001000010111100110000101111001000110100000000000
000000000000100111000000000111111010001111110000000000
000000000000001011100011111111011001110000000000000000
000000001000000101010011110101111101100000000000000000
000000100000000011000000010111100000000001000000000000
000001000000000000000010000101000000000000000000000000
000000000000001000010000010001011000000000100000000000
000000100000000101000010100101001011000000110000000000
010000001100000011100000010000000000000000000101000000
100000000000000111000010100011000000000010000000000000
.logic_tile 7 6
000000000000001111000111111011111010000000110000100000
000000001010101111000010111111111000000000000001000000
101100000001000101000010101011001100000110100010000000
100000000000000000100100000001101001001111110000000000
110001000000000011000011101011111010001111110001000010
110000100100000000000000001111111000111100110000000011
000000001110000101000110001101101011000010000001000000
000000000000001111100010110101101111000000000000000000
000000000000001000000111001001101100000110100000100000
000000000000000001000010000101111001001111110000000000
000010100010000000000010000101001011100010000000000000
000001000000001001010100000001101111000100010000000000
000000000000000000010011101000000000000000000100000000
000000000000000000000110100011000000000010000000000000
011000000010000000000011010000000000000000000100000010
100010000000000000000010001111000000000010000000000000
.logic_tile 8 6
000100000000001111000110001111011110100010000000000000
000100000000100001100000001001011110000100010000000000
101000000000001001100111010001111011100010000000000000
100000000000001011000111100101011010000100010000000000
110001001100000011000111100001011111010000000001000000
110010100000001001000100000001101100110000000000000000
000000100000001101100110111101100000000000010000000000
000001001000001111000011110001001100000000000000000000
000000000000100001100011100111011110000010000000100000
000000000000000000000111111101111110000000000000000000
000000000000001000000110011111101101100010000000000000
000100000000001101000010001001111011001000100000000000
000000000000000111100010001011000000000001100110000000
000000000000000001000111111011101010000010100001000000
010000000000000000000010011011100000000001100101000000
100000000000000111000011011011001000000010100000000000
.logic_tile 9 6
000000000000001111100000011001111101000000000000000000
000010000000000001100011001011001001000000010000000000
101000000000101001000011001101101101000000000000000000
100000000101000011100010111111001010000000010000000001
110000000000001000000011111011100000000001010000000100
100000000000001011000011000001101001000010010000100000
000000000000000001000111011111100000000001010000100000
000010000000001101100111101101001011000010010000100000
000000000000001111000010000111001010001100110010000000
000000000000000111000100000000100000110011000001000000
000100000000000001000010010101100001000000000010000000
000000000000000000100011101011101001000001000000100000
000010100000000000000000000001001100000000100000000000
000011000000000000000010000001001011000000000000100001
000000000000100001010000010000000000000000000100000000
000000000000010000000011100000000000000010000000000001
.ramt_tile 10 6
000000100000000000000000001011100000000000
000001010000000000000000001111100000000000
101000000000000000010110100000000000000000
100000010000000000000000001111000000000000
000010000000000000000010000011000000000000
000001000001000000000100001101100000000000
000000000001000111100000001000000000000000
000001000000100000000011100011000000000000
000000000000000011100010001111100000000000
000000000000000000100100001011100000000101
000000000000000101100110011000000000000000
000000000000000000000110101001000000000000
000000000000000000000111110101100000010100
000000001100000000000011001111100000000000
010000000000000000000111010000000000000000
110000000000000000000011000011000000000000
.logic_tile 11 6
000000000000011000000000001111111100000000000000100000
000000000000101111000000001111001000110000000001000000
101000000000000001000000001001111110000000000001000000
100000000000000111000000001011001010000000110000000100
110000000000001000000000000011000000000000000000000000
100000000000001111000000001011001100000000010001000000
000000000100000000000011000111000000000000000001000000
000000001010000000000111011111001110000000100000000000
010000000000000101000000001101100000000001000000000000
010000000000001101100010111101100000000000000000100100
000001000000100111100111001000000000000000000100000000
000000000000000000100100000001000000000010000000000000
000000000000000101000000000000000000000000000100000000
000000000000001101100010110000000000000010000000000100
000000000000000111100111000000000000000000000100000000
000010000000011001100100000000000000000010000001000000
.logic_tile 12 6
000010000000000000000000011101100000000011000000000100
000000000000000000000011101101100000000000000000000000
101000000000000000010000000111001001001100110000000000
100000000000001111000000000000011100110011000000000000
110000000010000000000000001000000000000000000100100000
100000000000000000000000000001000000000010000000000000
000000000000000011110010101000000000000000000100000000
000000000000000000000010101111000000000010000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000011100000000000000000000000000000
000000000000000111100000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000011000011000000000000000000000000000100000000
000000000000100000000000001011000000000010000000100000
010000000000000000000000000000000000000000000000000000
110000000000000000000011010000000000000000000000000000
.io_tile 13 6
000000000000000010
000100000000000000
000000011000000000
000000001000000001
000010000000000001
000011110011000000
001100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000010000010
000000000001000000
000000000000000000
000000000000000001
000000000000000001
000000000000000000
.io_tile 0 7
000000000000000000
000000000001100000
000000000000000000
000000000001100000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.logic_tile 1 7
000000000001000000000000000101000000000000001000000000
000000000000000000000000000000000000000000000000001000
101000000000010000000111100101000001000000001000000000
100000000000000000000000000000001100000000000000000000
110000000000000111100000000011001000001100111000000000
010000000000000001000000000000100000110011000000000010
000000000000000000000000000011101001001100111000000000
000000000000000000000000000000001100110011000000000000
000000000000000000000110110001101001001100111000000000
000000000000000000000011010000101110110011000000100000
000000000000001111000000010011101001001100111000000000
000000000000000101000010100000101100110011000000000010
000000000000000000000000000000001000111100000000000010
000000000000000000000000000000000000111100000000000000
000000000000001111000000001000000000000000000101000000
000000000000000011000000000111000000000010000000000000
.logic_tile 2 7
000010100000000000000110010011000000000000001000000000
000000000000000000000010000000100000000000000000001000
101000000001011001100000010000000001000000001000000000
100000000000100001000010000000001100000000000000000000
110000000000000000000000000000001000001100111110000000
010010100000000000000000000000001001110011000000000000
000000000000000000000000000000001000001100111100000000
000000000000000000000000000000001001110011000000000100
000000000001010000000010000000001001001100111100000000
000000001110000000000111100000001000110011000010000000
000000000000000001000000000000001001001100111110000010
000000000000000000100000000000001000110011000000000000
000000000000000000000000000000001001001100111100000000
000000000000010000000000000000001001110011000000000100
010000000000000000000000000000001000111100000000000100
100000000000000000000000000000000000111100000000000000
.ramb_tile 3 7
000000000000000000000000000000000000000000
000000010000000000000000000000000000000000
000000000000000000000000000000000000000000
000000001010000000000000000000000000000000
001010000000000000000000000000000000000000
000000001100000000000000000000000000000000
000000000110000000000000000000000000000000
000000000000000000000000000000000000000000
000001001110000000000000000000000000000000
000000100000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000001100000000000000000000000000000000
000000000110000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
.logic_tile 4 7
000000000000000001000000010001100000000000001000000000
000000000000001001000011110000100000000000000000001000
101010100110000001100010010000000001000000001000000000
100000000000000000000110000000001111000000000000000000
110000000000000001000000000011100000000000001000000000
010010100000000000100000000000101000000000000000000000
000000000000000000000000000000000000000000001000000000
000000000000000000000011010000001101000000000000000000
000000000000000101100110100000001000111100000000000000
000000000000000000010010010000000000111100000000100000
000000001101000000000010001101000000000001100100000000
000000000000100000000100000001001100000010100010000000
000000000000000000000000011001000000000001100100000000
000000000000000000000010101001001001000010100000000000
010000000001000000000000011101000000000001100100100000
100000000000100000000010101101001111000010100000000100
.logic_tile 5 7
000000000000010111000000000000000000000000000000000000
000000000000100000100011100000000000000000000000000000
101000000000001001100000010101100000000000100000000000
100000000001010001000011100011101000000000000000000000
010000100000000111000010100101000000000001000000000000
010001001000000000100110000111101010000000000000000000
000000000000001000000010001000000000000010000000000000
000000000000001111000000000101000000000000000000000000
000000100001000111000000001000000000000010000010000000
000000001000000000100000001111000000000000000010000000
000000000000000000000111000011101011001100110010000000
000000000000000000000111100000111101110011000000000000
000100000000000111000000001000000000000010000000000000
000000000010000000100000001001000000000000000000000000
010000000000000000000010101000000000000000000100000100
010000000000000000000100000001000000000010001000100000
.logic_tile 6 7
000100001100000000000111101011011110001100000000100000
000100001110100000000000000001111100000000000000000000
101000000000000111000000000000000000000000000000000000
110000000001011001000000000000000000000000000000000000
011000000000000000000111101011001101000000000000100000
110000000000000000010100000001101010000010000000100010
000000000000001111100000001011100000000001000000000000
000000000010000001000000000101000000000000000000000000
001000000000000111000111101011011110000000000000100010
000000000010000111000100000001111100001100000000000010
000000000001001000000000000000000000000000000100000010
000000000000001101000000001001000000000010000000100000
000000001010000000000000000000000000000000000000000000
000000000000000000010000000000000000000000000000000000
010000000000000000000000011000000000000000000100000010
100000000000100000010010100001000000000010000000000000
.logic_tile 7 7
000000000000001011000110001001101010100010000000000000
000000000000000011000010000101011101001000100000000000
101000001000000011000111111111011011100010000000000000
100001000000000000000010001001011110000100010000000000
010000000000000111000111100001000000000000010000001000
110001001000000001100111100011100000000000000000000000
000000100000000111000010010101011101100010000000000000
000000000000001011100011110001011101000100010000000000
000100100000001000000011111111011111000010000000000000
000100000000000001000010110011111111000000000010000000
000000000000001000000110001001011000000011000000000000
000000000010001101000010000101111101000000000000100010
000001000000000111000000010111001010001100110000000000
000010000000001111100011110000001000110011000000000001
010010000000001000000110001000000000000000000100000000
100001001000001101000010011101000000000010000000000000
.logic_tile 8 7
000000000001010111010000011101000000000001000001000000
000000000010100000000010100001100000000000000000000000
101000000000000101100111011001011000010000000000000000
110000100000001011000111100111111101110000000000000000
110000001110000111000111000111000000000000000000100000
010000000000001011100011111111100000000001000000000000
000000000000000111100110011101011011000110100000000000
000000000000001011000010000101011000001111110000000001
000010100000001000000110111101011011100010000000000000
000001000000001111000111100101011101000100010000000000
000000000100000000000000011101011101000010000000000000
000000000001011111000011011001101111000000000000100000
000000000000000000010110100000000000000000000110000000
000000000000000000000111110011000000000010000000000100
010001000000001000000000010000000000000000000100000100
100000100000000001000011010001000000000010000000100000
.logic_tile 9 7
000000100000000111100110010001011010000010000000000000
000000000000100000100010001001111010000000000000000110
101101000000001111000111111101001111100010000010000000
100010000010000001000011101011101001000100010000000000
110010100000000101100011001011000001000000000000000000
100001000010000011000110111011101000000000010000000000
000000000000001111000000010111000001000000000000000000
000000000000011111000011110111101000000000010000000000
000000000000001011100011110001000001000010000000100000
000001000000000111000111010011001010000011000000000000
000000000000001000000110101011011000000010000000100000
000010000000001011000010010101111100000000000000000000
000001000000000011000011101101000000000001000001000000
000000001110001001000100000001000000000000000000000000
110000000000000000000000000000000000000000000100000010
010000000000000000000000001101000000000010000000000000
.ramb_tile 10 7
000000000000000000000000000000000000110000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000010
000000000001000000000000000000000000100000
110000000000000000000000000000000000100010
110000000000000000000000000000000000000000
000000000000000000000000000000000000010100
000000000000000000000000000000000000011000
000000000000000000000000000000000000100010
000100001110000000000000000000000000010000
000010000000000000000000000000000000000000
000011000000000000000000000000000000001000
000000000000000000000011100000000000000100
000000000000000000000000000000000000001000
000000000000100000000000000000000000010010
000000000000010000000000000000000000000000
.logic_tile 11 7
000010001000000000000111000001101111000010000000000000
000011000000000000000000000011111111000000000000000000
000000000000000001100111000101000000000000000000000000
000000000000001011000011010011101010000000010000100000
000000000110010001100111011111000001000010000001000000
000000001010100011000010001001001010000011000000000000
000001000000000011100000010101011011000000000000000000
000000000000001011100010000011101010100000000000000000
000000000000100111000010010001111010000000000000001000
000000000000010001000011110101010000000001000000000110
000000000000000000000000000101011000010110100010000000
000000000100000000000000001011101100101000010000000000
000010000000001111000000000111101000010000000000000000
000001000000000001000010001011011110110000000000000000
000000000000001000000111100001101010111011110010000000
000000000000000101000000001101011100110011110000000000
.logic_tile 12 7
000000000000000001100111000101100000000000000000100000
000100000000000111000011000001000000000001000001000100
101000001110100111100000010101001100100010000000000000
100000000001000011000010001101011110000100010000000000
110000000000000111110111100000000000000000000000000000
110000000000000111100011010000000000000000000000000000
001000000000001111100000000001101111100010000000000000
000110000100000111100011011111001110000100010000000000
000001001110000000000000001001000000000000010000001000
000000100000000000000011011001000000000000000000000000
000000000000000000000000000001000000000000000000000010
000000000000000000000000000101100000000001000001000000
000000000000100011100111001101111000100010000000000000
000000001010000011000011110101101011001000100000000000
000001000001100000000000000000000000000000000110000000
000010000000100011000000001001000000000010000000000100
.io_tile 13 7
000000000000000010
000100000000001000
000000000000000000
000000000000011001
000000000000100010
000000000000110000
001000000000000000
000000000000000000
000000000000000000
000100000000000000
000001011000000000
010000000000000000
000000000001100000
000000000000000001
000000000000000000
000000000000000000
.io_tile 0 8
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000001010000000100
000000001000000100
001100000000000000
000000000000000000
000000000000000000
000000000000000000
100000000000000000
000000000000000000
000000000000000000
000000000000000001
000000000000000000
000000000000000000
.logic_tile 1 8
000001000000000000000010100111101011000001000000000000
000000100000000000000010011001111110000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000001100001000000110011000000000000010000000000100
000000000000000001000010010011000000000000000000000000
000000000000001001100000011011100001000010000000000000
000000000000001001000010010101101011000000000000000000
000001000000001000000000001000000000000010000000000000
000000000000000001010000000111000000000000000000000100
000000000000000000000011001101001100100001010000000010
000000000000000001000010011011101111010110100000000000
000000000000000000010000011001000000000000000000000010
000000000000000000000011100101100000000001000000000000
001000000000000101000000000101000000000000010001000000
000000000000000000000010100101101111000000000000000010
.logic_tile 2 8
000000100000000111100000000101100000000000001000000000
000000001010000000100010000000100000000000000000001000
000010100000000000000111000000000000000000001000000000
000001000000000000000000000000001000000000000000000000
000000000001000000000000000000001001001100111000000000
000001000000000000000000000000001110110011000000000010
000000000000000111100000000000001001001100111001000000
000000000000000000000011100000001001110011000000000000
000010100000000000000000000000001001001100111000100000
000000000000000000000000000000001010110011000000000000
000100000000000000000000000000001000001100111000000000
000100000000000000000000000000001110110011000000000100
000000000000001000000000000000001000001100111000000000
000000000000001011010000000000001001110011000000000010
000000000000000001000000000000001000111100000000000010
000000000000000000000000000000000000111100000000000000
.ramt_tile 3 8
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000001100000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000010000000000000000000000000000
000000000000100000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000010000000000000000000000000000000000000
000001000000000000000000000000000000000000
000001001100000000000000000000000000000000
000010000000000000000000000000000000000000
.logic_tile 4 8
000000000000000111000110000111111001111111000000000000
000000000000001001100011101111111000111111010000000100
101000000001010001100110001101000001000010100000000000
100001000000000001000000000101001110000001100000000000
010000000000001111100010011101101010111100000000000000
000000000000001011000011101011101000111000000000000000
010000100000000011000110010011101011000001000000000000
100000000000001011100011110101111011000000000000000000
000000100000000000000000000001100001000001100010000000
000000000000000000000000001001001010000010100000000000
000010000000000000000000010111000000000010010000000000
000001000000000000000010101101001000000001010000000000
000000000000001001100111111111001111110000000001000000
000000000000000001000110001101101000100000000000000000
000000000000001000000000011111011010001100000110000001
000000000000001101000011011111111001001110100000100000
.logic_tile 5 8
000000000000000111000111100001000000000000001000000000
000000000000000000000011010000100000000000000000001000
101000000000000000000000000001000000000000001000000000
100000001000000000000011000000101111000000000000000000
110000000000000000000111100011101000001100111000000000
110000000000000000000011010000101101110011000000000100
001000000000001001100000000000001000111100000000000000
000000000000000001000000000000000000111100000000000000
000000001010000000000010111011000000000010000000000000
000010001110000000000011001001100000000000000000000000
000000000000000000000110100000000000000010000000000000
000000000000000000000000000001000000000000000000000000
000000000000000000000110110101000000000010000000000000
000010100000000000000111001101100000000000000000000000
010000000000000000000000001000000000000000000110000000
110000000001000000000000000101000000000010001000000000
.logic_tile 6 8
000000000000000111000010110111100000000000001000000000
000000000000000000100110000000001100000000000000000000
101000000000000101000111110000001001001100111000000000
100000000000000000100110000000001101110011000001000000
010000000000000000000111110000001001001100111000000000
110000001000000000000110100000001110110011000000000000
000001000000000000000000000000001001001100111000000000
000010100000000000000000000000001001110011000000000001
000000000001001000000000010000001000111100000000000000
000000000000000111000010100000000000111100000001000000
000100001010001000000010100001100000000001100000000000
000000000000001001000000000001101001000010100000100000
000000000000000000000000000001100000000010010000000000
000000000000000000000000001001001101000001010000000000
110000000000001001000000000000000000000000000100000000
010000000000000011100000001101000000000010000001000000
.logic_tile 7 8
000000000000000101100000001001101010101010010000000000
000000000000000001100010010101011001010110010000000000
101000001100001111100010000000000000000010000000000010
100000000000001111100100001111000000000000000000000000
010100000000000000010011010111111001000010000000000010
110000000000000000000010001111001000000000000001100100
000000000000000001100000011011000000000001100010000000
000000000000001001000010001001001101000010100000000000
000000000000001000000010100000000000000000000000000000
000000000000000001000100000000000000000000000000000000
000000000000000000000110000001000001000010100000000000
000000000000000000000000000001001010000001100000000000
000000000000000000000011001011100000000000000000000011
000100000000000000000011101111100000000011000000000000
110000000000000011100110101000000000000010000100100000
110000000000000111100000001101000000000000000000000000
.logic_tile 8 8
000000000000000001100000011011000000000000000000000000
000000000000001001000011111011000000000010000000000000
101000000000000000000000000011011010001100110000000000
100000000000000000000011100000110000110011000000000110
011100000000001000000000000101011101000000010000000100
010110000010000001000000000001011001000000000000000000
000000000000000000000010000000000000000000000000000000
000000000000000000010111100000000000000000000000000000
000000000000001111000010010101011101000001000000000000
000000000000000001000111110001011001000000000000000000
000000000000100000000011100011011111001000000000000101
000000000000011001000011101011011011000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
110101000000000000000011100000000000000000000100000000
010000100000000000000000000001000000000010001001000000
.logic_tile 9 8
000000000000000111100010001101000001000001100001000000
000000000000000000100011100001101001000000110000000000
101000000001000000000000000000000000000000000000000000
100000000000000001000011000000000000000000000000000000
110000000000000000000110000001000000000000000000000010
100000000000000000000111011001001111000000010000000000
010000100000000000000000000101000000000000000010000000
000000000000000000000000001001100000000001000001000000
000000000000000000000000000000000000000000000100000000
000000000000000000000000000000000000000010000000000010
000000000000000000000000000000000000000000000100000000
000000000000000000000000000001000000000010000001000000
000000000000000000000111100000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000001101010000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.ramt_tile 10 8
000000000000001000000000000000000000000000
000000010000101011000000000001000000000000
101000001100000000000010001000000000000000
100000010000000000000100001001000000000000
000000001100000000000000001000000000000000
000000000000000000000000000101000000000000
000000001010000111100000001000000000000000
000000000000000000000000001111000000000000
000000001110000101100000010000000000000000
000000001100000000000010101111000000000000
000000000000100000000000000000000000000000
000000000001011001000000000011000000000000
000000000000001000000110100000000000000000
000000000000000101000000001011000000000000
110001000000000000000000010000000000000000
010000100000000000000010100111000000000000
.logic_tile 11 8
001000000000000111100000010000000000000000000100000000
000000000000000000100011110101000000000010000000000000
101000000000000000000000000011100000000001000100000000
100000000000000011000000000001100000000011000000000000
010000000000000111100000000101100000000001000100000000
000001000000000000100000000101100000000011000000000000
000000000000000000000000000001100000000001000100000000
000000000000000011000010000001000000000011000000000000
000000000000000000000000000000000000000000000110000000
000000000000000000000000001001000000000010000000000000
000000000000000000000000011000000000000000000100100000
000000000000000000000011100101000000000010000000000001
000000000010000000000000010111000000000001000100000000
000000000000000000000010100101100000000011000000000000
000000000000100000000000000000000000000000000101100001
000000000001010000000000001111000000000010000000000000
.logic_tile 12 8
000010100000000000000000000011100000000000000000000100
000000000000000011000000000001100000000001000001100000
101000000001000001000111101011000001000001000000000010
100000000000100001000110000011001001000000000000000000
110000000000000011000000000111000001000001010000000000
100000000000000000000000000101001000000010010000000000
010000000100100000000111101001100000000001000000000000
000000000011000000000100000001100000000000000000000000
010000000000000000000000001111000001000000000000000100
000000000000000011000000000111001011000000100000000100
010000000000000101000011001000000000000000000110000000
100000000000000000100100000011000000000010000000000000
000000000000000000000000000000000000000000000000000000
000000000000000011000000000000000000000000000000000000
000010000000000101000000001000000000000000000100000000
000000000000000000100000001001000000000010000010000000
.io_tile 13 8
000000000000000010
000000000000000000
000000011000000000
001000001000000001
000001110010001101
000000001001000000
001100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.io_tile 0 9
000000000000000000
000000000001100000
000000000000000000
000000000000001000
000000000000001100
000000000000001000
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000011010000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.logic_tile 1 9
000000000000000000000010000111100000000000001000000000
000000000000000000000010000000100000000000000000001000
000000000000000111000000000011000001000000001000000000
000000000000000000000000000000101000000000000000000000
000000000000000000000000000111100000000000001000000000
000001000000000000000000000000000000000000000000000000
000000000000000111000000000001000001000000001000000000
000000000000000000000000000000101000000000000000000000
000000000001010000000000010001000001000000001000000000
000000000000000000000011000000101010000000000000000000
000000000000001000000110100011100001000000001000000000
000000000000001111000000000000001000000000000000000000
000000000000000000000000000011100000000000001000000000
000000000000000000000000000000100000000000000000000000
000000000000000000000000010000001000111100000001000010
000000000000000001000010100000000000111100000000000001
.logic_tile 2 9
000000000000000000000000001000000000000010000010000000
000000001010000000000011100011000000000000000000000000
101010100001010001100110000000000000000010000000000100
100000000000000000000011100011000000000000000000000000
010000000000000000000010000000000000000010000000000100
010000000000000000000100001011000000000000000000000000
000100000000000000000000000000000000000000000000000000
000100000000000000000000000000000000000000000000000000
000000000000100111000000010000001110001100110000000000
000000000001010000100011010000000000110011000000100000
000000100000000000000000010101000001001100110100000000
000000000000001001000010000000101000110011000000000010
000000000000000000000000001001100000000000000100000000
000001000000001001000000001011000000000011000010000110
010000000000000000000000000000011001001100110100000000
100010000000000000000000000000011001110011000010000001
.ramb_tile 3 9
000000000000000000000000000000000000000000
000000010000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000001101000000000000000000000000000000
000000000000100000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
001001000000000000000000000000000000000000
000010100000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000001110000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
.logic_tile 4 9
000000000001001011110011000001000000000000000000100000
000000000000000001000111000101100000000010000000000000
101010101100000011100111111111011000000000110000000000
100000000000000001100110111011011011000000100000100000
110000000000000111100011010011011011001111110000000000
010000000000000000100110001001111000011111110000000000
010000100000000000000011100000000000000010000000000000
100001000000000000000011110011000000000000000000000010
000000000000011011100011110001100001000000000100000100
000000001000001011000011110001001011000000100000000000
000010000000000000000111000111001010111000000100000000
000001000000000000000100001001101000010100000000000100
000000000000000101000110100001111000111000000101000000
000000000000000000000100001101011100010100000000000000
110010000001010000000000000000000000000000000000000000
100000000000000000000000000000000000000000000000000000
.logic_tile 5 9
000000000000100101000111111101000000000000000000000100
000000000000000000100110001101100000000001000000000000
000000000000000001000110000101001010010110100001000000
000000001000000001000011000011011111101000010000000000
001000000100000101000111100001000001000000100000000000
000000000000000000100011001101001010000000110000000000
011000000000000001100110001001000000000000010000000001
100000000000000101000010111101101110000000000000000000
011000000010000101100000000001100000000000000000100010
100000000000000000000000001001100000000010000000000100
000000000110000111100000001001101110000011100000000000
000000000000000000100000000011001001000011110000000000
000000000001010101100000001101100001000010110000000010
000000000000101011000011110001001001000001010000100000
000010000000000000000000001101000000000010110000000001
000001001110000000000000000001001111000001010000000000
.logic_tile 6 9
000100000000001000000011100101000000000010010000000000
000100000000000111000010001001101010000001010000000000
101010000000001011100110001101100000000000100001000000
100001000010001011100000000011101100000000000000000100
010000000000001001000110010011000001000010100000000000
000000000000000001100010001111101000000001100000000000
000000000000001011000110001111000000000011000001100011
000000000000001011100010001001000000000001000000000000
001000000000001011000111100101100001000000000000100000
000000000000001011100000000011101100000000100000000001
000000000000010101000000001101100001000010100000000000
000000000000001001100000000001001010000001100000000000
000000000000000011000111100101000000000001100000000100
000000000000000000110100000001001011000010100000000000
000000000000000000000000000000000000000000000100000010
000000000000000000000000001001000000000010000000000000
.logic_tile 7 9
000000000000000111000010010001001010111100000000000000
000000000000001001000010000111011111011100000000100000
101101000000001001100000011001011101010110100001000000
100000100110011011000010110001111010101001000000000000
110000000000000001000010001001000001000001000000000000
010000000000001011100111001101101010000000000000000001
000010100001011001000111011011011010000000110000000000
000000000000101001100110111101001001000000100000000000
000010100000000111000000000111100000000000010000000000
000001000110000101000011111101101000000000000000000000
000000000000000000000010010001111100110000000000001000
000000000000001101000110000011100000100000000000000000
000000000000000101100110000011111111000000000000000000
000000000000000000000000000101101000001000000000000100
010000000000001000000000000000000000000000000110000000
100000000000001011000010100101000000000010000000000000
.logic_tile 8 9
000000000000000000000011011101000001000000010000000000
000000001000101101000011101011101010000000000000000000
101000000000000101000111010001000000000010000000000000
100000000001011011000010100101001111000000000000000000
110000000000001111100110001111011001110100000000000000
010000000000000001000010100001001011101000000000000000
000000000001010001100111111011001001101000010000000000
000000000000100101000111111101011001010110100000000000
000000001100001000000010010101100000000010000010000000
000000000000000101000111111111000000000000000000000000
000100000000000000000000011111101010110110100000000000
000000000000000000000010001101101101101101010000000000
001000001011001000000110111001000000000011000000000000
000000000000100101000110001001101011000001000000000000
010000000000100000000111001000000000000000000100000000
100000000001000000000110101111000000000010000000000001
.logic_tile 9 9
000010100000001000000110011011100001000000000001000000
000001001100000011000011110101101101000010000000000000
000000000000000111100111110111100000000001000001000000
000000000000000000100111110101000000000000000000000000
000000000000001000000111111001000001000000010000000000
000000000000000001000111110011101110000000000000000000
000000000000000111100000011111100001000000100000000000
000000000000000111100011111111101000000000110000000000
000000000000000000000111000101011001000000000000100000
000000000010001011000100001111111001000010000000000000
000000000000001001100111110001001011000010000000000000
000001000000001001000011111011111011000000000000000000
000000000001000000000111000101100000000000110000100000
000000000010000000000100000011001000000001100000000000
000000000000101001100111111101111111000000010000000000
000000001101001001000011110111011100000000000000000010
.ramb_tile 10 9
000000000000000000000000000000000000000000
000000010000000000000000000000000000000000
000000000000100000000000000000000000000000
000000000001000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000010000000000000000000000000000000000000
000001000010000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000100000000000000000000000000000
000000000011000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
001000000000000000000000000000000000000000
000000000001010000000000000000000000000000
.logic_tile 11 9
000000000000000000000000010011000001001100110000000001
000000000000000000000011010000001101110011000000000001
101000000000000000000010101011001111010000000000000000
100000000000000011000010011111111011000000000010000000
010000000000000000000000001111000000000010000000000011
010000000000001111000000000101101100000000000000000000
000000000000000001100000000000000000000000000000000000
000000000000001011010010000000000000000000000000000000
000001000000000011100000011101100000000001000000100000
000010100000000111000011110001000000000000000000000100
000010100000000000000000001001100000000000000010000000
000001000000000000000010001001100000000011000000000000
000000100000000000000111100000000000000000000000000000
000001001010000000000110100000000000000000000000000000
000000001010000000000000010000000000000000000100000000
000000000000000000000011010101000000000010000010000000
.logic_tile 12 9
000000000000001000000000000000000000000000000000000000
000000000010001011000000000000000000000000000000000000
101000000010000001000000001000000000000010000000000000
100000000000010000000000000001000000000000000000000000
010000100000000000000111100000000000000000000101000100
110001000000000101000100000001000000000010000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
010000000000000111000000001000000000000000000100000000
100000000100000000000000000011000000000010000011000000
000001000000101000000000000000000000000000000100000000
000000100001010011010000000101000000000010000000000100
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
010001100000000000000000000000000000000000000100000010
100001100000110000000000000011000000000010000000000000
.io_tile 13 9
000000011000000000
000100001000000000
000001011000000000
000000000000000000
000000000000000100
000000000000000000
000100000000001000
000000000000000000
000000000000000000
000100000000000000
000000000000000010
000000000000110000
000000000000000000
000000000001101001
000000000000000010
000000000000000000
.io_tile 0 10
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.logic_tile 1 10
000000000000000011000000000000000000000010000000000010
000000000000000000100000001101000000000000000000000000
101000000000000001000000001000000000000010000000000010
100000000000000000000000000011000000000000000000000000
010000000000000000000010000101111001010000000000000000
000000000000000000000000001111101011110000000010000000
000000100000000000000010100000000000000000000000000000
000001000000000000000011000000000000000000000000000000
010000000000000000000000001000000000000010000000000000
100000000000100000000000001011000000000000000000000100
000000000000000001000000010000000000000000000000000000
000000000000000000100010100000000000000000000000000000
000000000000000000000010000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000100000000
000000000000000000000000000001000000000010000000000100
.logic_tile 2 10
000000000000000000000000000011000000000000001000000000
000000000000001111000011100000100000000000000000001000
101000000000001111100011100011100001000000001000000000
100000000000001011110000000000001000000000000000000000
010000000000000000000000000001101001001100111100000100
010000000000000000000000000000101010110011000000000001
001000000000000111100000000001101001001100111100000100
000000000000000000100000000000001000110011000000000000
000000000000000000000011100111101001001100111100000000
000000001000000000000000000000101010110011000000000000
000000000000000000000010000001001001001100111100000000
000000000000000001000100000000001000110011000000000000
000000000000000000000000000011101001001100111100000000
000000000000000000000000000000101010110011000000000000
010000000000000000000000000000001000111100000000000000
100000000000000000000010010000000000111100000000000000
.ramt_tile 3 10
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000100000000000000000000000000000
000000000001010000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000010000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
.logic_tile 4 10
000100000000001111100010000101011101001000000000000000
000100000000000111100010010111001100001100000000100000
101000000001010001000111000001111000000011000000000000
100000000000000001000010011011011111000010000000000000
010000000000001101000110011001100000000000000000000000
110000000000001111000011101011000000000001000000000001
010000100000000000000010011101000000000001000000000000
100001000000000001000010001101001011000000000000000000
010000000000001001100011100111011101110000000000000000
100000000000000111000000000111111000010000000000000001
000000000000001001100010011001000001000000010000000000
000000000000000001000011000101001001000000000000000000
000000000000000011000000010111101100110100000000000000
000000000000000000000010100011101001111100000000000000
010000000000000001000000000101111110110011110100100000
100000000110000000000011101001101000110111110000100000
.logic_tile 5 10
000010100000111101000010010111011010001000000000000000
000001000000000001100010001001001011000000000000000000
000000000000000001000010000101100000000001000000000000
000000000000000001000100001001100000000000000001000000
000000000000001001100110110101000000000001000000000000
000000001100000011000110100101000000000000000000000000
110000000000001000000010011011100001000010100000000000
010000000000000001000110000001001001000001110000000001
010000001110001000000000001111100000000000000000000000
100000000000001001010000000001100000000001000000000000
000000000000100000010000000101100000000010000000000010
000000000101011001000000001101100000000011000011000000
000000000000001000000000000101100000000011010000000000
000000000000001001000000000011001001000011000000000000
001000000000000000010000001001000000000000000001000000
000000000000000000000010001101001000000000100000000000
.logic_tile 6 10
000000000010000111000110110101011000000010000000000000
000000000010001001000010001101111000000011000001000000
101001000000000111100111001101100000000000000000000000
100010100000000000100100000001001000000010000000000000
010000000000000101100111110001000000000000000000000000
010000001000000000000010010101100000000001000000000000
000000001100001011100111111101100000000000010000000000
000000000000001101100110001101101001000000110000000000
000000000000000000000010100101111101000000000000000000
000010000000000111000010101111011110010000000000000000
000100000000100011000111001111001100000000010000000000
000000000001010000000000000111011101000000000000000010
000000000000000001100111000111100000000011000000000000
000000000000000000000000000011100000000000000000000100
010000100000001011100000001000000000000000000100000010
100000000000000001100011000011000000000010000000000000
.logic_tile 7 10
000000000000000001100111011001001001000000010000000000
000000000110000000000110000011011000000000000000000100
101000000000001001100010010111000000000000110000000000
100000001010000111000111011101101010000000100000000000
110000000000000000000110111001100000000001000000000000
010000001110001001000010000111000000000000000000000000
000000001110101000000010011011111010000000000010000000
000000000000001001000110000101111111000010000000000000
000000000000000011000000010011011010101100000000000000
000000000000000111100011000011011001001100000000000000
000100000000001000000010011111011001000000000000000000
000000000000000001000110101111011101001000000000000000
000000000000000001000110000101111001000001000000000000
000000000000001001000010001101011101000000000000000000
000000000000000101100000000000000000000000000100000100
000000000000000000000010000111000000000010000000000000
.logic_tile 8 10
000010000000100011100000001101100000000000000001000000
000000000100011001000010001001100000000010000001000000
101000000001001011100111010000000000000010000000100100
100000000000000001000110001101000000000000000000000000
010000000000000001100011110000000000000000000000000000
010000000000000000000011010000000000000000000000000000
000010000000010001100000001001000000000011000000000000
000001100000100000000011100001000000000000000000000100
000000000000000111000000000000011100001100110000000000
000000001000000000000011100000011010110011000000000000
000000000001000001010111101011101101000010000000000000
000000000010000001000010010011111001000000000000000010
000000000000100000000011101111100000000001000000000000
000001000001010000000000000101101011000000000000000000
110100000000100000000000000111011000111001110100000000
010100100111000000000011000011101000111010110000000100
.logic_tile 9 10
000001001100000111100000000011100000000000010000000000
000000000000010111100010100111101001000000110000000000
101000000000001011000111100001100001000001010011000000
100000000000001111100010110001001011000010010000000000
110001000000001111000010100001111001010110100000000001
010000000010000001000111011001011101001001010000000000
000010100000000011000000000101101111010110100000000001
000000001100000000100010110101011110001001010000000000
000000000000000101100000010101000001000001010000100001
000000000100000000110011110101101001000010010000000000
000000000000000011000010001001000001000000000000000000
000000000010010000000110001111001100000010000001000000
000000100110000001000010010111000001000001010000000000
000000000000000000100011011101101001000010010000000001
000100000000000000000000000000000000000000000100000000
000000000000000001000011000011000000000010000010000010
.ramt_tile 10 10
000000000000000000000000000000000000000000
000010000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000001110000000000000000000000000000000
000000000000000000000000000000000000000000
000010000000100000000000000000000000000000
000001000001010000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
.logic_tile 11 10
000000000000000000000010100101000000000000001000000000
000000000000000000000110010000100000000000000000001000
101000000000000111100011100001000000000000001000000000
100000000000000000000011000000101101000000000000000000
110000000000000111000000000000001000111100000000000000
010000000000000000000010010000000000111100000000000010
000000000000000111100000000011100000000010000000000000
000000000000001011100000001111100000000000000000000001
000000000000000011100011111001001100010110100000000000
000000000000001111100111100101101010001001010001000000
000100000000000000000000011011000001000000010000000100
000000000000000000000011100001001001000000000000000000
000000000000000000000000001000000000000000000110000001
000000000000000000000011111001000000000010000001000000
010000000000000000000000001000000000000000000101100000
100000000000000000000000000101000000000010000000100000
.logic_tile 12 10
000000000000000000000000011101000000000000100000000010
000000000000000000000010000111101100000000000000000000
101000000000001000000000001001000000000000010000000010
100000000000000001000000000011101110000000000000000000
110010100000001000000000010111100001001100110000000100
100001000000000001000010000000101011110011000000000000
000000000100000000000111000000000000000000000000000000
000000000010000000010000000000000000000000000000000000
000000000000001000000000001101000000000000000000000100
000000000000000011000000000111101100000001000000000000
000000000000001001100000001001000000000000000000000100
000000000000000111100000000011101110000010000000000000
000000000000001000000000001000000000000000000100000010
000000000000000011000000000001000000000010000000000000
110000000000000001100000010000000000000000000100000000
010000000000000000100011100101000000000010000001000000
.io_tile 13 10
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
001100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.io_tile 0 11
000000000001100000
000000000001100000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
001100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000001
000000000000000000
000000000000000000
.logic_tile 1 11
000000000000000000000000000101100000000000001000000000
000000000000000000000000000000000000000000000000001000
000000000000010011100000000000000001000000001000000000
000000001110000000100000000000001111000000000000000000
000000000000000000000000000000000001000000001000000000
000000000000000000000000000000001110000000000000000000
000000000000000000000000000000000001000000001000000000
000000000000001101000000000000001110000000000000000000
000000000000000000000000010000000000000000001000000000
000000000000000000000010100000001101000000000000000000
000000000000000000000000000000000001000000001000000000
000000000000000000000000000000001000000000000000000000
000000000000000101100000000000000000000000001000000000
000000000000000000000000000000001110000000000000000000
000000000000001101100000010000001000111100000000000000
000000000000000101000010100000000000111100000000000100
.logic_tile 2 11
000000000000000111100010110001011000000000100000100000
000000001010000001000011110111001011000000110000000000
101000000000000111000110001000000000000010000000000000
100000000000000101000000001001000000000000000000000000
010000000000000000000110101000000000000010000000000000
010000000000000000000111010101000000000000000000000000
000000000001000101000010101101111111000010000010000000
000000000000100101000010100101011011000000000000000000
000010000000000000000000011000000000000010000000000000
000000000010000000000011010001000000000000000000000000
000000100000000000000000000000000000000010000000000000
000000000000000000000000001001000000000000000000000000
000000000000000111000000000000000000000010000000000000
000000001010000000100000000001000000000000000000000000
010010000000000000000110000011011010001100110100000000
100001000000000000000000000000111011110011000000000000
.ramb_tile 3 11
000001000001000000000000000000000000000000
000000010000100000000000000000000000000000
000000000110000000000000000000000000000000
000000001000000000000000000000000000000000
000000100000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000010000000000000000000000000000
000000000000000000010000000000000000000000
000000000000000000000000000000000000000000
.logic_tile 4 11
000000000000001111100111001111101010000000100000000000
000000000010000001100110010101101001000000110000000000
000000001100011111000011110101100000000001000000000000
000000000000001101000010001101100000000000000000000100
000000000100001011000110010011111100000010000000000000
000000000000000111100010001101011000000000000000000001
000000100000001111100011011001111000010100100000000000
000001000000000001000011110101101001101000100000000000
000000000000000001000000001001100000000001000000000000
000010101000000000100000001011100000000000000000000000
000000000000000001100110011011101010010000000000000000
000000000000000000000011111101101100110000000000000000
000000000000000000000000001001100000000001000000000000
000000000000001001000000001011000000000000000000000000
001010100010000000000000010011100000000000100000000000
000000000000000000000011110111101000000000110000000000
.logic_tile 5 11
000000001100000111100110001011100000000000000001000000
000000000000000000100110000011101001000000100000000001
101000001110010001100010001101000000000000110001100000
100000000000101101000010111101001001000000100000100000
110001000000001101000110001001100000000001000000000000
010010100000000111000110011101000000000000000000000000
000000000001010001100010011101000000000001000000000000
000000000110100000000011100111100000000000000000100000
000001000000000000000000011011100001000001000000000000
000000000000100000000010001001001010000000000000000001
001100000010001111100111101111001010001001010000000000
000000000000000101000100001001101010010110100000000000
010000001100000000000110101101000000000010000000000010
100010100000000000000000000001100000000011000000000001
000000000000001000000000000000000000000000000100000011
000000000000000101000000000001000000000010000000000000
.logic_tile 6 11
000000000000000001100010001011111111000100000001100000
000000000000000000000010110111111100000000000000000000
101000000001000000000010010011000000000000000000100000
100010000000100000000110100011001101000000100000000000
010000000000001001000110011001000001000010000000000000
010000000000000111000011011101001001000000000010000000
000000000000000001100011100101100000000000000010000000
000000000000000000000010011011000000000010000000000001
000000000000101001100111100001101010000011000000000000
000000000001010101100100001101101110000011100000000000
000000000000011000000110101111100000000000000000000000
000000000000000101000000001101100000000010000000000010
000000000000100001100110000011001010000000100000000000
000000000000000000100100000101011111000000110000000100
010001000100000101100111010000000000000000000101000000
100000101110000000000010101001000000000010000000000000
.logic_tile 7 11
000000000110000011100111010011000000000011000000000011
000000000000000000000110110111100000000010000001000000
101000000000001001100111100000000000000010000001000000
100000000000000111100100000011000000000000000000000000
110000000000000001000000010001101010001000000010000010
110000000000001001100011011011011100000000000010000010
000000000100010101100000000101100000000001000000000010
000000000000100000000000000001000000000000000001000000
000000000000000111000011110111001001101001000100000100
000000000000101001100111001001111111010101000000000110
000000000000000000000111001101011011010101000100000000
000010000000000000000011111001001101101001000001000000
000000000100000001000111111101001001010101000100100000
000000000000001001100111100001011111101001000000100000
000000000000000000000111000011111011010101000100100010
000000000000000000000000000111101101101001000000000010
.logic_tile 8 11
000000000001001001100010100001000000000001000010000000
000000001110000001000100001101000000000000000000000000
101000000000000001100000011011111001100010000000000000
100000000000001101000010001011111010001000100000000000
110010000000100101000110010101100001000000110000000000
010001000101000000100010000001001010000001100000100000
000000000000001001100110001111111011100010000000000000
000000000000000001000010011101111000001000100000000000
000010000000000000000000001000000000000000000100000001
000000000000000000000011100001000000000010000000000000
000000000000000000000111000000000000000000000100000000
000000000000000000000111011101000000000010000000000001
000100000001000000000000000000000000000000000100000000
000100000000100000000000000101000000000010000000000010
010000000000000000000010000000000000000000000101000000
100000000000000000000000001001000000000010000000000000
.logic_tile 9 11
000010000000000000000000000011000000000000001000000000
000000000000000011000000000000000000000000000000001000
000000000001000001100111110000000001000000001000000000
000000000011010000000010100000001111000000000000000000
000000000000010011000110010000001000001100111000100000
000000000000000000000010000000001100110011000000000000
000000000000001000000110010000001001001100111000000000
000000000000000101000011010000001011110011000000000000
000000000000001111000011100000001000111100000001000000
000000000000000111000000000000000000111100000000000000
000000000000000000000000011101001011100010000000000000
000000000000000000000011001001101010001000100000000000
000001000011000000000000001011001101001000010000000010
000000000000000000000000001101011101010010000000000000
000000000000000000000000011001011000000000000000000000
000000000000000000000011000001011011010010000000000000
.ramb_tile 10 11
000000000000100000000000000000000000000000
000000010000010000000000000000000000000000
000000000010000000000000000000000000000000
000000000000000000000000000000000000000000
000010100000000000000000000000000000000000
000011000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000100000000000000000000000000000
000000000001010000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000010000000000000000000000000000000000000
000001000000000000000000000000000000000000
000000000100000000000000000000000000000000
000000000000000000000000000000000000000000
.logic_tile 11 11
000000000110001000000110001000000000000010000000000000
000000001100000011000011010111000000000000000000000000
101000000000000111100010110011000001000000010001000000
100000000000000000100111101001001100000000000000000000
110000000000000000000000000000011010001100110001000000
010000001100000000000000000000000000110011000000000000
000000000000001000000000001001000001000000110000000010
000000000000001101000000001001001101000000010000000000
000000000000001111100000000000001110001100110000000100
000000000000001111000010000000011001110011000000000100
000000000000000011000010101000000000000010000000000001
000000000000010000100000000001000000000000000000000100
000000000000000000000000011000000000000010000000000000
000000001100000000000010101001000000000000000000000000
000000000000000011000000000000000000000000000110000000
000000000000000000100000000011000000000010000000100000
.logic_tile 12 11
000010000000001011000000000001000000000000001000000000
000000000000000011000000000000000000000000000000001000
000000000000001000000000000000000000000000001000000000
000000000000010111000000000000001100000000000000000000
000000000000001000000000000000001000111100000000000000
000000000000000011000000000000000000111100000000000000
000000000000011000000000000000000000000010000000000000
000000000000000111000000001011000000000000000000000000
000000000000000111000111000011100001000000010000000000
000000000000000000000100000001101000000000000000000100
000000000000000000000111100111100001000001000000000000
000000000000000000000100000101101010000000000000100000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000001000000000000000111100000000000000000000000000000
000000100000000000000100000000000000000000000000000000
.io_tile 13 11
000000000000000010
000100000000000000
000000000000000000
000011110000000001
000000000000000010
000000000000110000
001100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000100010
000010110000110000
000000000000000000
000000000000000001
000000000000000010
000000000000000000
.io_tile 0 12
000000000000000010
000100000000000000
000010000000000000
000000110000000001
000000000000000010
000000000000110000
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.logic_tile 1 12
000000000000000000000000000001100000000000001000000000
001000000000000000000000000000000000000000000000001000
000000000000000011100000000000000001000000001000000000
000000000000000000100000000000001100000000000000000000
000000000000000000000000010000001000111100000000000000
000000000000000000000010000000000000111100000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000011100000000000000010000000000000
000000000000000000000100000111000000000000000000000000
000000000000000001000111001000000000000010000000000000
000000000000000000100100001011000000000000000000000100
000000000000000001000000000000001011001100110000000000
000000000000000000100000000000011111110011000000000001
000000000000000000000010000000000000000010000000000000
000000000000000000000000001011000000000000000000000100
.logic_tile 2 12
000000000000000000000111000111011101000100000000000000
000000000000000000010111000011111001000000000001000000
101000000000001000000000000000000000000000000000000000
100000000000000001000011110000000000000000000000000000
010100001110001000000110000111011101000000000000000000
111100000000000011000000000011111001000100000000000001
000000000000000000000110011001100000000001000000000000
001000000110000000000011111101000000000000000000000000
000000000001001000000000010101011111000011100000000000
000000000000001101000010111001001011000001110000000000
000010100000000001000011001011011110000000000000000000
000001000000000000000000000011111001000000010000000001
000000000001000000000000010111011101000000000010000000
000000000000000000000010110011111001000000100000000000
010000000000000000000011000000000000000000000100000000
100000000000000111000000000101000000000010000010000000
.ramt_tile 3 12
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000010000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000010000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
.logic_tile 4 12
000000000000000111000111000101000000000000001000000000
001000000000000000000010000000000000000000000000001000
101000000000101000000000000000000000000000001000000000
100000000000011101000011010000001001000000000000000000
110000000000001101000000000000001001001100111001000000
011000000000000011000010100000001001110011000010000000
000000000000000000000110000000001000111100000010000000
001000000000000000000000000000000000111100000000000000
000000000000010000000010110011011110000001000010000000
000000000000100101000011110101101100000000000000000000
000000000001000011100000000011100000000001000010000000
000000000000100111100000001101000000000000000000000001
000000000000000000000000001001011101000000000000000001
001000001110000000000000000001001011000010000000000000
010000000000000001000000000111101000001100110110000000
100000000000000111100000000000010000110011000000000000
.logic_tile 5 12
000000000000000011100111000101000000000000000000000000
001000000000000001100010011011101110000000010000000000
101000000000001011110000001011100000000001000000000000
100000000000000001100000000001000000000000000000100010
010010000000001000000110011011101001000000000000000000
011001000000000001000010000011111011000100000000000000
000000000000000000000110011001001110000000010000100000
001000000000000001000010000001011010000000000000000000
000000000000000101000010100101100001000001110000000000
000000000000000111000010100011001101000000110000000000
000110100100001000000111011001101011000001000010000100
000100000000001111000010111101011111000000000010100000
000010100000000111100010101001001101000011000000000000
001001000000000000100000001111001110000011010000000000
010000000000100101100111010000000000000000000100000000
100000000000000000000010111011000000000010000000000000
.logic_tile 6 12
000000000000000000000110000101100000000001000000000000
001000000000000000000010000101001011000000000000000000
101000000000000111000011100000011101001100110000000010
100000000000100000000110010000011000110011000000000000
110000000000001101100010100001000000000001000000000000
011000000000000001010100001111100000000000000000000000
000000000000001001100000001001111010000010000000000000
001010000000000001000000001011101101000011000000000000
000000000110000111100110110011000000000001000000000000
000000001000001001000110001001000000000000000000000100
000000000000000000000111010011000001000000000000100000
000000000000000000000111110101001001000000100000100110
000000000000000000000110001000000000000000000101000000
000000000000000000000100001111000000000010000000000000
010000000000000000000110111000000000000000000100000100
100010000000000000000010101111000000000010000000000000
.logic_tile 7 12
000000000000100001000011100001000000000000001000000000
000000000001111001100111110000000000000000000000001000
101000000000000000000000000000000001000000001000000000
100000000000000000000000000000001110000000000000000000
010000000000000101000000000000000000000000001000000000
011000000000000000000000000000001010000000000000000000
000000000000000000000000000000000000000000001000000000
001000100000000000000000000000001111000000000000000000
000000000000000000000000000000001000111100000000000001
000000000000000000000000000000000000111100000000000000
000000000001000000000000000000000000000000000000000000
000000000010000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000100000000
000000000000000000000011000001000000000010000000000000
000000000000001000000000000000000000000000000100000000
000000000000001101000000001001000000000010000000000000
.logic_tile 8 12
010000000000000000000000000001100001001100110000000000
001010100000000101000000000000101100110011000000000000
101000000000000001000010000001100000000001010000000010
100011000000001011000110101111101010000010010000000000
010000000000000000000000000000000000000000000000000000
001000000000000101000000000000000000000000000000000000
000000000000000000000010111101100000000001010000000000
001000000000000101000010001101101010000010010000100000
010000000000001000000110100101100000000001010000000000
000000000100000001000000000011001000000010010000000100
000000000000000001100110001001100001000001010000000000
000000000000000001000000001011001000000010010000100000
001000000000000000000000010000001101001100110000000000
000000000000000000000010100000011011110011000000000000
000000000000000000000000001000000000000000000101000000
000011000000010000000000000011000000000010000000000000
.logic_tile 9 12
000000000000001000000000000111100000000000001000000000
000000000000000011000000000000000000000000000000001000
101000000000000000000000000000000001000000001000000000
100000000000000000000000000000001111000000000000000000
010000000000000000000010000000001000001100111000000000
110000000000000000010000000000001000110011000000000000
000000100000000000000000000000001000111100000000000000
001000000000000000000000000000000000111100000000000000
000000000000000000000000001000000000000010000000100000
000000000000000000000011001011000000000000000000000000
000000000000000011000000000000000000000010000001100000
000000000000000000100010001111000000000000000000000000
000000000000000011000000000111000000000001000000000000
000000000000000111000011011011001110000000000001000000
000000000000001000000000011000000000000000000100000000
000000000000001001000011000011000000000010000000000011
.ramt_tile 10 12
000000000000010000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000010100000000000000000000000000000000000
000001000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000100000000000000000000000000000000000
000001000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
.logic_tile 11 12
000000000000000000000110000001000000000000001000000000
000000000000000101000100000000100000000000000000001000
000000000000000101000111000000000001000000001000000000
000000000000001011100111010000001000000000000000000000
000000000001010000000000000000000000000000001000000000
001000000000100000000000000000001000000000000000000000
000001000000000000000000000000000001000000001000000000
001000000000000000000010100000001011000000000000000000
000000000000000000000000000000000001000000001000000000
000000000000000000000000000000001000000000000000000000
000000000000000000000000000000000001000000001000000000
000000000000000000000000000000001001000000000000000000
000010100000000000000000000000000001000000001000000000
000001000000000000000000000000001001000000000000000000
000000000000000000000000000000001000111100000000000000
000000000000000000000000000000000000111100000000000000
.logic_tile 12 12
000010000000000000000010100001000000000000001000000000
001001000000000000000000000000100000000000000000001000
000000000000000000000000000111100001000000001000000000
000000000000000000000000000000001100000000000000000000
000000000000000011000000000000000000000000001000000000
001000000000000000000000000000001100000000000000000000
000000000000000000000011010000000001000000001000000000
001000000000000000000111010000001111000000000000000000
000000000000001000000000000000000001000000001000000000
000000000000001001000000000000001011000000000000000000
000000000000000101000000000000000001000000001000000000
000000000000000000100000000000001011000000000000000000
000000000000000000000000000000000000000000001000000000
000000000000000000000000000000001010000000000000000000
000000000000000101100000010000001000111100000000000000
001000000000000000100010010000000000111100000000000000
.io_tile 13 12
000000011000000010
000010110000000000
000000000000000000
000000000000000001
000000000000000010
000000000000010000
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000010
000000000000010000
000000000000000000
000000000000000001
000000000000000010
000000000000000000
.io_tile 0 13
000010000000000010
000101010000000000
000000000000000000
000000000000011001
000000000000000010
000000000000010000
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.logic_tile 1 13
000000001010000000000000010000000000000000000000000000
000001000000000000000011100000000000000000000000000000
101000000000000000000000011011100001000011110010000000
100000000000000000000011001011101100000011100000000000
010000000000000001000000001000000000000010000000000000
011000000000000000000000000101000000000000000000000001
000000000000000001000000000000000000000000000000000000
001000000000010000100000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000101000010101011111001000010000000000000
001000000000000000000010101011111100000000010000000000
000000000000000000000000000000000000000010000000000000
000000000000000000000000000101000000000000000000000000
001000000000000000000000000000000000000000000100000000
000000000000000000000000000000000000000010000000000000
.logic_tile 2 13
000000000000000111100000010011001010010110000000000000
000000000000001001000010000101101110101010000000100000
101010000000001101000010100111000001000000100000000100
100001001010000111100111110101101001000000000000000000
010000000000001011000011111101011111101001010000000000
111000000000000111000010111001111010011001010000000000
000000000001000101100000000001000000000000000000000000
001000000000100000000010000001101100000010000000100000
000000000100000111000011100000000000000000000100000000
000000000000000000000000000001000000000010000000000000
000000000000000000000111001000000000000000000100000000
001100000000000000000000001101000000000010000000000000
000000000000000011100011100001100001000011000100000000
000000000010000000000000000111001000000010010000000000
010000000000000000000000011000000000000000000100000000
100000000000000000000011001011000000000010000000000000
.ramb_tile 3 13
001100000000000000000000000000000000000000
000100000000000000000011100000000000000000
000000000000000000000000000000000000000010
000000000000000000000000000000000000000000
010000000000000000000000000000000000000010
010000000000000000000000000000000000000000
000000000000000000000000000000000000000000
001000000000000000000000000000000000000100
000000000000000000000000000000000000000000
000001000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000001000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
.logic_tile 4 13
000001000000001011100111010001101110000001000000000000
000010100010000011100011011111001001000011000001000000
101000000000000101000111011001101101010110000000000001
100000000000000101000111010001001101101010000000000000
110000001110000001000111000000000000000010000000000001
011000001110000000000000000101000000000000000000000000
000000000000000000000011110001100001000000000100000000
001000000000000000000011011001101001000000100000000001
000000000001001000000111000101100000000000000110000000
000000000000000001000010001101101000000000100000000000
000000000000000000000011100001100000000000000100000001
001000000000000000000100001001101101000000100000000000
000100000000001000000110100101100001000000000100000000
001000000000000101000000001101101011000000100000100000
110000000000000000000000000001100000000000000100000000
100000000000000000000000001001101000000000100000000000
.logic_tile 5 13
000000000000000111000000001011100000000001000000000010
001000000000000000000010000101000000000000000000000000
101000000000001011100111001001101001000000010000000000
100000100000001001100000001001011110000000000000000000
111001000000000111100000010011100000000000000000000000
111010000000000000100010000101000000000010000010000000
000000000000000011100000001011000000000001000001000000
001000000000000000100000000001000000000000000000000000
000000000000000001100000010000000000000000000000000000
000000000000001001000011000000000000000000000000000000
000000000000001111000000000111101100000000010000000100
000000000000000011100000001101001100000000000000000000
000000000100000000000011100001000000000001010110000000
000000000000000000000000001011001001000010011000000000
110000000110001001100000000000000000000000000000000000
010000000000000101110000000000000000000000000000000000
.logic_tile 6 13
000000000000000000000000010011111010011100000000000100
000000000000000101000010000101111011111000000000000000
101000000000000000000110000011100000000001000011000011
100000000000000101000000000101000000000000000000000000
110000100000000111100110101001100000000000000000000001
011001000001000101100000000111100000000001000000000000
000000000100001001000110011101100000000000000000000001
001000000000000001100010000011100000000010000000000010
000000000110000001100000010111000000000001000000000000
000000000000000000100011011001000000000000000000000000
000000100000001101000111000001111010000000010000001000
000011100000000001100100000011000000000000000010000000
000000000000000000000000000101100001000001000000000000
000000000000001111000000000001001111000000000000000000
010001000000000101000010101000000000000000000100000000
100000000000000000100000000011000000000010000000000000
.logic_tile 7 13
000100000100000001100010000101100000000010100000000000
000100000000001111000111101111001000000010010000000000
101010100000000111100010100001100000000010000000100000
100001000000000111000110011001100000000000000000000000
110000000000000011100110010101001010000000000000000000
011000001100001011000011101101101010000010000000000000
000000000000001111100010100111101100000000000000000000
001000000000010011100100000001001101000010000000000000
000010000000000000000111001011100000000010100000000000
000000000000001111000111101011101000000010010000000000
000000000000000000000110011001100001000001010100000000
000010100000000011000010000001001001000010011000000001
000000000000001000000010011111000001000001010100000000
000000000000001111000110110101101011000010011000000000
110000000000000111100000000001000001000001010100000000
010000000000110000100000000111101001000010011000000000
.logic_tile 8 13
000010100000011111100011101001100000000010100000000000
000000001100001111000010001011101000000010010000000000
101000000110001111000110010101111010000000000000000000
100000000000000101000011011111101100000000100000000000
010100000000001011000111000101000000000010100000100000
010000000000000101000000000011001011000010010000000000
000000000000100011100110011001100000000010100000100000
001000001000001101000110110101001000000010010000000000
000000000000011111100000010101111001000000000000000100
000000001100100001000010100111101111000100000000000000
000000000000100101100010111011001111000100000000000000
000000000001010111000110001111111100000000000000000010
000001000000000001100110111001000001000001010100000000
000010100000000000000010111001101110000010011000000000
110000000000010011100010111101000001000001010100000000
010000000000100000100010101101001101000010011000000000
.logic_tile 9 13
000000000000000001100000010000011010001100110000000000
000010000000000000000011010000011011110011000000000000
101001000000000000000000010001100001001100110000000000
100010100000000011000011010000101111110011000000000000
110010000000100000000110010111100001000001000101000000
011001000001000011000011011001101000000000100000000000
000000000000000101100000010101100000000000000100000001
001000000000000000000011101101001110000000100000000001
000000000000000000000000010000000000000000000000000000
001010100000000000010011110000000000000000000000000000
000000000000000000000000000101100000000000000100100010
000000000000000000000000001101001010000000100000000001
000000000000001000000000001001000000000011000101000010
000000000000000001000000000101001001000011010000000000
011000000000000000000000010000000000000000000000000000
101000000000000000000010000000000000000000000000000000
.ramb_tile 10 13
000000000000000000000000000000000000000000
000000010000000000000000000000000000000000
000000000000000000000000000000000000000000
000010001100000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000100000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000010000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000010000000000000000000000000000000000000
.logic_tile 11 13
000000000000000000000000000101000000000000001000000000
000000000000000000000000000000000000000000000000001000
101101000000000000000000000000000001000000001000000000
100000001000000000000011010000001010000000000000000000
110000000000000000000000000000001001001100111001000000
100000000000000011000000000000001001110011000000000000
000000000000001000000010000000001000111100000000000000
001000000000011111000000000000000000111100000001000000
001000000000000000000110100000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000011000000000000000000000000000000000010000000000000
000000100000000000000000001011000000000000000000000000
000000000000000000000000001000000000000000000100000000
000000000000000000000000001101000000000010000010000000
110000001110000000000000001000000000000000000100000000
001000000000000011000000000111000000000010000000100000
.logic_tile 12 13
000000000000000000000000001101000000000000000000000000
000000000000000000000010011011001100000010000000000001
101000000000000000000000000000000000000010000000000000
100000000000000000000000001011000000000000000000000000
010000000000000000000000000000000000000000000000000000
010000000000000011000000000000000000000000000000000000
000000000000000000000000001000000000000000000101100000
001000000000000000000000000011000000000010000000100000
000000000000001000000111100000000000000000000000000000
001000000000001111000100000000000000000000000000000000
000000000001000111100000000000000000000000000000000000
000000000000100000000010110000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000100000000000000000000000000000000000000000
001000000001000000000000000000000000000000000000000000
.io_tile 13 13
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000010000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000010000
000000000000000000
000000000000000000
.io_tile 0 14
000000000000000010
000100000000000000
000000000000000000
000000000000000001
000000000000110010
000000000000110000
001100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000110010
000000000000110000
000000000000000000
000000000000000001
000001010000000010
000000110000000000
.logic_tile 1 14
000001000000000111000111010001000000000000001000000000
000010100000000001100011000000100000000000000000001000
000000000000000000000000000101100000000000001000000000
000000000000000000000000000000101000000000000000000000
000000000100000000000000000000000000000000001000000000
000000000000001111000000000000001001000000000000000000
000000000000000000000011100101100000000000001000000000
000000000000000000000110100000101110000000000000000000
000000000000000000000000000000000000000000001000000000
000000000000000000000011000000001000000000000000000000
000000000000000000000000000000000001000000001000000000
000000000000000000000000000000001011000000000000000000
000100000000000000000000000000000000000000001000000000
000000000000000011000000000000001101000000000000000000
000000000001010000000000000000000000000000001000000000
000000000000100000000000000000001010000000000000000000
.logic_tile 2 14
000000000000101101000111101011000000000001010000000100
000000000000011111000100001111101111000010010000000000
101000000000000000000000000000000000000000000000000000
100000000000000000000011100000000000000000000000000000
110100000000001000010000001101000001000001010001000000
000100000000011001000000000111001001000010010000000000
000000000000000011100000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000011000000000000000010000000000000000000000100100000
000001000000000111000000000001000000000010000000000000
000001000000000000000000000011000000000010000100000100
000010000000000000000000001001000000000011000000000000
000100000100100000000111001111000000000010000100000100
000100000001010111000000000101000000000011000000100000
010000000000100011100011000011000000000001000100000000
100000000000000000100000000001000000000000000000000000
.ramt_tile 3 14
000000000000001000000000000000000000000000
000000010000001111000000001101000000000000
101000000000001101100111101000000000000000
100000010000001011100100000111000000000000
000000000000000000000111101000000000000000
000000000000000000000100001111000000000000
000000000000000000000000001000000000000000
000000000000000000000000000001000000000000
000000000000000000000000001000000000000000
000000000000100000000000000111000000000000
000000000000000000000000001000000000000000
000000000000000000000000001111000000000000
000000000000000000000000000000000000000000
000000000000000000000000000001000000000000
010000000000001001100110011000000000000000
010000000000001001100110011001000000000000
.logic_tile 4 14
000000000000001011100111100111100001000001010001000000
000000000000001011010100000011101100000010010010000000
101000000000000101000010100111100000000001010001000000
100000000000001011100010110001101100000010010000000000
111000000000000101000000001101100001000001010001000000
010000000000000000000010011101101001000010010000000000
000000000000000101100111011001000001000001010001000010
000000000000001001100111001001001000000010010000000000
000100000000001111100111100011001001000000000000000000
000100000000001011100011110101111010001100000001000000
000000000000000000000000000111100001000001010000100000
000000000000001001000010001101001010000010010000000000
000000000000000000000000001111100001000001010000000000
000000000000000000000000001011001000000010010010000000
010000000000001001100110010000000000000000000100100000
100000000000001001100110011001000000000010000000000001
.logic_tile 5 14
000000000000000111100110100000000000000000000000000000
000000000000000001100111010000000000000000000001000010
101000000010000001000000000000000000000010000001100010
100000000000000000000000000000000000000000000000000000
000000000000000000000000000001001100101001000010000000
000000000010001001000000001001101000010110100000000001
000000000000000000000110000101100001000011000000000000
000000000000000000000000000001101000000011100001100000
010000000000000011100000000000000000000000000000000000
100000000000000000100000000000000000000000000000000000
000001000010000000000000000111000000000001000000000010
000000000000000000000000000101000000000000000000000000
000000000010000011100000000000000000000000000000000000
000000000000000000100000000000000000000000000000000000
010000000000000000000000000000000000000000000100000000
100000000000000000000000000001000000000010000000000000
.logic_tile 6 14
000000000000000111000111100001000000000000100000000000
000000000000000001000110011001001000000000000000000000
000000000000000001100110001101001110010100000000000000
000000000000000011000011010001001100100100000000000010
000000000000000101000110001101000001000010100000000000
000000000000001011100011010001101101000010010000000000
000000000000000111100000010101111111101000010000000000
000000000000001011000010000001011011010110100000000000
000000000000001111100000011101000001000010100000000000
000001000000000101010010001001001101000010010000000000
000000000000001000000000010101001101010110100000000000
000000000000000111000011000111101001101001000000000000
001000000000001111000000001101100001000010100000000000
000000000000000001100000000011001101000010010000000000
000000000000001000000010001011011110101101110000000000
000000000000000001000000000111111001011101110000000000
.logic_tile 7 14
000000000000000000000011000001011010100000010000000000
000000000000000000000000000101101101010000010000000000
101000000000001000000000010101100000000010000000000010
100000001000000001000011011011000000000000000000000000
000000000000000011000111001011111111110100000000000000
000000000000000000100010100011011111111100100001000100
000000000000000001000000010011000000000000000000000000
000000000000001011100010001101000000000001000000000000
000000000000001000000110011011111011110100000000000000
000100001100000101000010100011011111101100000000000100
000000000000000011100000000111011000000000000000000000
000010000000000001100000001011011111100000000000000000
000010100000001011100000011111100000000000110100000010
000000000000001011100010000001101011000010110000000000
000000000000001001100010111111100000000001010101100001
000000000000001111000011010111001110000010110000000000
.logic_tile 8 14
000000000000001101100000001111000001000011110001000001
000000000000001111100010110111101011000011010000000100
101000100001000101000110100000000000000000000000000000
100001000000000011100010110000000000000000000000000000
010000000000001011000010000011000000000000000000000000
110000001100000001000111011001000000000001000000000000
000000001110000000000010101001100000000001000000000100
000000000000000000010100000001100000000000000000000000
000110100000000101000000001011100000000010100000000000
000101000000000000000000001011101000000010010000000000
000000100000000000000110010001100000000001000000000000
000000000000000001000010000101100000000000000010000000
000010000000000000000000001101000000000001010100000000
000001000000100000000010011111101010000010011000000000
110000000000000011000110100001100001000001010100000000
010000000000000000000000000001001001000010011000000000
.logic_tile 9 14
000010000000100000010110111001111100100000000000000000
000001000001011011000010101101011111000000000000000000
101101000000000011100000001001101100100000000000000001
100000100000000000100010110101101001000000000000000000
110000000000000000000000010111100000000001000000000000
010100000000000000000010101001100000000000000000000000
000000100000000101100111100011100000000001000000000100
000000000000001101000000001011000000000000000000000010
000000000000001011000010110101000000000001000000000000
000000000000000001110110000001100000000000000000100000
000001000000001000000010000000000000000000000000000000
000010100100000011000000000000000000000000000000000000
000000000000000000000011101000000000000010000001000000
000000000000000000000000000101000000000000000000000000
000000000000000000000000010000000000000000000100000010
000000000000000000000010110011000000000010000000000000
.ramt_tile 10 14
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000010000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000001000000000000000000000000000000000000
000010000000000000000000000000000000000000
000000000000000000000000000000000000000000
000010000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
.logic_tile 11 14
000000000000000000000000001000000000000010000000000000
000000000000000111000000000011000000000000000000000010
101000000000001001100011011000000000000010000000000000
100000000000001111000011100001000000000000000000000000
110000000000000000000110001000000000000010000000000000
010000000000000000000000000001000000000000000000000000
000000000000101111000000001001100000000001000000000101
000000000000001101000000001001100000000000000000000000
000000000000000000000011100000000000000010000000000000
000000000000000000000011111101000000000000000000000000
000000100000000000000000001101100000000001000000000000
000001000000000001000000001001000000000000000000000100
000000000000000000000000000101100000000000000000100000
000000000000000000000000000001000000000010000000000010
000000000000000000000000000000000000000000000101000010
000000000000000000000000001011000000000010000000000000
.logic_tile 12 14
000000000000000101100011000001000000000000001000000000
000000000000001101000000000000100000000000000000001000
000000000000101000000000000000000000000000001000000000
000000000001000101000000000000001011000000000000000000
000000000000000011100000010000000000000000001000000000
000000000000000000000010100000001000000000000000000000
000000000000000000000000000000000000000000001000000000
000000000000000000000000000000001100000000000000000000
000000000000000101000000000000000001000000001000000000
000100000000000000100000000000001000000000000000000000
000000000000000000000000000000000000000000001000000000
000000000000000000000000000000001000000000000000000000
000000000000000000000000000000000000000000001000000000
000000000000000000000000000000001010000000000000000000
000000000000100000000000000000001000111100000000000100
000000001000000000000000000000000000111100000000000000
.io_tile 13 14
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.io_tile 0 15
000000000000000000
000000000000000000
000000000000000000
000000000001100000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.logic_tile 1 15
000000000000000001000000000000001000111100000000000100
000000000000000000000010010000000000111100000000010000
101000000000000101100010010000000001001100110000000000
100000000000000000100110110000001000110011000000000000
010000000000000001100111100001111011001100110100000000
110000000000000000000011011001101001101100100000000001
000000000000000000000000000000000000000000000100000010
000000000000001011000000001101000000000010000000000000
000000001110000000000000000000000000000000000000000000
000000000000000001000000000000000000000000000000000000
000000000000000000000000001001001011101100000100000000
000000000000000000000000000001101001111100100000000001
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
010000000000000000000000000001001101101100000100000000
100000000000000000000000000001101001111100100000000001
.logic_tile 2 15
000000000000000000000000010000000000000000000000000000
000001000000000000000011110000000000000000000000000000
101000000000000000000000010000000000000000000000000000
100000000000000000000010110000000000000000000000000000
010000000000000000000000000000000000000000000000000000
010000000000001011000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000001000000000000000001101000000000011000110000010
000000000010000000000000001001000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000001000000000000000000000000000000000000000000
000000001000000000000000000000000000000000000000000000
010000000000000000010000000000000000000000000000000000
100000000000000000000000000000000000000000000000000000
.ramb_tile 3 15
000000000000000000000000000000000000000000
000100010000000000000000000000000000000000
000100000000000000000000000000000000000000
000100000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000100000000000000000000000000000
001000000000000000010000000000000000000000
000000000000000000000000000000000000000000
.logic_tile 4 15
000010000000000000000000000001100001000000001000000000
000001000000000000000000000000001111000000000000000000
101000000000000001000000000000001001001100111000000000
100000000000000101000000000000001011110011000000000000
110000000000000000000000000000001001001100111000000000
000000000010000000000000000000001010110011000000000000
000000000000000101000000000000001000111100000000000001
000000000000000101100010110000000000111100000000000000
110000000000000000000000001000000000000000000100000001
000100000000000000000000000001000000000010000000000000
000100001000000000000000001000000000000000000100000000
000100000000000000000000000101000000000010000000000000
001000000000000000000000001000000000000000000100000000
000000000000000000000000000001000000000010000000000000
010000000000000000000010101000000000000000000110000000
100000000000000000000000000101000000000010000000000000
.logic_tile 5 15
000000000000000000000000000001100000000000001000000000
000000000000000000000000000000000000000000000000001000
000000000000000001100000000000000001000000001000000000
000000000000001101000000000000001100000000000000000000
000000000000001000000000000000000001000000001000000000
000000000000000111000000000000001000000000000000000000
000000000000000000000000000000000000000000001000000000
000000000000000011000000000000001010000000000000000000
000000000001010000000000000000001000111100000010000101
000000000000100000000000000000000000111100000000000000
000000000000000101100000001000000000000010000000000000
000000000000000000000000000101000000000000000000000000
000000000000000000010000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000100000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.logic_tile 6 15
000000000000001000000110011011011100000000100000000000
000000000000000001000010010001001001000000000000000000
101100100000001000000010101111101101000011010000000000
100100100000000111000100001001011010000011000000000000
000000000000000111100000001011100000000000000000100000
000000000000000000100000001101000000000010000000000000
000000000000001000000010101001000000000001000000000001
000000000000001001000110111101100000000000000000000000
001000000000000111000000000111100000000001000000100000
000000000000000000100010100101100000000000000000000000
000000000000001111100011101000000000000010000000000000
000000000000000001000100000111000000000000000000000000
000000000000000000000000000001000001000001110100000000
000000000000000000000000000001101100000010100000000000
000000000000001111100000011000000000000000000100000100
000000000000000001000010001011000000000010000010100000
.logic_tile 7 15
000000000000000000000000011111001101110100000000000000
000000001100001001000010001101111111101100000000000000
101000000110000001000010011111011001010111110001000000
100000000000000101100111000111011101011011110000000000
000001000000001011100010100011101011110000000000000000
000011000000000001000110100001111001100000000000000000
000000000001000001100010010001101101000000000000000000
000000000000000000000011000011011011010000000000000000
000010100000000101000111001001100000000001000010100000
000001000000000000100111110111000000000000000010000000
000000000000001000000010001101000001000000000000000000
000000000000000001000100001001001011000001000000000000
000000000000010101000000001111101011111000110100000001
000000001000100000100011110101111100010100110000000000
000000000000000001000110100001001010000001010100000000
000000000000001101000010110101111100000010110001000101
.logic_tile 8 15
000000000000001001100000000101000001000001000000000000
000000001110000001100000001011101001000000000000000000
101000001110000101000010010101100000000001000000000100
100000000000001011000111100101000000000000000000000000
000000000000000001100110101101100000000000000000000010
000000001000000101100110110001000000000011000001000011
000000000000001001100111001001011011000000000010000000
000000000000000101000000001011011111001000000000000000
000010100000000001100000010111000000001100110000000000
000001000000100000000010010000101110110011000000000000
000000000100000000000111000101001010111001010100101000
000000000000000000000100000011010000111010100000000100
000000000000000001100000000001011000111101010101000010
000000000000000000000010011101001110101100100000000000
000000000000000000000000011000000000000000000100000000
000000000000000000000011101001000000000010000000000000
.logic_tile 9 15
000100000000000111100111100101000000000001000011000000
000110100000001111100100000001000000000000000000000000
101000000000001001000111100011001100001100110000000100
110001000000011101100111100000010000110011000001000000
000000000000001101000000000001000000000001000010000000
000000000000001101000011010001000000000000000000000000
000000000100000000000000010000011001001100110010000000
000001000000000000000010000000011011110011000000000000
000000000000001000000000000101000000000001000010100000
000000000000000111000011100001100000000000000000000001
001000000000100000000000000000000000000000000000000000
000000000001010000000000000000000000000000000000000000
000000000000000000000000000001100000000001000000000000
000000000000000000000000000001000000000000000010000000
000000000000010000000000001101011000111001010100100000
000001000000100000000000001001001001111010100000000101
.ramb_tile 10 15
000000000001000000000000000000000000000000
000000010000000000000000000000000000000000
000001000000000000000000000000000000000000
000010000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000001000000000000000000000000000000000000
000000100000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
.logic_tile 11 15
000000000000000001000111100011000000000000000001000000
000000000000000000100111011001000000000001000000000000
101000000000000000000000000000000000000010000000000000
100000001110000011000010110111000000000000000000000000
000000000001011000000111101001001011111001010100000010
000000000000100001000110110011101101111010100000000000
000000000001000101000000001101001100111001010101000000
000000000000001011000000000111101000111010100000000001
001000000000001011100000001001001011111001010100100000
000000000000000001000000000101101001111010100000100010
000000000000001000000000010000000000000000000000000000
000000000000000111000011110000000000000000000000000000
000000000000001000000011001001001010111001010101000000
000000000000001111000000000001101111111010100000000100
000000000000001000000000001101001100111001010100100000
000000000000001111000000000101101011111010100000000000
.logic_tile 12 15
000001000000000000000000000000000000000010000000000000
000010001100001111000000000001000000000000000000000000
101000000001000000000000001000000000000000000110000000
100000000000000000000000001011000000000010000000000000
110000000000000000000000000000000000000000000000000000
100000000000000000000000000000000000000000000000000000
001000000000000011100000001000000000000000000101000000
000000000000000000000000000011000000000010000000000000
000000000000000011000000001000000000000000000100000000
000000000000000000000000000101000000000010000000000100
000001000000000101100110100000000000000000000100000000
000000100000000000100100000011000000000010000000000100
000000000000001000000000000000000000000000000000000000
000000000000001011000000000000000000000000000000000000
110000000100000000000000000000000000000000000100000000
000000000010000000000000000111000000000010000001000000
.io_tile 13 15
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000001100000
000000000000000000
000000000000000000
000000000000000000
.io_tile 0 16
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.logic_tile 1 16
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
101000000000000000000000000000000000000000000100000000
100000000000000000000000001011000000000010000000000010
110000000000000000000000000000000000000000000100000000
000000000000000000000000001111000000000010000010000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000111000000000000000000000000000000
000000000000000000000100000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000111000000000000000000000100000000
000000000000000000000100001111000000000010000000000100
010000000000000000000000000000000000000000000000000000
100000000000000000000000000000000000000000000000000000
.logic_tile 2 16
000000000000000000000000001001100000000011000000000000
000000000000000000000010010101101100000011100000000001
101000000000000000000110000000000000000000000000000000
100000000000000000000000000000000000000000000000000000
010000000000000000000000000000000000000000000000000000
010000000000000000000000000000000000000000000000000000
000000000000000011000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000001000000000000000000000000000000000000000
000000000000000111000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000001000000000000000000000000000000000000000
000000000000000111000000000000000000000000000000000000
000000000000000000000000000000000000000000000100000000
000000000000000000000000000111000000000010000010000000
.ramt_tile 3 16
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
001000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
.logic_tile 4 16
000000000000000101000000000000000000000000000000000000
000000000000000000000010100000000000000000000000000000
101000000000000001100110010000000000000000000000000000
100000000000000000000010000000000000000000000000000000
000000000000000000000110000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000010000000001101001100110000000000
000000000000000000000000000000011001110011000000000000
000000000000000000000000001001111101100000000000000000
000000000000000000000010001111011001000000000000000100
000000000000000111100110101001000000000000000100000000
000000000001000000000000000011100000000001000000000000
000000000000000000000000001001000000000000000100000000
000000000000000000000000001101000000000001000000000000
000000000000000000000110001101000000000000000100000000
000000000000000000000000000011100000000001000000000000
.logic_tile 5 16
000000000000000000000000010000000000000000000000000000
000000000000000000000010000000000000000000000000000000
101000000000000001100111000001100001001100110000000000
100010000000000001000000000000001101110011000000000000
000000000000000001100110011001100000000001000001000000
000000001100000000000110000101000000000000000000000000
110000000000000111100000000000000000000000000000000000
000000000000000000100000000000000000000000000000000000
000000000000000000000110100000000000000010000000000000
000000000000000000000000001001000000000000000000000000
000000000000000000000110000101000000000001110100000000
000000000000000000000000001011101011000010100000000000
000010100000000000000000000000000000000000000000000000
000001000000000000000000000000000000000000000000000000
000000000000000000000000001101000000000000000100000000
000000000000000000000000001001000000000001000000000000
.logic_tile 6 16
000010100000001001100011111101000000000000000000000000
000001000000001111000010000101100000000010000000000000
000000000000001001100110000101000001000000000000000000
000000000000001011000000000101101100000000100000000000
000000000000001000000111001011001001000011010000000000
000000000000001111000010100001111110000011110000000000
000000000000001011100110011011111001000000000000000000
000000000000001111100010111101001010000000010000000000
000000100000001000000111000001100000000000000000000000
000000000000000001000100000001100000000001000000000010
000000000000000011100000000101101001011100000000000000
000000000000000001100000000101111110111100000000000000
000000000000000000000000000001011001000010110000000000
000000000000000000000000000011001000000001010000000000
000000000000001011100000000111100000000000000000000000
000000000000001001100000001011000000000010000000000000
.logic_tile 7 16
000000000000000000000010110001101100000011010000000000
000000000000000001000010000001001001000010100000000000
101000000000001001100110101011100000000000010000000000
100000000000000001000010011001001010000000110000000000
000000001110001000000010101101100000000000000000000000
000000000000000101000010011011001100000000010000000000
000000000000001000000110110101011001001100000000000000
000000000000000101000010000101111011001000000000000000
000000000000000001100000001101100000000000010000000000
000000000000000111000000001011001100000000000000000000
000000000000001000000000000101100001000000100000000000
000000000000000101000011000111101110000000110000000000
000000000000000000000000001001101010000011100000000000
000000000000000111000000000011111100000011110000000000
010000000000001000000000000001111000010100000100100000
100000000000000101000000001001011011100100000100100000
.logic_tile 8 16
000000000001011111100010010111101000000000000000000000
000000000000100101100011000101111111000001000000000000
101000000000000001100010010011100000000010010001000000
100000000000000000000110001111101100000011110000100000
000000000000001001100110000001100001000000100000000000
000000000000001011000000001111001100000000000000000000
000000000000000000000000000001100000000000000000000000
000000000000000000000000000101100000000010000000000001
000000000000001011000000000011100000000001000000000000
000000000000000001000000001001100000000000000001000000
000000000000101000000110000000011101001100110000000000
000000000000000101000010010000001001110011000000000000
000100000000000000000110110001000000000011000100000000
000100000000000000000011001101001100000001000000000000
000000000000000000000000011001000001000001100100000000
000000000000000000000011001011001111000010100000000000
.logic_tile 9 16
000000000000000000000110100011100000000000001000000000
000000000000000000000000000000000000000000000000001000
101000000000000000000000000011100001000000001000000000
100000000000000000000000000000001101000000000000000000
110000000000000000000000000101101001001100111000100010
100000000000000000000000000000001111110011000001000000
000000000000000001100000000101101001001100111000000000
000000000000001011010000000000001101110011000000000000
000000000000000000000000000000001000111100000000000000
000000000000000000000000000000000000111100000000000000
000000000000000011100111000000000000000010000000000000
000000000000000111100000001001000000000000000000000000
000000000001000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
110000000000001000000111001000000000000000000110000000
000010000000001101000000000111000000000010000000000000
.ramt_tile 10 16
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
.logic_tile 11 16
000000000000000001000000010101100000000000001000000000
000000000000000000100011000000100000000000000000001000
000000000000000000000000000000000000000000001000000000
000000000000000000000000000000001000000000000000000000
000000000000000000000000000000001000001100111000000000
000000000000000000000000000000001100110011000000000000
000000000000000000000000010000001001001100111000000001
000000000000000000000010110000001101110011000000000000
000000000000000000000000000000001001001100111000000010
000000000000000111000000000000001111110011000000000000
000000000000000000000010000000001000001100111000000000
000000000000000000000100000000001111110011000000000001
000000000000000000000000010000001000001100111000000000
000000000000000000000010110000001001110011000000000000
000000000001000000000010000000001000111100000010000000
000000000000000000000100000000000000111100000000000000
.logic_tile 12 16
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.io_tile 13 16
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.io_tile 1 17
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.io_tile 2 17
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.io_tile 3 17
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.io_tile 4 17
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000011000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.io_tile 5 17
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.io_tile 6 17
000000110000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000100
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.io_tile 7 17
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000001100
000000000000001100
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000010000000000000
000001010000000000
.io_tile 8 17
000000000000000000
000000000000000000
000000000000000000
000000000001100000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.io_tile 9 17
000000000000000010
000100000000000000
000001011000000000
000000000000000001
000000000000000001
000000000011000000
001100000000000000
000000000000000000
000000000000000000
000100000000000000
000001111001000010
000000000011000000
000000000000000000
000000000000000001
000000000000000001
000000000000000000
.io_tile 10 17
000000111000000010
000100000000000000
000000000000000000
000000000000000001
000000000000000001
000000000001000000
001100000000000000
000000000000000000
000000000000000000
000100000000000000
000001010001000010
000000001011000000
000000000000000000
000000000000000001
000000000000000001
000000000000000000
.io_tile 11 17
000001110000000010
000100001000000000
000000000000000000
000000000000000001
000000000000000001
000000000001000000
001110000000000000
000011110000000000
000000000000000000
000100000000000000
000000000010000010
000000000011000000
000000000001100000
000000000000000001
000000000000000001
000000000000000000
.io_tile 12 17
000000000000000010
000100000000000000
000010000000000000
000000110000000001
000000000001000001
000000000001000000
001100000000000000
000000000000000000
000010000000000000
000100110000000000
000000000000000010
000000000011000000
000000000000000000
000000000000000001
000000000000000001
000000000000000000
.ram_data 3 13
000000040000000a00000003000000020000003f000100000000001e00000000
000000000000000000010000000100010004009f000000060000000500000003
0000001500e7002900e0001900070005000100a1000600090001000500000000
0005009500010081000800750001009500020081000800950001007500010025
0003009100030075000100950002009100050029000100190008000500010075
0000008100650029000000190007000500650025000000150008007500060095
00000000000000000000000000000000000000000000000000000000000000c0
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
.ram_data 10 5
0000000000000000000000000000000000000000000000000000000000005555
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
.ram_data 10 7
000000010001000100e70058004c0053000100010001000100e0003900e10029
0001000100010001002c002a0019003b000100010001000100e200150006003a
0001000100010001002c002a0019003b000100010001000100e200150006003a
0001000100010001002c002a0019003b000100010001000100e200150006003a
0001000100010001002c002a0019003b000100010001000100e200150006003a
0001000100010001002c002a0019003b000100010001000100e200150006003a
0001000100010001002c002a0019003b000100010001000100e200150006003a
0001000100010001002c002a0019003b000100010001000100e200150006003a
0001000100010001002c002a0019003b000100010001000100e200150006003a
0001000100010001002c002a0019003b000100010001000100e200150006003a
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
.ram_data 3 5
0000000000000000000000000000000000000000000000000000000000005555
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
.sym 1 $auto$rtlil.cc:1692:NotGate$92893$2
.sym 2 RESET$2
.sym 3 $logic_not$top.v:66$10_Y$2
.sym 4 CLK$2$2
.sym 5 $auto$wreduce.cc:310:run$57529[3]$2
.sym 6 $auto$dff2dffe.cc:175:make_patterns_logic$81361$2
.sym 7 $auto$simplemap.cc:250:simplemap_eqne$76135[8]$2
.sym 8 $auto$dff2dffe.cc:175:make_patterns_logic$91425$2
.sym 39 KEYBOARD.COLS_SHADOW[1]
.sym 46 KEYBOARD.COLS_SHADOW[3]
.sym 53 $auto$alumacc.cc:484:replace_alu$57637[7]
.sym 178 $add$top.v:89$20_Y[0]
.sym 179 report_data_wr[1]
.sym 180 report_data_wr[4]
.sym 184 report_data_wr[0]
.sym 293 $add$top.v:89$20_Y[2]
.sym 294 $add$top.v:89$20_Y[3]
.sym 295 $add$top.v:89$20_Y[4]
.sym 296 $add$top.v:89$20_Y[5]
.sym 297 $add$top.v:89$20_Y[6]
.sym 298 $auto$alumacc.cc:484:replace_alu$57662[6]
.sym 405 $sub$top.v:88$19_Y[7]
.sym 406 $3\report_data_adr[7:0][3]
.sym 407 $auto$dff2dffe.cc:175:make_patterns_logic$91580
.sym 408 $sub$top.v:88$19_Y[0]
.sym 409 $3\report_data_adr[7:0][6]
.sym 410 $auto$alumacc.cc:483:replace_alu$57607[5]
.sym 411 $3\report_data_adr[7:0][0]
.sym 412 $3\report_data_adr[7:0][7]
.sym 519 $3\report_data_adr[7:0][2]
.sym 520 $3\report_data_adr[7:0][5]
.sym 521 $3\report_data_adr[7:0][1]
.sym 522 report_data_adr[5]
.sym 523 report_data_adr[4]
.sym 524 report_data_adr[6]
.sym 525 report_data_adr[1]
.sym 526 report_data_adr[3]
.sym 635 $sub$top.v:88$19_Y[3]
.sym 636 $sub$top.v:88$19_Y[4]
.sym 637 $sub$top.v:88$19_Y[5]
.sym 638 $sub$top.v:88$19_Y[6]
.sym 639 $auto$alumacc.cc:484:replace_alu$57677[6]
.sym 640 KEYBOARD.ram_wr
.sym 746 $abc$92916$n680
.sym 748 $auto$alumacc.cc:483:replace_alu$57607[7]
.sym 749 $abc$92916$n681
.sym 750 $auto$alumacc.cc:483:replace_alu$57578[0]
.sym 751 $abc$92916$n952
.sym 752 $3\report_data_adr[7:0][4]
.sym 753 $abc$92916$n679
.sym 830 $auto$simplemap.cc:250:simplemap_eqne$76135[8]
.sym 836 CLK$2
.sym 867 $auto$simplemap.cc:250:simplemap_eqne$80251[1]
.sym 944 CLK$2
.sym 974 $techmap$auto$alumacc.cc:470:replace_alu$57577.$ternary$/usr/bin/../share/yosys/ice40/arith_map.v:42$58789_Y[3]
.sym 975 $auto$alumacc.cc:483:replace_alu$57578[6]
.sym 976 $abc$92916$n785
.sym 978 $auto$alumacc.cc:483:replace_alu$57631[6]
.sym 981 UART.TX_sig_last
.sym 1095 $auto$alumacc.cc:484:replace_alu$57632[7]
.sym 1204 $auto$alumacc.cc:484:replace_alu$57697[6]
.sym 1206 $auto$alumacc.cc:483:replace_alu$57631[1]
.sym 1207 $auto$alumacc.cc:483:replace_alu$57578[2]
.sym 1208 $techmap\I2C_HID_DESC.$add$descriptors.v:36$552_Y[7]
.sym 1209 $auto$alumacc.cc:483:replace_alu$57578[7]
.sym 1289 UART.tx_line
.sym 1317 $auto$simplemap.cc:250:simplemap_eqne$76135[8]
.sym 1318 $auto$alumacc.cc:483:replace_alu$57578[4]
.sym 1321 $abc$92916$n721
.sym 1322 $auto$alumacc.cc:483:replace_alu$57578[5]
.sym 1323 KBD_FREEZE
.sym 1403 I2C.is_read
.sym 1517 KBD_FREEZE
.sym 1522 INT
.sym 1544 $auto$alumacc.cc:484:replace_alu$57579[7]
.sym 1545 $techmap\I2C_HID_DESC.$add$descriptors.v:36$552_Y[0]
.sym 1546 I2C_HID_DESC.real_adress[6]
.sym 1547 I2C_HID_DESC.real_adress[3]
.sym 1549 I2C_HID_DESC.real_adress[0]
.sym 1551 I2C_HID_DESC.real_adress[7]
.sym 1659 I2C_OUT_DESC_MASK[3]
.sym 1660 I2C_OUT_DESC_MASK[5]
.sym 1664 I2C_OUT_DESC_MASK[7]
.sym 1851 $false
.sym 1853 KEYBOARD.ROWS_EN[13]
.sym 1856 $false
.sym 1858 KEYBOARD.ROWS_EN[14]
.sym 1881 $techmap\KEYBOARD.$procmux$5651_Y[5]
.sym 1885 KEYBOARD.report[0][4]
.sym 2002 KBD_COLUMNS[1]$2
.sym 2003 $false
.sym 2004 $false
.sym 2005 $false
.sym 2037 KBD_COLUMNS[3]$2
.sym 2038 $false
.sym 2039 $false
.sym 2040 $false
.sym 2041 $true
.sym 2042 CLK$2$2
.sym 2043 $false
.sym 2140 $true
.sym 2177 $auto$alumacc.cc:483:replace_alu$57607[2]$2
.sym 2178 $false
.sym 2179 $auto$alumacc.cc:483:replace_alu$57607[2]
.sym 2180 $false
.sym 2181 $false
.sym 2182 $auto$alumacc.cc:484:replace_alu$57637[3]
.sym 2184 $true$2
.sym 2185 $auto$alumacc.cc:483:replace_alu$57607[3]
.sym 2187 $auto$alumacc.cc:484:replace_alu$57637[4]
.sym 2189 $false
.sym 2190 $auto$alumacc.cc:483:replace_alu$57607[4]
.sym 2192 $auto$alumacc.cc:484:replace_alu$57637[5]
.sym 2194 $false
.sym 2195 $auto$alumacc.cc:483:replace_alu$57607[5]
.sym 2197 $auto$alumacc.cc:484:replace_alu$57637[6]
.sym 2199 $false
.sym 2200 $auto$alumacc.cc:483:replace_alu$57607[6]
.sym 2202 $auto$alumacc.cc:484:replace_alu$57637[7]$2
.sym 2204 $false
.sym 2205 $auto$alumacc.cc:483:replace_alu$57607[7]
.sym 2211 $auto$alumacc.cc:484:replace_alu$57637[7]$2
.sym 2220 $auto$alumacc.cc:484:replace_alu$57608[7]
.sym 2221 $auto$alumacc.cc:483:replace_alu$57607[4]
.sym 2223 $abc$92916$n623
.sym 2226 KEYBOARD.row_time[0]
.sym 2311 $false
.sym 2312 $true$2
.sym 2313 $3\report_data_adr[7:0][0]
.sym 2314 $false
.sym 2316 $abc$92916$n1012
.sym 2317 $3\report_data_adr[7:0][0]
.sym 2318 $3\report_data_adr[7:0][1]
.sym 2319 $auto$simplemap.cc:250:simplemap_eqne$80251[1]
.sym 2321 $add$top.v:89$20_Y[4]
.sym 2322 $abc$92916$n1033
.sym 2323 $auto$simplemap.cc:250:simplemap_eqne$80251[1]
.sym 2324 $false
.sym 2341 $add$top.v:89$20_Y[0]
.sym 2342 $abc$92916$n997
.sym 2343 $auto$simplemap.cc:250:simplemap_eqne$80251[1]
.sym 2344 $false
.sym 2345 $auto$dff2dffe.cc:175:make_patterns_logic$76937
.sym 2346 CLK$2$2
.sym 2347 $false
.sym 2349 $auto$alumacc.cc:483:replace_alu$57607[3]
.sym 2350 $abc$92916$n727
.sym 2351 $add$top.v:89$20_Y[7]
.sym 2352 $auto$simplemap.cc:309:simplemap_lut$68590[1]
.sym 2353 $abc$92916$n1013_1
.sym 2354 $abc$92916$n1012
.sym 2355 KEYBOARD.row_time[15]
.sym 2396 $true
.sym 2433 $3\report_data_adr[7:0][0]$2
.sym 2434 $false
.sym 2435 $3\report_data_adr[7:0][0]
.sym 2436 $false
.sym 2437 $false
.sym 2438 $auto$alumacc.cc:484:replace_alu$57662[1]
.sym 2440 $false
.sym 2441 $3\report_data_adr[7:0][1]
.sym 2443 $auto$alumacc.cc:484:replace_alu$57662[2]
.sym 2444 $false
.sym 2445 $false
.sym 2446 $3\report_data_adr[7:0][2]
.sym 2447 $auto$alumacc.cc:484:replace_alu$57662[1]
.sym 2448 $auto$alumacc.cc:484:replace_alu$57662[3]
.sym 2449 $false
.sym 2450 $false
.sym 2451 $3\report_data_adr[7:0][3]
.sym 2452 $auto$alumacc.cc:484:replace_alu$57662[2]
.sym 2453 $auto$alumacc.cc:484:replace_alu$57662[4]
.sym 2454 $false
.sym 2455 $false
.sym 2456 $3\report_data_adr[7:0][4]
.sym 2457 $auto$alumacc.cc:484:replace_alu$57662[3]
.sym 2458 $auto$alumacc.cc:484:replace_alu$57662[5]
.sym 2459 $false
.sym 2460 $false
.sym 2461 $3\report_data_adr[7:0][5]
.sym 2462 $auto$alumacc.cc:484:replace_alu$57662[4]
.sym 2463 $auto$alumacc.cc:484:replace_alu$57662[6]$2
.sym 2464 $false
.sym 2465 $false
.sym 2466 $3\report_data_adr[7:0][6]
.sym 2467 $auto$alumacc.cc:484:replace_alu$57662[5]
.sym 2472 $auto$alumacc.cc:484:replace_alu$57662[6]$2
.sym 2476 $abc$92916$n1047_1
.sym 2477 $techmap\UART.$sub$uart.v:32$535_Y[3]
.sym 2479 $abc$92916$n1040
.sym 2480 $abc$92916$n1197_1
.sym 2481 report_data_wr[6]
.sym 2482 report_data_wr[3]
.sym 2483 report_data_wr[5]
.sym 2562 $false
.sym 2563 init_ram_cnt[7]
.sym 2564 $true$2
.sym 2565 $auto$alumacc.cc:484:replace_alu$57677[6]
.sym 2567 $abc$92916$n952
.sym 2568 $sub$top.v:88$19_Y[3]
.sym 2569 $false
.sym 2570 $false
.sym 2572 $techmap\KEYBOARD.$procmux$7960_Y
.sym 2573 $auto$rtlil.cc:1692:NotGate$92893$2
.sym 2574 RESET$2
.sym 2575 $false
.sym 2577 $false
.sym 2578 init_ram_cnt[0]
.sym 2579 $true$2
.sym 2580 $true$2
.sym 2582 $abc$92916$n952
.sym 2583 $sub$top.v:88$19_Y[6]
.sym 2584 $false
.sym 2585 $false
.sym 2587 I2C.byte_counter[5]
.sym 2588 $false
.sym 2589 $false
.sym 2590 $false
.sym 2592 $abc$92916$n952
.sym 2593 $sub$top.v:88$19_Y[0]
.sym 2594 $false
.sym 2595 $false
.sym 2597 $abc$92916$n952
.sym 2598 $sub$top.v:88$19_Y[7]
.sym 2599 $false
.sym 2600 $false
.sym 2604 $add$top.v:184$103_Y[0]
.sym 2605 $abc$92916$n961
.sym 2606 $abc$92916$n958
.sym 2607 $add$top.v:184$103_Y[7]
.sym 2608 $abc$92916$n995
.sym 2609 report_data_adr[7]
.sym 2610 report_data_adr[2]
.sym 2611 report_data_adr[0]
.sym 2690 $abc$92916$n952
.sym 2691 init_ram_cnt[1]
.sym 2692 init_ram_cnt[2]
.sym 2693 $false
.sym 2695 $abc$92916$n952
.sym 2696 $sub$top.v:88$19_Y[5]
.sym 2697 $false
.sym 2698 $false
.sym 2700 $abc$92916$n952
.sym 2701 init_ram_cnt[1]
.sym 2702 $false
.sym 2703 $false
.sym 2705 $3\report_data_adr[7:0][5]
.sym 2706 $abc$92916$n981
.sym 2707 $auto$simplemap.cc:250:simplemap_eqne$80251[1]
.sym 2708 $false
.sym 2710 $3\report_data_adr[7:0][4]
.sym 2711 $abc$92916$n974
.sym 2712 $auto$simplemap.cc:250:simplemap_eqne$80251[1]
.sym 2713 $false
.sym 2715 $3\report_data_adr[7:0][6]
.sym 2716 $abc$92916$n988
.sym 2717 $auto$simplemap.cc:250:simplemap_eqne$80251[1]
.sym 2718 $false
.sym 2720 $3\report_data_adr[7:0][1]
.sym 2721 $abc$92916$n957
.sym 2722 $auto$simplemap.cc:250:simplemap_eqne$80251[1]
.sym 2723 $false
.sym 2725 $3\report_data_adr[7:0][3]
.sym 2726 $abc$92916$n964
.sym 2727 $auto$simplemap.cc:250:simplemap_eqne$80251[1]
.sym 2728 $false
.sym 2729 $auto$dff2dffe.cc:175:make_patterns_logic$76062
.sym 2730 CLK$2$2
.sym 2731 $false
.sym 2734 init_ram_cnt[2]
.sym 2735 init_ram_cnt[3]
.sym 2736 init_ram_cnt[4]
.sym 2737 init_ram_cnt[5]
.sym 2738 init_ram_cnt[6]
.sym 2739 $auto$alumacc.cc:484:replace_alu$57665[6]
.sym 2780 $true
.sym 2817 init_ram_cnt[1]$3
.sym 2818 $false
.sym 2819 init_ram_cnt[1]
.sym 2820 $false
.sym 2821 $false
.sym 2822 $auto$alumacc.cc:484:replace_alu$57677[2]
.sym 2824 init_ram_cnt[2]
.sym 2825 $true$2
.sym 2827 $auto$alumacc.cc:484:replace_alu$57677[3]
.sym 2828 $false
.sym 2829 init_ram_cnt[3]
.sym 2830 $false
.sym 2831 $auto$alumacc.cc:484:replace_alu$57677[2]
.sym 2832 $auto$alumacc.cc:484:replace_alu$57677[4]
.sym 2833 $false
.sym 2834 init_ram_cnt[4]
.sym 2835 $true$2
.sym 2836 $auto$alumacc.cc:484:replace_alu$57677[3]
.sym 2837 $auto$alumacc.cc:484:replace_alu$57677[5]
.sym 2838 $false
.sym 2839 init_ram_cnt[5]
.sym 2840 $true$2
.sym 2841 $auto$alumacc.cc:484:replace_alu$57677[4]
.sym 2842 $auto$alumacc.cc:484:replace_alu$57677[6]$2
.sym 2843 $false
.sym 2844 init_ram_cnt[6]
.sym 2845 $true$2
.sym 2846 $auto$alumacc.cc:484:replace_alu$57677[5]
.sym 2851 $auto$alumacc.cc:484:replace_alu$57677[6]$2
.sym 2853 $techmap\KEYBOARD.$procmux$7960_Y
.sym 2854 $false
.sym 2855 $false
.sym 2856 $false
.sym 2857 $auto$dff2dffe.cc:175:make_patterns_logic$91580
.sym 2858 CLK$2$2
.sym 2859 $false
.sym 2862 $add$top.v:184$103_Y[2]
.sym 2863 $add$top.v:184$103_Y[3]
.sym 2864 $add$top.v:184$103_Y[4]
.sym 2865 $add$top.v:184$103_Y[5]
.sym 2866 $add$top.v:184$103_Y[6]
.sym 2867 $auto$alumacc.cc:484:replace_alu$57656[6]
.sym 2946 init_ram_cnt[3]
.sym 2947 init_ram_cnt[1]
.sym 2948 init_ram_cnt[0]
.sym 2949 init_ram_cnt[2]
.sym 2956 I2C.byte_counter[7]
.sym 2957 $false
.sym 2958 $false
.sym 2959 $false
.sym 2961 init_ram_cnt[4]
.sym 2962 init_ram_cnt[5]
.sym 2963 init_ram_cnt[6]
.sym 2964 $false
.sym 2966 init_ram_cnt[0]
.sym 2967 $false
.sym 2968 $false
.sym 2969 $false
.sym 2971 $auto$alumacc.cc:484:replace_alu$57579[7]
.sym 2972 $abc$92916$n681
.sym 2973 init_ram_cnt[7]
.sym 2974 $abc$92916$n680
.sym 2976 $abc$92916$n952
.sym 2977 $sub$top.v:88$19_Y[4]
.sym 2978 $false
.sym 2979 $false
.sym 2981 $abc$92916$n680
.sym 2982 $abc$92916$n681
.sym 2983 init_ram_cnt[7]
.sym 2984 $false
.sym 2988 $auto$alumacc.cc:470:replace_alu$57595.BB[2]
.sym 2989 $auto$alumacc.cc:483:replace_alu$57607[0]
.sym 2990 $auto$alumacc.cc:483:replace_alu$57607[2]
.sym 2992 $8\report_data_adr[7:0][7]
.sym 2993 init_ram_cnt[0]
.sym 2994 init_ram_cnt[1]
.sym 2995 init_ram_cnt[7]
.sym 3036 $true
.sym 3073 init_ram_cnt[1]$2
.sym 3074 $false
.sym 3075 init_ram_cnt[1]
.sym 3076 $false
.sym 3077 $false
.sym 3078 $auto$alumacc.cc:484:replace_alu$57590[2]
.sym 3080 init_ram_cnt[2]
.sym 3081 $true$2
.sym 3083 $auto$alumacc.cc:484:replace_alu$57590[3]
.sym 3085 init_ram_cnt[3]
.sym 3086 $false
.sym 3088 $auto$alumacc.cc:484:replace_alu$57590[4]
.sym 3090 init_ram_cnt[4]
.sym 3091 $true$2
.sym 3093 $auto$alumacc.cc:484:replace_alu$57590[5]
.sym 3095 init_ram_cnt[5]
.sym 3096 $true$2
.sym 3098 $auto$alumacc.cc:484:replace_alu$57590[6]
.sym 3100 init_ram_cnt[6]
.sym 3101 $true$2
.sym 3103 $auto$simplemap.cc:250:simplemap_eqne$80251[1]$2
.sym 3105 init_ram_cnt[7]
.sym 3106 $false
.sym 3112 $auto$simplemap.cc:250:simplemap_eqne$80251[1]$2
.sym 3118 I2C_INPUT_LEN[2]
.sym 3119 I2C_INPUT_LEN[3]
.sym 3120 I2C_INPUT_LEN[4]
.sym 3121 I2C_INPUT_LEN[5]
.sym 3122 I2C_INPUT_LEN[6]
.sym 3123 $auto$alumacc.cc:484:replace_alu$57674[6]
.sym 3202 init_ram_cnt[3]
.sym 3203 $false
.sym 3204 $false
.sym 3205 $false
.sym 3207 init_ram_cnt[6]
.sym 3208 $false
.sym 3209 $false
.sym 3210 $false
.sym 3212 I2C.is_read
.sym 3213 $auto$dff2dffe.cc:175:make_patterns_logic$73101
.sym 3214 $auto$simplemap.cc:250:simplemap_eqne$80251[1]
.sym 3215 RESET$2
.sym 3222 I2C_INPUT_LEN[6]
.sym 3223 $false
.sym 3224 $false
.sym 3225 $false
.sym 3237 UART_WR
.sym 3238 $false
.sym 3239 $false
.sym 3240 $false
.sym 3241 RESET$2
.sym 3242 CLK$2$2
.sym 3243 $false
.sym 3244 $auto$dff2dffe.cc:175:make_patterns_logic$81361
.sym 3245 $auto$alumacc.cc:483:replace_alu$57631[7]
.sym 3246 $auto$alumacc.cc:483:replace_alu$57631[5]
.sym 3247 $abc$92916$n798
.sym 3248 $auto$alumacc.cc:483:replace_alu$57631[4]
.sym 3249 $auto$alumacc.cc:483:replace_alu$57631[3]
.sym 3250 $auto$alumacc.cc:483:replace_alu$57631[2]
.sym 3251 I2C_INPUT_LEN[7]
.sym 3292 $true
.sym 3329 $auto$alumacc.cc:483:replace_alu$57631[1]$2
.sym 3330 $false
.sym 3331 $auto$alumacc.cc:483:replace_alu$57631[1]
.sym 3332 $false
.sym 3333 $false
.sym 3334 $auto$alumacc.cc:484:replace_alu$57632[2]
.sym 3336 $false
.sym 3337 $auto$alumacc.cc:483:replace_alu$57631[2]
.sym 3339 $auto$alumacc.cc:484:replace_alu$57632[3]
.sym 3341 $false
.sym 3342 $auto$alumacc.cc:483:replace_alu$57631[3]
.sym 3344 $auto$alumacc.cc:484:replace_alu$57632[4]
.sym 3346 $false
.sym 3347 $auto$alumacc.cc:483:replace_alu$57631[4]
.sym 3349 $auto$alumacc.cc:484:replace_alu$57632[5]
.sym 3351 $false
.sym 3352 $auto$alumacc.cc:483:replace_alu$57631[5]
.sym 3354 $auto$alumacc.cc:484:replace_alu$57632[6]
.sym 3356 $false
.sym 3357 $auto$alumacc.cc:483:replace_alu$57631[6]
.sym 3359 $auto$alumacc.cc:484:replace_alu$57632[7]$2
.sym 3361 $false
.sym 3362 $auto$alumacc.cc:483:replace_alu$57631[7]
.sym 3368 $auto$alumacc.cc:484:replace_alu$57632[7]$2
.sym 3372 $abc$92916$n799_1
.sym 3374 $abc$92916$n805
.sym 3375 $auto$dff2dffe.cc:175:make_patterns_logic$84280
.sym 3376 $abc$92916$n814_1
.sym 3377 $abc$92916$n803
.sym 3378 $abc$92916$n801
.sym 3379 last_uart_active
.sym 3420 $true
.sym 3457 I2C.byte_counter[5]$2
.sym 3458 $false
.sym 3459 I2C.byte_counter[5]
.sym 3460 $false
.sym 3461 $false
.sym 3462 $auto$alumacc.cc:484:replace_alu$57697[6]$2
.sym 3464 $false
.sym 3465 I2C.byte_counter[6]
.sym 3471 $auto$alumacc.cc:484:replace_alu$57697[6]$2
.sym 3478 I2C_INPUT_LEN[1]
.sym 3479 $false
.sym 3480 $false
.sym 3481 $false
.sym 3483 init_ram_cnt[2]
.sym 3484 $false
.sym 3485 $false
.sym 3486 $false
.sym 3488 $false
.sym 3489 $false
.sym 3490 I2C.byte_counter[7]
.sym 3491 $auto$alumacc.cc:484:replace_alu$57697[6]
.sym 3493 init_ram_cnt[7]
.sym 3494 $false
.sym 3495 $false
.sym 3496 $false
.sym 3500 $abc$92916$n1070
.sym 3501 $abc$92916$n1072
.sym 3502 $abc$92916$n716
.sym 3503 $auto$dff2dffe.cc:175:make_patterns_logic$72910
.sym 3504 I2C_HID_DESC.real_adress[1]
.sym 3505 I2C_HID_DESC.real_adress[4]
.sym 3506 I2C_HID_DESC.real_adress[5]
.sym 3507 I2C_HID_DESC.real_adress[2]
.sym 3591 I2C_OUTPUT_TYPE[2]
.sym 3592 I2C_OUTPUT_TYPE[1]
.sym 3593 I2C_OUTPUT_TYPE[0]
.sym 3594 $false
.sym 3596 init_ram_cnt[4]
.sym 3597 $false
.sym 3598 $false
.sym 3599 $false
.sym 3611 I2C_OUTPUT_TYPE[2]
.sym 3612 I2C_OUTPUT_TYPE[1]
.sym 3613 I2C_OUTPUT_TYPE[0]
.sym 3614 $auto$alumacc.cc:484:replace_alu$57632[7]
.sym 3616 init_ram_cnt[5]
.sym 3617 $false
.sym 3618 $false
.sym 3619 $false
.sym 3621 $false
.sym 3622 $false
.sym 3623 $false
.sym 3624 $false
.sym 3625 $auto$dff2dffe.cc:175:make_patterns_logic$73101
.sym 3626 CLK$2$2
.sym 3627 $false
.sym 3628 $abc$92916$n1103
.sym 3630 $abc$92916$n1097
.sym 3632 I2C_OUT_DESC_MASK[4]
.sym 3633 I2C_OUTPUT_TYPE[0]
.sym 3634 I2C_OUTPUT_TYPE[1]
.sym 3635 I2C_OUTPUT_TYPE[2]
.sym 3676 $true
.sym 3713 $auto$alumacc.cc:483:replace_alu$57578[0]$2
.sym 3714 $false
.sym 3715 $auto$alumacc.cc:483:replace_alu$57578[0]
.sym 3716 $false
.sym 3717 $false
.sym 3718 $auto$alumacc.cc:484:replace_alu$57579[1]
.sym 3720 $true$2
.sym 3721 $sub$top.v:88$19_Y[1]
.sym 3723 $auto$alumacc.cc:484:replace_alu$57579[2]
.sym 3725 $false
.sym 3726 $auto$alumacc.cc:483:replace_alu$57578[2]
.sym 3728 $auto$alumacc.cc:484:replace_alu$57579[3]
.sym 3730 $true$2
.sym 3731 $techmap$auto$alumacc.cc:470:replace_alu$57577.$ternary$/usr/bin/../share/yosys/ice40/arith_map.v:42$58789_Y[3]
.sym 3733 $auto$alumacc.cc:484:replace_alu$57579[4]
.sym 3735 $false
.sym 3736 $auto$alumacc.cc:483:replace_alu$57578[4]
.sym 3738 $auto$alumacc.cc:484:replace_alu$57579[5]
.sym 3740 $false
.sym 3741 $auto$alumacc.cc:483:replace_alu$57578[5]
.sym 3743 $auto$alumacc.cc:484:replace_alu$57579[6]
.sym 3745 $false
.sym 3746 $auto$alumacc.cc:483:replace_alu$57578[6]
.sym 3748 $auto$alumacc.cc:484:replace_alu$57579[7]$2
.sym 3750 $false
.sym 3751 $auto$alumacc.cc:483:replace_alu$57578[7]
.sym 3760 I2C_INPUT_LEN[1]
.sym 3845 $auto$alumacc.cc:484:replace_alu$57579[7]$2
.sym 3847 $false
.sym 3848 $false
.sym 3849 I2C.byte_counter[0]
.sym 3850 $false
.sym 3852 I2C_OUTPUT_TYPE[1]
.sym 3853 I2C_OUTPUT_TYPE[0]
.sym 3854 I2C.byte_counter[5]
.sym 3855 I2C.byte_counter[6]
.sym 3857 I2C.byte_counter[3]
.sym 3858 $false
.sym 3859 $false
.sym 3860 $false
.sym 3867 I2C.byte_counter[0]
.sym 3868 I2C_OUTPUT_TYPE[1]
.sym 3869 I2C_OUTPUT_TYPE[0]
.sym 3870 $techmap\I2C_HID_DESC.$add$descriptors.v:36$552_Y[0]
.sym 3877 I2C.byte_counter[7]
.sym 3878 I2C_OUTPUT_TYPE[1]
.sym 3879 I2C_OUTPUT_TYPE[0]
.sym 3880 $techmap\I2C_HID_DESC.$add$descriptors.v:36$552_Y[7]
.sym 3881 $auto$dff2dffe.cc:158:make_patterns_logic$92134
.sym 3882 CLK$2$2
.sym 3883 $logic_not$top.v:66$10_Y$2
.sym 3884 $auto$dff2dffe.cc:158:make_patterns_logic$85062
.sym 3891 I2C.i2c_start_latency
.sym 3975 $2\I2C_OUT_DESC_MASK[7:0][7]
.sym 3976 $false
.sym 3977 $false
.sym 3978 $false
.sym 3980 $2\I2C_OUT_DESC_MASK[7:0][7]
.sym 3981 $false
.sym 3982 $false
.sym 3983 $false
.sym 4000 $2\I2C_OUT_DESC_MASK[7:0][7]
.sym 4001 $false
.sym 4002 $false
.sym 4003 $false
.sym 4009 $auto$dff2dffe.cc:175:make_patterns_logic$81361$2
.sym 4010 CLK$2$2
.sym 4011 $logic_not$top.v:66$10_Y$2
.sym 4100 $false
.sym 4102 KEYBOARD.ROWS_EN[15]
.sym 4210 $auto$rtlil.cc:1692:NotGate$92753
.sym 4211 KEYBOARD.kbd_code_hid[5]
.sym 4212 $false
.sym 4213 $false
.sym 4230 KEYBOARD.report[0][4]
.sym 4231 $auto$rtlil.cc:1692:NotGate$92753
.sym 4232 $abc$92916$n1201
.sym 4233 $false
.sym 4239 $auto$dff2dffe.cc:175:make_patterns_logic$91231
.sym 4240 CLK$2$2
.sym 4241 $logic_not$top.v:66$10_Y$2
.sym 4318 $true
.sym 4355 $auto$alumacc.cc:483:replace_alu$57607[0]$2
.sym 4356 $false
.sym 4357 $auto$alumacc.cc:483:replace_alu$57607[0]
.sym 4358 $false
.sym 4359 $false
.sym 4360 $auto$alumacc.cc:484:replace_alu$57608[1]
.sym 4362 $true$2
.sym 4363 $auto$simplemap.cc:309:simplemap_lut$68590[1]
.sym 4365 $auto$alumacc.cc:484:replace_alu$57608[2]
.sym 4367 $false
.sym 4368 $auto$alumacc.cc:483:replace_alu$57607[2]
.sym 4370 $auto$alumacc.cc:484:replace_alu$57608[3]
.sym 4372 $false
.sym 4373 $auto$alumacc.cc:483:replace_alu$57607[3]
.sym 4375 $auto$alumacc.cc:484:replace_alu$57608[4]
.sym 4377 $false
.sym 4378 $auto$alumacc.cc:483:replace_alu$57607[4]
.sym 4380 $auto$alumacc.cc:484:replace_alu$57608[5]
.sym 4382 $false
.sym 4383 $auto$alumacc.cc:483:replace_alu$57607[5]
.sym 4385 $auto$alumacc.cc:484:replace_alu$57608[6]
.sym 4387 $false
.sym 4388 $auto$alumacc.cc:483:replace_alu$57607[6]
.sym 4390 $auto$alumacc.cc:484:replace_alu$57608[7]$2
.sym 4392 $false
.sym 4393 $auto$alumacc.cc:483:replace_alu$57607[7]
.sym 4475 $auto$alumacc.cc:484:replace_alu$57608[7]$2
.sym 4477 I2C.byte_counter[4]
.sym 4478 $false
.sym 4479 $false
.sym 4480 $false
.sym 4487 KEYBOARD.row_time[10]
.sym 4488 KEYBOARD.row_time[11]
.sym 4489 $false
.sym 4490 $false
.sym 4502 $false
.sym 4503 $true$2
.sym 4504 KEYBOARD.row_time[0]
.sym 4505 $false
.sym 4511 RESET$2
.sym 4512 CLK$2$2
.sym 4513 $auto$rtlil.cc:1692:NotGate$92893$2
.sym 4593 I2C.byte_counter[3]
.sym 4594 $false
.sym 4595 $false
.sym 4596 $false
.sym 4598 $auto$alumacc.cc:484:replace_alu$57608[7]
.sym 4599 $abc$92916$n728
.sym 4600 $auto$alumacc.cc:484:replace_alu$57637[7]
.sym 4601 $false
.sym 4603 $false
.sym 4604 $false
.sym 4605 $3\report_data_adr[7:0][7]
.sym 4606 $auto$alumacc.cc:484:replace_alu$57662[6]
.sym 4608 I2C.byte_counter[1]
.sym 4609 $false
.sym 4610 $false
.sym 4611 $false
.sym 4613 KEYBOARD.report[0][1]
.sym 4614 $abc$92916$n1009
.sym 4615 $abc$92916$n1014
.sym 4616 $abc$92916$n1017_1
.sym 4618 KEYBOARD.report[0][1]
.sym 4619 $abc$92916$n1010_1
.sym 4620 $abc$92916$n1013_1
.sym 4621 $2\INT[0:0]
.sym 4623 $false
.sym 4624 $false
.sym 4625 KEYBOARD.row_time[15]
.sym 4626 $auto$alumacc.cc:484:replace_alu$57724[14]
.sym 4627 RESET$2
.sym 4628 CLK$2$2
.sym 4629 $auto$rtlil.cc:1692:NotGate$92893$2
.sym 4630 REPORT_DATA.r_data[0]
.sym 4632 REPORT_DATA.r_data[1]
.sym 4634 REPORT_DATA.r_data[2]
.sym 4636 REPORT_DATA.r_data[3]
.sym 4704 KEYBOARD.report[0][6]
.sym 4705 $abc$92916$n1010_1
.sym 4706 $abc$92916$n1048
.sym 4707 $2\INT[0:0]
.sym 4709 $false
.sym 4710 UART.tx_clk_counter[3]
.sym 4711 $true$2
.sym 4712 $auto$alumacc.cc:484:replace_alu$57727[2]
.sym 4719 KEYBOARD.report[0][5]
.sym 4720 $abc$92916$n1010_1
.sym 4721 $abc$92916$n1041
.sym 4722 $2\INT[0:0]
.sym 4724 KEYBOARD.kbd_code_hid[2]
.sym 4725 KEYBOARD.kbd_code_hid[1]
.sym 4726 KEYBOARD.kbd_code_hid[0]
.sym 4727 $false
.sym 4729 $add$top.v:89$20_Y[6]
.sym 4730 $abc$92916$n1047_1
.sym 4731 $auto$simplemap.cc:250:simplemap_eqne$80251[1]
.sym 4732 $false
.sym 4734 $add$top.v:89$20_Y[3]
.sym 4735 $abc$92916$n1026
.sym 4736 $auto$simplemap.cc:250:simplemap_eqne$80251[1]
.sym 4737 $false
.sym 4739 $add$top.v:89$20_Y[5]
.sym 4740 $abc$92916$n1040
.sym 4741 $auto$simplemap.cc:250:simplemap_eqne$80251[1]
.sym 4742 $false
.sym 4743 $auto$dff2dffe.cc:175:make_patterns_logic$76937
.sym 4744 CLK$2$2
.sym 4745 $false
.sym 4746 REPORT_DATA.r_data[4]
.sym 4748 REPORT_DATA.r_data[5]
.sym 4750 REPORT_DATA.r_data[6]
.sym 4752 REPORT_DATA.r_data[7]
.sym 4820 $false
.sym 4821 $true$2
.sym 4822 report_data_adr[0]
.sym 4823 $false
.sym 4825 wr_cnt[2]
.sym 4826 $abc$92916$n687
.sym 4827 $abc$92916$n733
.sym 4828 $add$top.v:184$103_Y[2]
.sym 4830 $abc$92916$n733
.sym 4831 report_data_adr[0]
.sym 4832 report_data_adr[1]
.sym 4833 $false
.sym 4835 $false
.sym 4836 $false
.sym 4837 report_data_adr[7]
.sym 4838 $auto$alumacc.cc:484:replace_alu$57656[6]
.sym 4840 $8\report_data_adr[7:0][7]
.sym 4841 $abc$92916$n733
.sym 4842 $add$top.v:184$103_Y[7]
.sym 4843 $abc$92916$n687
.sym 4845 $3\report_data_adr[7:0][7]
.sym 4846 $abc$92916$n995
.sym 4847 $2\INT[0:0]
.sym 4848 $auto$simplemap.cc:250:simplemap_eqne$80251[1]
.sym 4850 $3\report_data_adr[7:0][2]
.sym 4851 $abc$92916$n961
.sym 4852 $2\INT[0:0]
.sym 4853 $auto$simplemap.cc:250:simplemap_eqne$80251[1]
.sym 4855 $3\report_data_adr[7:0][0]
.sym 4856 $abc$92916$n954
.sym 4857 $2\INT[0:0]
.sym 4858 $auto$simplemap.cc:250:simplemap_eqne$80251[1]
.sym 4859 $auto$dff2dffe.cc:175:make_patterns_logic$76062
.sym 4860 CLK$2$2
.sym 4861 $false
.sym 4898 $true
.sym 4935 init_ram_cnt[0]$2
.sym 4936 $false
.sym 4937 init_ram_cnt[0]
.sym 4938 $false
.sym 4939 $false
.sym 4940 $auto$alumacc.cc:484:replace_alu$57665[1]
.sym 4942 $false
.sym 4943 init_ram_cnt[1]
.sym 4945 $auto$alumacc.cc:484:replace_alu$57665[2]
.sym 4946 $false
.sym 4947 $false
.sym 4948 init_ram_cnt[2]
.sym 4949 $auto$alumacc.cc:484:replace_alu$57665[1]
.sym 4950 $auto$alumacc.cc:484:replace_alu$57665[3]
.sym 4951 $false
.sym 4952 $false
.sym 4953 init_ram_cnt[3]
.sym 4954 $auto$alumacc.cc:484:replace_alu$57665[2]
.sym 4955 $auto$alumacc.cc:484:replace_alu$57665[4]
.sym 4956 $false
.sym 4957 $false
.sym 4958 init_ram_cnt[4]
.sym 4959 $auto$alumacc.cc:484:replace_alu$57665[3]
.sym 4960 $auto$alumacc.cc:484:replace_alu$57665[5]
.sym 4961 $false
.sym 4962 $false
.sym 4963 init_ram_cnt[5]
.sym 4964 $auto$alumacc.cc:484:replace_alu$57665[4]
.sym 4965 $auto$alumacc.cc:484:replace_alu$57665[6]$2
.sym 4966 $false
.sym 4967 $false
.sym 4968 init_ram_cnt[6]
.sym 4969 $auto$alumacc.cc:484:replace_alu$57665[5]
.sym 4974 $auto$alumacc.cc:484:replace_alu$57665[6]$2
.sym 4975 $auto$dff2dffe.cc:158:make_patterns_logic$73200
.sym 4976 CLK$2$2
.sym 4977 $logic_not$top.v:66$10_Y$2
.sym 5014 $true
.sym 5051 report_data_adr[0]$2
.sym 5052 $false
.sym 5053 report_data_adr[0]
.sym 5054 $false
.sym 5055 $false
.sym 5056 $auto$alumacc.cc:484:replace_alu$57656[1]
.sym 5058 $false
.sym 5059 report_data_adr[1]
.sym 5061 $auto$alumacc.cc:484:replace_alu$57656[2]
.sym 5062 $false
.sym 5063 $false
.sym 5064 report_data_adr[2]
.sym 5065 $auto$alumacc.cc:484:replace_alu$57656[1]
.sym 5066 $auto$alumacc.cc:484:replace_alu$57656[3]
.sym 5067 $false
.sym 5068 $false
.sym 5069 report_data_adr[3]
.sym 5070 $auto$alumacc.cc:484:replace_alu$57656[2]
.sym 5071 $auto$alumacc.cc:484:replace_alu$57656[4]
.sym 5072 $false
.sym 5073 $false
.sym 5074 report_data_adr[4]
.sym 5075 $auto$alumacc.cc:484:replace_alu$57656[3]
.sym 5076 $auto$alumacc.cc:484:replace_alu$57656[5]
.sym 5077 $false
.sym 5078 $false
.sym 5079 report_data_adr[5]
.sym 5080 $auto$alumacc.cc:484:replace_alu$57656[4]
.sym 5081 $auto$alumacc.cc:484:replace_alu$57656[6]$2
.sym 5082 $false
.sym 5083 $false
.sym 5084 report_data_adr[6]
.sym 5085 $auto$alumacc.cc:484:replace_alu$57656[5]
.sym 5090 $auto$alumacc.cc:484:replace_alu$57656[6]$2
.sym 5168 i2c_input_data_type[2]
.sym 5169 $false
.sym 5170 $false
.sym 5171 $false
.sym 5173 I2C.byte_counter[0]
.sym 5174 $false
.sym 5175 $false
.sym 5176 $false
.sym 5178 I2C.byte_counter[2]
.sym 5179 $false
.sym 5180 $false
.sym 5181 $false
.sym 5188 $false
.sym 5189 $false
.sym 5190 $false
.sym 5191 $auto$alumacc.cc:484:replace_alu$57647[6]
.sym 5193 $false
.sym 5194 $true$2
.sym 5195 init_ram_cnt[0]
.sym 5196 $false
.sym 5198 init_ram_cnt[1]
.sym 5199 init_ram_cnt[0]
.sym 5200 $false
.sym 5201 $false
.sym 5203 $false
.sym 5204 $false
.sym 5205 init_ram_cnt[7]
.sym 5206 $auto$alumacc.cc:484:replace_alu$57665[6]
.sym 5207 $auto$dff2dffe.cc:158:make_patterns_logic$73200
.sym 5208 CLK$2$2
.sym 5209 $logic_not$top.v:66$10_Y$2
.sym 5246 $true
.sym 5283 I2C.byte_counter[0]$2
.sym 5284 $false
.sym 5285 I2C.byte_counter[0]
.sym 5286 $false
.sym 5287 $false
.sym 5288 $auto$alumacc.cc:484:replace_alu$57674[1]
.sym 5290 I2C.byte_counter[1]
.sym 5291 $true$2
.sym 5293 $auto$alumacc.cc:484:replace_alu$57674[2]
.sym 5294 $false
.sym 5295 I2C.byte_counter[2]
.sym 5296 $true$2
.sym 5297 $auto$alumacc.cc:484:replace_alu$57674[1]
.sym 5298 $auto$alumacc.cc:484:replace_alu$57674[3]
.sym 5299 $false
.sym 5300 I2C.byte_counter[3]
.sym 5301 $true$2
.sym 5302 $auto$alumacc.cc:484:replace_alu$57674[2]
.sym 5303 $auto$alumacc.cc:484:replace_alu$57674[4]
.sym 5304 $false
.sym 5305 I2C.byte_counter[4]
.sym 5306 $true$2
.sym 5307 $auto$alumacc.cc:484:replace_alu$57674[3]
.sym 5308 $auto$alumacc.cc:484:replace_alu$57674[5]
.sym 5309 $false
.sym 5310 I2C.byte_counter[5]
.sym 5311 $true$2
.sym 5312 $auto$alumacc.cc:484:replace_alu$57674[4]
.sym 5313 $auto$alumacc.cc:484:replace_alu$57674[6]$2
.sym 5314 $false
.sym 5315 I2C.byte_counter[6]
.sym 5316 $true$2
.sym 5317 $auto$alumacc.cc:484:replace_alu$57674[5]
.sym 5322 $auto$alumacc.cc:484:replace_alu$57674[6]$2
.sym 5323 $auto$dff2dffe.cc:175:make_patterns_logic$80258
.sym 5324 CLK$2$2
.sym 5325 $logic_not$top.v:66$10_Y$2
.sym 5400 I2C.is_read
.sym 5401 $auto$dff2dffe.cc:175:make_patterns_logic$73101
.sym 5402 $abc$92916$n713
.sym 5403 $abc$92916$n701
.sym 5405 I2C_INPUT_LEN[7]
.sym 5406 $false
.sym 5407 $false
.sym 5408 $false
.sym 5410 I2C_INPUT_LEN[5]
.sym 5411 $false
.sym 5412 $false
.sym 5413 $false
.sym 5415 I2C_INPUT_LEN[4]
.sym 5416 I2C_INPUT_LEN[5]
.sym 5417 I2C_INPUT_LEN[6]
.sym 5418 I2C_INPUT_LEN[7]
.sym 5420 I2C_INPUT_LEN[4]
.sym 5421 $false
.sym 5422 $false
.sym 5423 $false
.sym 5425 I2C_INPUT_LEN[3]
.sym 5426 $false
.sym 5427 $false
.sym 5428 $false
.sym 5430 I2C_INPUT_LEN[2]
.sym 5431 $false
.sym 5432 $false
.sym 5433 $false
.sym 5435 $false
.sym 5436 I2C.byte_counter[7]
.sym 5437 $true$2
.sym 5438 $auto$alumacc.cc:484:replace_alu$57674[6]
.sym 5439 $auto$dff2dffe.cc:175:make_patterns_logic$80258
.sym 5440 CLK$2$2
.sym 5441 $logic_not$top.v:66$10_Y$2
.sym 5516 I2C_INPUT_LEN[2]
.sym 5517 I2C_INPUT_LEN[3]
.sym 5518 I2C_INPUT_LEN[0]
.sym 5519 I2C_INPUT_LEN[1]
.sym 5526 I2C_INPUT_LEN[2]
.sym 5527 I2C_INPUT_LEN[3]
.sym 5528 I2C_INPUT_LEN[0]
.sym 5529 I2C_INPUT_LEN[1]
.sym 5531 $abc$92916$n789
.sym 5532 $abc$92916$n814_1
.sym 5533 $false
.sym 5534 $false
.sym 5536 $abc$92916$n701
.sym 5537 UART.tx_activity
.sym 5538 last_uart_active
.sym 5539 $auto$dff2dffe.cc:175:make_patterns_logic$73101
.sym 5541 I2C_INPUT_LEN[2]
.sym 5542 I2C_INPUT_LEN[3]
.sym 5543 I2C_INPUT_LEN[0]
.sym 5544 I2C_INPUT_LEN[1]
.sym 5546 I2C_INPUT_LEN[2]
.sym 5547 I2C_INPUT_LEN[3]
.sym 5548 I2C_INPUT_LEN[0]
.sym 5549 I2C_INPUT_LEN[1]
.sym 5551 UART.tx_activity
.sym 5552 $false
.sym 5553 $false
.sym 5554 $false
.sym 5555 $auto$dff2dffe.cc:175:make_patterns_logic$84280
.sym 5556 CLK$2$2
.sym 5557 $logic_not$top.v:66$10_Y$2
.sym 5558 I2C_TX_DESC[0]
.sym 5559 I2C_TX_DESC[1]
.sym 5560 I2C_TX_DESC[2]
.sym 5561 I2C_TX_DESC[3]
.sym 5562 I2C_TX_DESC[4]
.sym 5563 I2C_TX_DESC[5]
.sym 5564 I2C_TX_DESC[6]
.sym 5565 I2C_TX_DESC[7]
.sym 5632 $abc$92916$n809
.sym 5633 $abc$92916$n1068
.sym 5634 I2C_OUTPUT_TYPE[1]
.sym 5635 $abc$92916$n1066
.sym 5637 $abc$92916$n1066
.sym 5638 $abc$92916$n1068
.sym 5639 I2C_OUTPUT_TYPE[2]
.sym 5640 $false
.sym 5642 $abc$92916$n717
.sym 5643 $auto$dff2dffe.cc:175:make_patterns_logic$73101
.sym 5644 $abc$92916$n721
.sym 5645 I2C.is_read
.sym 5647 $abc$92916$n713
.sym 5648 $abc$92916$n716
.sym 5649 $abc$92916$n701
.sym 5650 $false
.sym 5652 I2C.byte_counter[1]
.sym 5653 $false
.sym 5654 $false
.sym 5655 $false
.sym 5657 I2C.byte_counter[4]
.sym 5658 $false
.sym 5659 $false
.sym 5660 $false
.sym 5662 I2C_OUTPUT_TYPE[1]
.sym 5663 I2C_OUTPUT_TYPE[0]
.sym 5664 I2C.byte_counter[5]
.sym 5665 $false
.sym 5667 I2C.byte_counter[2]
.sym 5668 $false
.sym 5669 $false
.sym 5670 $false
.sym 5671 $auto$dff2dffe.cc:158:make_patterns_logic$92134
.sym 5672 CLK$2$2
.sym 5673 $logic_not$top.v:66$10_Y$2
.sym 5748 I2C_TX_REPORT[3]
.sym 5749 I2C_TX_DESC[3]
.sym 5750 I2C_OUT_DESC_MASK[3]
.sym 5751 $false
.sym 5758 I2C_TX_REPORT[0]
.sym 5759 I2C_TX_DESC[0]
.sym 5760 I2C_OUT_DESC_MASK[0]
.sym 5761 $false
.sym 5768 $2\I2C_OUT_DESC_MASK[7:0][7]
.sym 5769 $false
.sym 5770 $false
.sym 5771 $false
.sym 5773 $abc$92916$n1065
.sym 5774 $2\INT[0:0]
.sym 5775 $false
.sym 5776 $false
.sym 5778 $abc$92916$n1070
.sym 5779 $2\INT[0:0]
.sym 5780 $false
.sym 5781 $false
.sym 5783 $abc$92916$n1072
.sym 5784 $2\INT[0:0]
.sym 5785 $false
.sym 5786 $false
.sym 5787 $auto$dff2dffe.cc:175:make_patterns_logic$81361$2
.sym 5788 CLK$2$2
.sym 5789 $logic_not$top.v:66$10_Y$2
.sym 5884 I2C.byte_counter[0]
.sym 5885 I2C.byte_counter[1]
.sym 5886 $false
.sym 5887 $false
.sym 5903 $auto$dff2dffe.cc:175:make_patterns_logic$80258
.sym 5904 CLK$2$2
.sym 5905 $logic_not$top.v:66$10_Y$2
.sym 5980 I2C.i2c_state_machine
.sym 5981 I2C.i2c_start_latency
.sym 5982 $techmap\I2C.$procmux$19804_Y
.sym 5983 $false
.sym 6015 $techmap\I2C.$procmux$19804_Y
.sym 6016 $false
.sym 6017 $false
.sym 6018 $false
.sym 6019 $auto$dff2dffe.cc:158:make_patterns_logic$85062
.sym 6020 CLK$2$2
.sym 6021 $false
.sym 6194 KBD_COLUMNS[0]$2
.sym 6196 KBD_COLUMNS[1]$2
.sym 6198 $auto$alumacc.cc:484:replace_alu$57563[7]
.sym 6199 $abc$92916$n629
.sym 6200 $auto$rtlil.cc:1692:NotGate$92893
.sym 6201 $abc$92916$n616
.sym 6202 $abc$92916$n622
.sym 6203 $abc$92916$n667
.sym 6204 $abc$92916$n618
.sym 6205 $abc$92916$n668
.sym 6338 KEYBOARD.row_time[2]
.sym 6339 KEYBOARD.row_time[3]
.sym 6340 KEYBOARD.row_time[4]
.sym 6341 KEYBOARD.row_time[5]
.sym 6342 KEYBOARD.row_time[6]
.sym 6343 KEYBOARD.row_time[7]
.sym 6438 KEYBOARD.row_time[8]
.sym 6439 KEYBOARD.row_time[9]
.sym 6440 KEYBOARD.row_time[10]
.sym 6441 KEYBOARD.row_time[11]
.sym 6442 KEYBOARD.row_time[12]
.sym 6443 KEYBOARD.row_time[13]
.sym 6444 KEYBOARD.row_time[14]
.sym 6445 $auto$alumacc.cc:484:replace_alu$57724[14]
.sym 6542 $techmap\UART.$sub$uart.v:32$535_Y[2]
.sym 6543 $auto$alumacc.cc:484:replace_alu$57727[2]
.sym 6544 $auto$alumacc.cc:483:replace_alu$57607[6]
.sym 6545 KEYBOARD.report[5][7]
.sym 6546 KEYBOARD.report[5][6]
.sym 6547 KEYBOARD.report[5][5]
.sym 6642 $abc$92916$n840
.sym 6643 $techmap\UART.$sub$uart.v:32$535_Y[0]
.sym 6644 $abc$92916$n841
.sym 6645 $abc$92916$n957
.sym 6646 UART.tx_clk_counter[3]
.sym 6647 UART.tx_clk_counter[1]
.sym 6648 UART.tx_clk_counter[2]
.sym 6649 UART.tx_clk_counter[0]
.sym 6650 $undef
.sym 6651 $undef
.sym 6652 $undef
.sym 6653 $undef
.sym 6654 $undef
.sym 6655 $undef
.sym 6656 $undef
.sym 6657 $undef
.sym 6658 report_data_adr[0]
.sym 6659 report_data_adr[1]
.sym 6660 $false
.sym 6661 report_data_adr[2]
.sym 6662 report_data_adr[3]
.sym 6663 report_data_adr[4]
.sym 6664 report_data_adr[5]
.sym 6665 report_data_adr[6]
.sym 6666 report_data_adr[7]
.sym 6667 $false
.sym 6668 $false
.sym 6669 CLK$2$2
.sym 6670 $true
.sym 6671 report_data_wr[0]
.sym 6672 $undef
.sym 6673 report_data_wr[1]
.sym 6674 $undef
.sym 6675 report_data_wr[2]
.sym 6676 $undef
.sym 6677 report_data_wr[3]
.sym 6678 $undef
.sym 6679 report_wr_en
.sym 6748 $auto$alumacc.cc:484:replace_alu$57597[3]
.sym 6749 KEYBOARD.report[0][1]
.sym 6750 KEYBOARD.report[0][2]
.sym 6751 KEYBOARD.report[0][6]
.sym 6752 $undef
.sym 6753 $undef
.sym 6754 $undef
.sym 6755 $undef
.sym 6756 $undef
.sym 6757 $undef
.sym 6758 $undef
.sym 6759 $undef
.sym 6760 report_data_adr[0]
.sym 6761 report_data_adr[1]
.sym 6762 $false
.sym 6763 report_data_adr[2]
.sym 6764 report_data_adr[3]
.sym 6765 report_data_adr[4]
.sym 6766 report_data_adr[5]
.sym 6767 report_data_adr[6]
.sym 6768 report_data_adr[7]
.sym 6769 $false
.sym 6770 $false
.sym 6771 CLK$2$2
.sym 6772 $true
.sym 6773 $true$2
.sym 6774 report_data_wr[5]
.sym 6775 $undef
.sym 6776 report_data_wr[6]
.sym 6777 $undef
.sym 6778 report_data_wr[7]
.sym 6779 $undef
.sym 6780 report_data_wr[4]
.sym 6781 $undef
.sym 6846 $auto$dff2dffe.cc:158:make_patterns_logic$85140
.sym 6847 $abc$92916$n976
.sym 6848 $abc$92916$n839
.sym 6849 $abc$92916$n1188_1
.sym 6850 $abc$92916$n974
.sym 6851 $abc$92916$n975
.sym 6852 $auto$dff2dffe.cc:175:make_patterns_logic$85121
.sym 6853 UART.tx_activity
.sym 6948 $abc$92916$n726_1
.sym 6949 $abc$92916$n703
.sym 6950 $abc$92916$n705
.sym 6951 $auto$alumacc.cc:483:replace_alu$57596[0]
.sym 6952 I2C_TX_REPORT[6]
.sym 6953 I2C_TX_REPORT[1]
.sym 6954 I2C_TX_REPORT[3]
.sym 7050 $auto$dff2dffe.cc:175:make_patterns_logic$79939
.sym 7051 $abc$92916$n692
.sym 7052 $abc$92916$n678_1
.sym 7053 $auto$dff2dffe.cc:175:make_patterns_logic$71021
.sym 7054 $auto$dff2dffe.cc:175:make_patterns_logic$70825
.sym 7055 $abc$92916$n784_1
.sym 7056 $abc$92916$n691
.sym 7057 UART_WR
.sym 7152 $abc$92916$n804
.sym 7153 $abc$92916$n794
.sym 7154 $abc$92916$n795
.sym 7155 $abc$92916$n796
.sym 7156 $abc$92916$n800
.sym 7157 $abc$92916$n802
.sym 7158 $abc$92916$n797
.sym 7159 $abc$92916$n806_1
.sym 7256 $auto$wreduce.cc:310:run$57529[2]
.sym 7257 $auto$alumacc.cc:484:replace_alu$57721[2]
.sym 7258 $abc$92916$n1068
.sym 7259 $abc$92916$n808
.sym 7260 $abc$92916$n807
.sym 7261 I2C_INPUT_LEN[0]
.sym 7356 $abc$92916$n1066
.sym 7357 $abc$92916$n1065
.sym 7358 $sub$top.v:88$19_Y[1]
.sym 7359 I2C_TX_REPORT[5]
.sym 7360 I2C_TX_REPORT[0]
.sym 7361 I2C_TX_REPORT[4]
.sym 7362 I2C_TX_REPORT[7]
.sym 7363 I2C_TX_REPORT[2]
.sym 7458 $abc$92916$n1109
.sym 7459 $abc$92916$n1111
.sym 7460 $abc$92916$n1099
.sym 7461 $abc$92916$n1101
.sym 7462 $2\I2C_OUT_DESC_MASK[7:0][7]
.sym 7463 $abc$92916$n1107
.sym 7464 $abc$92916$n1105
.sym 7465 INT
.sym 7474 $false
.sym 7475 $false
.sym 7477 $false
.sym 7478 $false
.sym 7479 $false
.sym 7480 $false
.sym 7481 $false
.sym 7482 $false
.sym 7485 $false
.sym 7486 $false$2
.sym 7487 $false
.sym 7488 $false
.sym 7489 $false
.sym 7490 $false
.sym 7491 $false
.sym 7492 $false
.sym 7493 $false
.sym 7494 $false
.sym 7495 $false
.sym 7561 $add$top.v:66$11_Y[1]
.sym 7562 $add$top.v:66$11_Y[2]
.sym 7563 $auto$alumacc.cc:484:replace_alu$57659[2]
.sym 7564 I2C_OUT_DESC_MASK[6]
.sym 7565 I2C_OUT_DESC_MASK[2]
.sym 7566 I2C_OUT_DESC_MASK[1]
.sym 7567 I2C_OUT_DESC_MASK[0]
.sym 7576 I2C_HID_DESC.real_adress[0]
.sym 7577 I2C_HID_DESC.real_adress[1]
.sym 7579 I2C_HID_DESC.real_adress[2]
.sym 7580 I2C_HID_DESC.real_adress[3]
.sym 7581 I2C_HID_DESC.real_adress[4]
.sym 7582 I2C_HID_DESC.real_adress[5]
.sym 7583 I2C_HID_DESC.real_adress[6]
.sym 7584 I2C_HID_DESC.real_adress[7]
.sym 7587 CLK$2$2
.sym 7588 $true
.sym 7589 $true$2
.sym 7665 $add$top.v:66$11_Y[3]
.sym 7666 RESET
.sym 7667 rststate[2]
.sym 7668 rststate[1]
.sym 7669 rststate[3]
.sym 7894 $abc$92916$n615
.sym 7895 $abc$92916$n621
.sym 7897 $abc$92916$n1201
.sym 7898 $abc$92916$n624
.sym 7899 $abc$92916$n633
.sym 7901 KEYBOARD.row_time[1]
.sym 7931 $true
.sym 7968 KEYBOARD.kbd_code_hid[0]$2
.sym 7969 $false
.sym 7970 KEYBOARD.kbd_code_hid[0]
.sym 7971 $false
.sym 7972 $false
.sym 7973 $auto$alumacc.cc:484:replace_alu$57563[1]
.sym 7975 KEYBOARD.kbd_code_hid[1]
.sym 7976 $false
.sym 7978 $auto$alumacc.cc:484:replace_alu$57563[2]
.sym 7980 KEYBOARD.kbd_code_hid[2]
.sym 7981 $false
.sym 7983 $auto$alumacc.cc:484:replace_alu$57563[3]
.sym 7985 KEYBOARD.kbd_code_hid[3]
.sym 7986 $false
.sym 7988 $auto$alumacc.cc:484:replace_alu$57563[4]
.sym 7990 KEYBOARD.kbd_code_hid[4]
.sym 7991 $false
.sym 7993 $auto$alumacc.cc:484:replace_alu$57563[5]
.sym 7995 KEYBOARD.kbd_code_hid[5]
.sym 7996 $true$2
.sym 7998 $auto$alumacc.cc:484:replace_alu$57563[6]
.sym 8000 KEYBOARD.kbd_code_hid[6]
.sym 8001 $false
.sym 8003 $auto$alumacc.cc:484:replace_alu$57563[7]$2
.sym 8005 KEYBOARD.kbd_code_hid[7]
.sym 8006 $false
.sym 8011 KBD_COLUMNS[2]$2
.sym 8013 KBD_COLUMNS[3]$2
.sym 8015 $abc$92916$n619
.sym 8016 $abc$92916$n642
.sym 8017 $abc$92916$n630
.sym 8018 $abc$92916$n657
.sym 8019 $techmap\KEYBOARD.$procmux$7960_Y
.sym 8020 $abc$92916$n658
.sym 8021 $abc$92916$n632
.sym 8022 $abc$92916$n626
.sym 8128 $auto$alumacc.cc:484:replace_alu$57563[7]$2
.sym 8130 KEYBOARD.row_time[8]
.sym 8131 KEYBOARD.row_time[9]
.sym 8132 KEYBOARD.row_time[10]
.sym 8133 KEYBOARD.row_time[11]
.sym 8135 $abc$92916$n642
.sym 8136 $abc$92916$n667
.sym 8137 $abc$92916$n617
.sym 8138 $abc$92916$n668
.sym 8140 $abc$92916$n617
.sym 8141 $abc$92916$n618
.sym 8142 $false
.sym 8143 $false
.sym 8145 $abc$92916$n617
.sym 8146 $abc$92916$n623
.sym 8147 KEYBOARD.row_time[8]
.sym 8148 KEYBOARD.row_time[9]
.sym 8150 $abc$92916$n623
.sym 8151 KEYBOARD.row_time[4]
.sym 8152 KEYBOARD.row_time[5]
.sym 8153 $false
.sym 8155 KEYBOARD.row_time[8]
.sym 8156 KEYBOARD.row_time[9]
.sym 8157 KEYBOARD.row_time[10]
.sym 8158 KEYBOARD.row_time[11]
.sym 8160 KEYBOARD.row_time[8]
.sym 8161 KEYBOARD.row_time[9]
.sym 8162 KEYBOARD.row_time[6]
.sym 8163 KEYBOARD.row_time[7]
.sym 8167 $abc$92916$n641
.sym 8168 $abc$92916$n648
.sym 8169 $abc$92916$n647
.sym 8170 $abc$92916$n649
.sym 8171 $abc$92916$n672
.sym 8172 $abc$92916$n673
.sym 8173 $abc$92916$n643
.sym 8174 KEYBOARD.report[0][0]
.sym 8203 $true
.sym 8240 KEYBOARD.row_time[0]$2
.sym 8241 $false
.sym 8242 KEYBOARD.row_time[0]
.sym 8243 $false
.sym 8244 $false
.sym 8245 $auto$alumacc.cc:484:replace_alu$57724[1]
.sym 8247 $false
.sym 8248 KEYBOARD.row_time[1]
.sym 8250 $auto$alumacc.cc:484:replace_alu$57724[2]
.sym 8251 $false
.sym 8252 $false
.sym 8253 KEYBOARD.row_time[2]
.sym 8254 $auto$alumacc.cc:484:replace_alu$57724[1]
.sym 8255 $auto$alumacc.cc:484:replace_alu$57724[3]
.sym 8256 $false
.sym 8257 $false
.sym 8258 KEYBOARD.row_time[3]
.sym 8259 $auto$alumacc.cc:484:replace_alu$57724[2]
.sym 8260 $auto$alumacc.cc:484:replace_alu$57724[4]
.sym 8261 $false
.sym 8262 $false
.sym 8263 KEYBOARD.row_time[4]
.sym 8264 $auto$alumacc.cc:484:replace_alu$57724[3]
.sym 8265 $auto$alumacc.cc:484:replace_alu$57724[5]
.sym 8266 $false
.sym 8267 $false
.sym 8268 KEYBOARD.row_time[5]
.sym 8269 $auto$alumacc.cc:484:replace_alu$57724[4]
.sym 8270 $auto$alumacc.cc:484:replace_alu$57724[6]
.sym 8271 $false
.sym 8272 $false
.sym 8273 KEYBOARD.row_time[6]
.sym 8274 $auto$alumacc.cc:484:replace_alu$57724[5]
.sym 8275 $auto$alumacc.cc:484:replace_alu$57724[7]
.sym 8276 $false
.sym 8277 $false
.sym 8278 KEYBOARD.row_time[7]
.sym 8279 $auto$alumacc.cc:484:replace_alu$57724[6]
.sym 8280 RESET$2
.sym 8281 CLK$2$2
.sym 8282 $auto$rtlil.cc:1692:NotGate$92893$2
.sym 8283 $abc$92916$n1034_1
.sym 8284 $abc$92916$n998
.sym 8285 $abc$92916$n1033
.sym 8286 $abc$92916$n617
.sym 8287 $abc$92916$n997
.sym 8288 $techmap\KEYBOARD.$procmux$18803_CMP
.sym 8289 $abc$92916$n1035
.sym 8290 report_data_wr[7]
.sym 8319 $auto$alumacc.cc:484:replace_alu$57724[7]
.sym 8356 $auto$alumacc.cc:484:replace_alu$57724[8]
.sym 8357 $false
.sym 8358 $false
.sym 8359 KEYBOARD.row_time[8]
.sym 8360 $auto$alumacc.cc:484:replace_alu$57724[7]
.sym 8361 $auto$alumacc.cc:484:replace_alu$57724[9]
.sym 8362 $false
.sym 8363 $false
.sym 8364 KEYBOARD.row_time[9]
.sym 8365 $auto$alumacc.cc:484:replace_alu$57724[8]
.sym 8366 $auto$alumacc.cc:484:replace_alu$57724[10]
.sym 8367 $false
.sym 8368 $false
.sym 8369 KEYBOARD.row_time[10]
.sym 8370 $auto$alumacc.cc:484:replace_alu$57724[9]
.sym 8371 $auto$alumacc.cc:484:replace_alu$57724[11]
.sym 8372 $false
.sym 8373 $false
.sym 8374 KEYBOARD.row_time[11]
.sym 8375 $auto$alumacc.cc:484:replace_alu$57724[10]
.sym 8376 $auto$alumacc.cc:484:replace_alu$57724[12]
.sym 8377 $false
.sym 8378 $false
.sym 8379 KEYBOARD.row_time[12]
.sym 8380 $auto$alumacc.cc:484:replace_alu$57724[11]
.sym 8381 $auto$alumacc.cc:484:replace_alu$57724[13]
.sym 8382 $false
.sym 8383 $false
.sym 8384 KEYBOARD.row_time[13]
.sym 8385 $auto$alumacc.cc:484:replace_alu$57724[12]
.sym 8386 $auto$alumacc.cc:484:replace_alu$57724[14]$2
.sym 8387 $false
.sym 8388 $false
.sym 8389 KEYBOARD.row_time[14]
.sym 8390 $auto$alumacc.cc:484:replace_alu$57724[13]
.sym 8395 $auto$alumacc.cc:484:replace_alu$57724[14]$2
.sym 8396 RESET$2
.sym 8397 CLK$2$2
.sym 8398 $auto$rtlil.cc:1692:NotGate$92893$2
.sym 8399 $abc$92916$n1044
.sym 8400 $abc$92916$n1042_1
.sym 8401 $abc$92916$n872
.sym 8402 $abc$92916$n1048
.sym 8403 $abc$92916$n880
.sym 8404 $abc$92916$n1041
.sym 8405 $abc$92916$n883
.sym 8406 report_data_wr[2]
.sym 8435 $true
.sym 8472 UART.tx_clk_counter[0]$2
.sym 8473 $false
.sym 8474 UART.tx_clk_counter[0]
.sym 8475 $false
.sym 8476 $false
.sym 8477 $auto$alumacc.cc:484:replace_alu$57727[1]
.sym 8479 UART.tx_clk_counter[1]
.sym 8480 $true$2
.sym 8482 $auto$alumacc.cc:484:replace_alu$57727[2]$2
.sym 8483 $false
.sym 8484 UART.tx_clk_counter[2]
.sym 8485 $true$2
.sym 8486 $auto$alumacc.cc:484:replace_alu$57727[1]
.sym 8491 $auto$alumacc.cc:484:replace_alu$57727[2]$2
.sym 8493 I2C.byte_counter[6]
.sym 8494 $false
.sym 8495 $false
.sym 8496 $false
.sym 8498 $techmap\KEYBOARD.$procmux$5651_Y[7]
.sym 8499 $false
.sym 8500 $false
.sym 8501 $false
.sym 8503 $techmap\KEYBOARD.$procmux$5651_Y[6]
.sym 8504 $false
.sym 8505 $false
.sym 8506 $false
.sym 8508 $techmap\KEYBOARD.$procmux$5651_Y[5]
.sym 8509 $false
.sym 8510 $false
.sym 8511 $false
.sym 8512 $auto$dff2dffe.cc:175:make_patterns_logic$87074
.sym 8513 CLK$2$2
.sym 8514 $logic_not$top.v:66$10_Y$2
.sym 8515 $abc$92916$n1019_1
.sym 8516 $8\report_data_adr[7:0][0]
.sym 8517 $abc$92916$n1020
.sym 8518 $abc$92916$n1049
.sym 8519 $abc$92916$n954
.sym 8520 $abc$92916$n1051
.sym 8521 KEYBOARD.report[3][6]
.sym 8522 KEYBOARD.report[3][5]
.sym 8589 $abc$92916$n841
.sym 8590 UART.tx_clk_counter[0]
.sym 8591 UART.tx_clk_counter[1]
.sym 8592 $false
.sym 8594 $false
.sym 8595 UART.tx_clk_counter[0]
.sym 8596 $false
.sym 8597 $true$2
.sym 8599 $techmap\UART.$sub$uart.v:32$535_Y[0]
.sym 8600 $techmap\UART.$sub$uart.v:32$535_Y[2]
.sym 8601 $techmap\UART.$sub$uart.v:32$535_Y[3]
.sym 8602 $false
.sym 8604 wr_cnt[1]
.sym 8605 $abc$92916$n687
.sym 8606 $abc$92916$n958
.sym 8607 $2\INT[0:0]
.sym 8609 $abc$92916$n840
.sym 8610 UART.tx_activity
.sym 8611 $techmap\UART.$sub$uart.v:32$535_Y[3]
.sym 8612 $false
.sym 8614 UART.tx_activity
.sym 8615 UART.tx_clk_counter[0]
.sym 8616 UART.tx_clk_counter[1]
.sym 8617 $false
.sym 8619 $abc$92916$n840
.sym 8620 UART.tx_activity
.sym 8621 $techmap\UART.$sub$uart.v:32$535_Y[2]
.sym 8622 $false
.sym 8624 $abc$92916$n840
.sym 8625 UART.tx_activity
.sym 8626 $techmap\UART.$sub$uart.v:32$535_Y[0]
.sym 8627 $false
.sym 8628 $auto$dff2dffe.cc:158:make_patterns_logic$85140
.sym 8629 CLK$2$2
.sym 8630 $logic_not$top.v:66$10_Y$2
.sym 8632 $abc$92916$n1195
.sym 8633 $abc$92916$n1205
.sym 8634 $auto$alumacc.cc:483:replace_alu$57596[3]
.sym 8635 $eq$top.v:243$154_Y
.sym 8636 $auto$alumacc.cc:470:replace_alu$57551.B_buf[3]
.sym 8637 $auto$alumacc.cc:483:replace_alu$57596[1]
.sym 8638 UART.tx_bit_counter[3]
.sym 8667 $true
.sym 8704 $auto$alumacc.cc:483:replace_alu$57596[0]$2
.sym 8705 $false
.sym 8706 $auto$alumacc.cc:483:replace_alu$57596[0]
.sym 8707 $false
.sym 8708 $false
.sym 8709 $auto$alumacc.cc:484:replace_alu$57597[1]
.sym 8711 $false
.sym 8712 $auto$alumacc.cc:483:replace_alu$57596[1]
.sym 8714 $auto$alumacc.cc:484:replace_alu$57597[2]
.sym 8716 $true$2
.sym 8717 $auto$alumacc.cc:470:replace_alu$57595.BB[2]
.sym 8719 $auto$alumacc.cc:484:replace_alu$57597[3]$2
.sym 8721 $false
.sym 8722 $auto$alumacc.cc:483:replace_alu$57596[3]
.sym 8728 $auto$alumacc.cc:484:replace_alu$57597[3]$2
.sym 8730 KEYBOARD.report[0][1]
.sym 8731 $auto$rtlil.cc:1692:NotGate$92753
.sym 8732 $abc$92916$n1195
.sym 8733 $false
.sym 8735 KEYBOARD.report[0][2]
.sym 8736 $auto$rtlil.cc:1692:NotGate$92753
.sym 8737 $abc$92916$n1197_1
.sym 8738 $false
.sym 8740 KEYBOARD.report[0][6]
.sym 8741 $auto$rtlil.cc:1692:NotGate$92753
.sym 8742 $abc$92916$n1205
.sym 8743 $false
.sym 8744 $auto$dff2dffe.cc:175:make_patterns_logic$91231
.sym 8745 CLK$2$2
.sym 8746 $logic_not$top.v:66$10_Y$2
.sym 8749 $auto$alumacc.cc:470:replace_alu$57551.B_buf[2]
.sym 8750 $auto$alumacc.cc:484:replace_alu$57730[2]
.sym 8751 $3\report_wr_en[0:0]
.sym 8752 $auto$rtlil.cc:1692:NotGate$92667
.sym 8753 $abc$92916$n842
.sym 8754 report_wr_en
.sym 8821 UART.TX_sig_last
.sym 8822 UART_WR
.sym 8823 RESET$2
.sym 8824 UART.tx_activity
.sym 8826 $add$top.v:184$103_Y[4]
.sym 8827 $2\ring_rd[3:0][1]
.sym 8828 $abc$92916$n733
.sym 8829 $false
.sym 8831 $abc$92916$n842
.sym 8832 UART.tx_bit_counter[2]
.sym 8833 UART.tx_bit_counter[3]
.sym 8834 $abc$92916$n840
.sym 8836 $abc$92916$n840
.sym 8837 $abc$92916$n842
.sym 8838 UART.tx_bit_counter[2]
.sym 8839 UART.tx_bit_counter[3]
.sym 8841 $2\ring_wr[3:0][1]
.sym 8842 $abc$92916$n975
.sym 8843 $2\INT[0:0]
.sym 8844 $false
.sym 8846 $8\report_data_adr[7:0][4]
.sym 8847 $abc$92916$n976
.sym 8848 $abc$92916$n687
.sym 8849 $false
.sym 8851 UART.tx_activity
.sym 8852 $abc$92916$n839
.sym 8853 RESET$2
.sym 8854 $auto$dff2dffe.cc:158:make_patterns_logic$85140
.sym 8856 UART_WR
.sym 8857 UART.TX_sig_last
.sym 8858 $abc$92916$n1188_1
.sym 8859 UART.tx_activity
.sym 8860 RESET$2
.sym 8861 CLK$2$2
.sym 8862 $false
.sym 8863 $auto$dff2dffe.cc:175:make_patterns_logic$74683
.sym 8864 $abc$92916$n739
.sym 8865 $abc$92916$n742
.sym 8866 $auto$dff2dffe.cc:175:make_patterns_logic$76062
.sym 8867 $auto$dff2dffe.cc:175:make_patterns_logic$76937
.sym 8868 $abc$92916$n743
.sym 8869 $auto$dff2dffe.cc:175:make_patterns_logic$73370
.sym 8870 $abc$92916$n738
.sym 8937 $abc$92916$n727
.sym 8938 $abc$92916$n728
.sym 8939 $false
.sym 8940 $false
.sym 8942 $abc$92916$n687
.sym 8943 $abc$92916$n676
.sym 8944 $abc$92916$n705
.sym 8945 $abc$92916$n704
.sym 8947 $2\INT[0:0]
.sym 8948 $abc$92916$n679
.sym 8949 RESET$2
.sym 8950 $auto$simplemap.cc:250:simplemap_eqne$80251[1]
.sym 8952 i2c_input_data_type[0]
.sym 8953 $false
.sym 8954 $false
.sym 8955 $false
.sym 8957 $abc$92916$n726_1
.sym 8958 $abc$92916$n733
.sym 8959 REPORT_DATA.r_data[6]
.sym 8960 $false
.sym 8962 $abc$92916$n728
.sym 8963 $abc$92916$n733
.sym 8964 REPORT_DATA.r_data[1]
.sym 8965 $abc$92916$n727
.sym 8967 $abc$92916$n728
.sym 8968 $abc$92916$n733
.sym 8969 REPORT_DATA.r_data[3]
.sym 8970 $abc$92916$n727
.sym 8976 $auto$dff2dffe.cc:175:make_patterns_logic$70825
.sym 8977 CLK$2$2
.sym 8978 $auto$simplemap.cc:250:simplemap_eqne$76135[8]$2
.sym 8979 $abc$92916$n732
.sym 8980 $abc$92916$n676
.sym 8981 $abc$92916$n689
.sym 8982 $abc$92916$n685
.sym 8983 $abc$92916$n731
.sym 8984 $auto$dff2dffe.cc:158:make_patterns_logic$73200
.sym 8985 $abc$92916$n725
.sym 8986 $auto$dff2dffe.cc:175:make_patterns_logic$73607
.sym 9053 I2C.is_read
.sym 9054 $abc$92916$n765
.sym 9055 $auto$dff2dffe.cc:175:make_patterns_logic$70825
.sym 9056 $abc$92916$n784_1
.sym 9058 $auto$simplemap.cc:250:simplemap_eqne$80251[1]
.sym 9059 RESET$2
.sym 9060 $abc$92916$n689
.sym 9061 $abc$92916$n693
.sym 9063 $abc$92916$n679
.sym 9064 RESET$2
.sym 9065 $false
.sym 9066 $false
.sym 9068 $abc$92916$n691
.sym 9069 $abc$92916$n703
.sym 9070 $auto$dff2dffe.cc:175:make_patterns_logic$73101
.sym 9071 $false
.sym 9073 I2C.is_read
.sym 9074 $abc$92916$n689
.sym 9075 RESET$2
.sym 9076 $auto$dff2dffe.cc:175:make_patterns_logic$80258
.sym 9078 $abc$92916$n785
.sym 9079 $abc$92916$n786
.sym 9080 $abc$92916$n703
.sym 9081 $false
.sym 9083 $abc$92916$n701
.sym 9084 UART.tx_activity
.sym 9085 last_uart_active
.sym 9086 $abc$92916$n692
.sym 9088 last_uart_active
.sym 9089 UART.tx_activity
.sym 9090 $2\uart_double_ff[0:0]
.sym 9091 $auto$rtlil.cc:1692:NotGate$92623
.sym 9092 $auto$dff2dffe.cc:175:make_patterns_logic$71021
.sym 9093 CLK$2$2
.sym 9094 $logic_not$top.v:66$10_Y$2
.sym 9095 $abc$92916$n713
.sym 9096 $auto$dff2dffe.cc:175:make_patterns_logic$80258
.sym 9097 $auto$dff2dffe.cc:175:make_patterns_logic$83913
.sym 9098 $abc$92916$n789
.sym 9099 $auto$dff2dffe.cc:175:make_patterns_logic$84512
.sym 9100 $abc$92916$n811
.sym 9101 $abc$92916$n744
.sym 9102 last_wr
.sym 9169 $abc$92916$n805
.sym 9170 $abc$92916$n798
.sym 9171 $abc$92916$n755
.sym 9172 i2c_input_data_type[0]
.sym 9174 $abc$92916$n795
.sym 9175 i2c_input_data_type[2]
.sym 9176 $false
.sym 9177 $false
.sym 9179 $abc$92916$n796
.sym 9180 $abc$92916$n802
.sym 9181 $abc$92916$n804
.sym 9182 $abc$92916$n806_1
.sym 9184 $abc$92916$n800
.sym 9185 $abc$92916$n797
.sym 9186 $auto$alumacc.cc:484:replace_alu$57597[3]
.sym 9187 $abc$92916$n763
.sym 9189 $abc$92916$n798
.sym 9190 $abc$92916$n801
.sym 9191 $false
.sym 9192 $false
.sym 9194 $abc$92916$n803
.sym 9195 $abc$92916$n798
.sym 9196 $abc$92916$n755
.sym 9197 i2c_input_data_type[0]
.sym 9199 $abc$92916$n798
.sym 9200 $abc$92916$n799_1
.sym 9201 $false
.sym 9202 $false
.sym 9204 $abc$92916$n807
.sym 9205 $abc$92916$n798
.sym 9206 $abc$92916$n773_1
.sym 9207 $false
.sym 9211 $abc$92916$n696
.sym 9212 $abc$92916$n677
.sym 9213 $abc$92916$n699
.sym 9214 $abc$92916$n693
.sym 9215 $abc$92916$n711
.sym 9216 $auto$dff2dffe.cc:175:make_patterns_logic$71223
.sym 9217 $abc$92916$n710
.sym 9218 uart_double_ff
.sym 9247 $true
.sym 9284 KEYBOARD.row_counter[0]$2
.sym 9285 $false
.sym 9286 KEYBOARD.row_counter[0]
.sym 9287 $false
.sym 9288 $false
.sym 9289 $auto$alumacc.cc:484:replace_alu$57721[1]
.sym 9291 $false
.sym 9292 KEYBOARD.row_counter[1]
.sym 9294 $auto$alumacc.cc:484:replace_alu$57721[2]$2
.sym 9295 $false
.sym 9296 $false
.sym 9297 KEYBOARD.row_counter[2]
.sym 9298 $auto$alumacc.cc:484:replace_alu$57721[1]
.sym 9303 $auto$alumacc.cc:484:replace_alu$57721[2]$2
.sym 9305 $abc$92916$n794
.sym 9306 $abc$92916$n809
.sym 9307 $abc$92916$n1067_1
.sym 9308 i2c_input_data_type[0]
.sym 9310 $abc$92916$n795
.sym 9311 i2c_input_data_type[0]
.sym 9312 $false
.sym 9313 $false
.sym 9315 I2C_INPUT_LEN[2]
.sym 9316 I2C_INPUT_LEN[3]
.sym 9317 I2C_INPUT_LEN[0]
.sym 9318 I2C_INPUT_LEN[1]
.sym 9320 $false
.sym 9321 I2C.byte_counter[0]
.sym 9322 $false
.sym 9323 $true$2
.sym 9324 $auto$dff2dffe.cc:175:make_patterns_logic$80258
.sym 9325 CLK$2$2
.sym 9326 $logic_not$top.v:66$10_Y$2
.sym 9327 $abc$92916$n1067_1
.sym 9328 $abc$92916$n947
.sym 9329 $abc$92916$n793
.sym 9330 $abc$92916$n809
.sym 9332 $abc$92916$n946
.sym 9333 UART_TX_DATA[0]
.sym 9401 $abc$92916$n809
.sym 9402 $abc$92916$n808
.sym 9403 $abc$92916$n794
.sym 9404 $abc$92916$n1067_1
.sym 9406 $abc$92916$n808
.sym 9407 $abc$92916$n1068
.sym 9408 I2C_OUTPUT_TYPE[0]
.sym 9409 $abc$92916$n1066
.sym 9411 init_ram_cnt[1]
.sym 9412 $false
.sym 9413 $false
.sym 9414 $false
.sym 9416 $abc$92916$n726_1
.sym 9417 $abc$92916$n733
.sym 9418 REPORT_DATA.r_data[5]
.sym 9419 $false
.sym 9421 $abc$92916$n726_1
.sym 9422 $abc$92916$n733
.sym 9423 REPORT_DATA.r_data[0]
.sym 9424 $false
.sym 9426 $abc$92916$n726_1
.sym 9427 $abc$92916$n733
.sym 9428 REPORT_DATA.r_data[4]
.sym 9429 $false
.sym 9431 $abc$92916$n726_1
.sym 9432 $abc$92916$n733
.sym 9433 REPORT_DATA.r_data[7]
.sym 9434 $false
.sym 9436 $abc$92916$n726_1
.sym 9437 $abc$92916$n733
.sym 9438 REPORT_DATA.r_data[2]
.sym 9439 $false
.sym 9440 $auto$dff2dffe.cc:175:make_patterns_logic$70825
.sym 9441 CLK$2$2
.sym 9442 $auto$simplemap.cc:250:simplemap_eqne$76135[8]$2
.sym 9443 $false$2
.sym 9444 $true$2
.sym 9445 $abc$92916$n820
.sym 9446 $auto$dff2dffe.cc:158:make_patterns_logic$92134
.sym 9448 I2C_TRANS
.sym 9450 I2C_HID_DESC.last_rd_request
.sym 9517 I2C_TX_REPORT[6]
.sym 9518 I2C_TX_DESC[6]
.sym 9519 I2C_OUT_DESC_MASK[6]
.sym 9520 $false
.sym 9522 I2C_TX_REPORT[7]
.sym 9523 I2C_TX_DESC[7]
.sym 9524 I2C_OUT_DESC_MASK[7]
.sym 9525 $false
.sym 9527 I2C_TX_REPORT[1]
.sym 9528 I2C_TX_DESC[1]
.sym 9529 I2C_OUT_DESC_MASK[1]
.sym 9530 $false
.sym 9532 I2C_TX_REPORT[2]
.sym 9533 I2C_TX_DESC[2]
.sym 9534 I2C_OUT_DESC_MASK[2]
.sym 9535 $false
.sym 9537 $abc$92916$n1065
.sym 9538 $abc$92916$n1070
.sym 9539 $abc$92916$n1072
.sym 9540 $2\INT[0:0]
.sym 9542 I2C_TX_REPORT[5]
.sym 9543 I2C_TX_DESC[5]
.sym 9544 I2C_OUT_DESC_MASK[5]
.sym 9545 $false
.sym 9547 I2C_TX_REPORT[4]
.sym 9548 I2C_TX_DESC[4]
.sym 9549 I2C_OUT_DESC_MASK[4]
.sym 9550 $false
.sym 9552 $2\INT[0:0]
.sym 9553 $false
.sym 9554 $false
.sym 9555 $false
.sym 9556 $auto$dff2dffe.cc:175:make_patterns_logic$72910
.sym 9557 CLK$2$2
.sym 9558 $logic_not$top.v:66$10_Y$2
.sym 9563 $auto$alumacc.cc:484:replace_alu$57574[3]
.sym 9564 $auto$alumacc.cc:483:replace_alu$57573[0]
.sym 9595 $false
.sym 9632 $auto$alumacc.cc:484:replace_alu$57659[0]
.sym 9634 $logic_not$top.v:66$10_Y$2
.sym 9635 rststate[0]
.sym 9637 $auto$alumacc.cc:484:replace_alu$57659[1]
.sym 9638 $false
.sym 9639 $false
.sym 9640 rststate[1]
.sym 9641 $auto$alumacc.cc:484:replace_alu$57659[0]
.sym 9642 $auto$alumacc.cc:484:replace_alu$57659[2]$2
.sym 9643 $false
.sym 9644 $false
.sym 9645 rststate[2]
.sym 9646 $auto$alumacc.cc:484:replace_alu$57659[1]
.sym 9651 $auto$alumacc.cc:484:replace_alu$57659[2]$2
.sym 9653 $2\I2C_OUT_DESC_MASK[7:0][7]
.sym 9654 $false
.sym 9655 $false
.sym 9656 $false
.sym 9658 $2\I2C_OUT_DESC_MASK[7:0][7]
.sym 9659 $false
.sym 9660 $false
.sym 9661 $false
.sym 9663 $2\I2C_OUT_DESC_MASK[7:0][7]
.sym 9664 $false
.sym 9665 $false
.sym 9666 $false
.sym 9668 $2\I2C_OUT_DESC_MASK[7:0][7]
.sym 9669 $false
.sym 9670 $false
.sym 9671 $false
.sym 9672 $auto$dff2dffe.cc:175:make_patterns_logic$81361$2
.sym 9673 CLK$2$2
.sym 9674 $logic_not$top.v:66$10_Y$2
.sym 9676 $add$top.v:66$11_Y[0]
.sym 9677 $auto$alumacc.cc:470:replace_alu$57572.B_buf[2]
.sym 9679 $auto$alumacc.cc:483:replace_alu$57573[2]
.sym 9680 I2C.i2c_bit_counter[2]
.sym 9682 rststate[0]
.sym 9764 $false
.sym 9765 $false
.sym 9766 rststate[3]
.sym 9767 $auto$alumacc.cc:484:replace_alu$57659[2]
.sym 9769 rststate[3]
.sym 9770 rststate[2]
.sym 9771 rststate[1]
.sym 9772 rststate[0]
.sym 9774 $abc$92916$n946
.sym 9775 $add$top.v:66$11_Y[2]
.sym 9776 $false
.sym 9777 $false
.sym 9779 $abc$92916$n946
.sym 9780 $add$top.v:66$11_Y[1]
.sym 9781 $false
.sym 9782 $false
.sym 9784 $abc$92916$n946
.sym 9785 $add$top.v:66$11_Y[3]
.sym 9786 $false
.sym 9787 $false
.sym 9788 $true
.sym 9789 CLK$2$2
.sym 9790 $false
.sym 9890 $abc$92916$n651
.sym 9892 $abc$92916$n625
.sym 9893 $abc$92916$n614
.sym 9895 $abc$92916$n1218
.sym 9896 $abc$92916$n631
.sym 9965 $abc$92916$n616
.sym 9966 KEYBOARD.row_time[0]
.sym 9967 KEYBOARD.row_time[1]
.sym 9968 $false
.sym 9970 $abc$92916$n622
.sym 9971 $abc$92916$n624
.sym 9972 $abc$92916$n626
.sym 9973 $false
.sym 9980 KEYBOARD.kbd_code_hid[2]
.sym 9981 KEYBOARD.kbd_code_hid[1]
.sym 9982 KEYBOARD.kbd_code_hid[0]
.sym 9983 $false
.sym 9985 $abc$92916$n625
.sym 9986 KEYBOARD.row_time[0]
.sym 9987 KEYBOARD.row_time[1]
.sym 9988 $false
.sym 9990 KEYBOARD.row_time[0]
.sym 9991 KEYBOARD.row_time[1]
.sym 9992 $false
.sym 9993 $false
.sym 10000 KEYBOARD.row_time[0]
.sym 10001 KEYBOARD.row_time[1]
.sym 10002 $false
.sym 10003 $false
.sym 10004 RESET$2
.sym 10005 CLK$2$2
.sym 10006 $auto$rtlil.cc:1692:NotGate$92893$2
.sym 10011 $abc$92916$n662
.sym 10012 $abc$92916$n663
.sym 10013 $abc$92916$n628
.sym 10014 KEYBOARD.report[6][4]
.sym 10015 KEYBOARD.report[6][1]
.sym 10016 KEYBOARD.report[6][7]
.sym 10018 KEYBOARD.report[6][0]
.sym 10121 KEYBOARD.row_time[4]
.sym 10122 KEYBOARD.row_time[5]
.sym 10123 KEYBOARD.row_time[6]
.sym 10124 KEYBOARD.row_time[7]
.sym 10126 $abc$92916$n633
.sym 10127 KEYBOARD.row_time[2]
.sym 10128 KEYBOARD.row_time[3]
.sym 10129 $false
.sym 10131 KEYBOARD.row_time[0]
.sym 10132 KEYBOARD.row_time[1]
.sym 10133 KEYBOARD.row_time[2]
.sym 10134 KEYBOARD.row_time[3]
.sym 10136 $abc$92916$n616
.sym 10137 $abc$92916$n658
.sym 10138 $abc$92916$n626
.sym 10139 $false
.sym 10141 $abc$92916$n622
.sym 10142 $abc$92916$n626
.sym 10143 $abc$92916$n630
.sym 10144 $false
.sym 10146 $abc$92916$n633
.sym 10147 KEYBOARD.row_time[2]
.sym 10148 KEYBOARD.row_time[3]
.sym 10149 $false
.sym 10151 KEYBOARD.row_time[4]
.sym 10152 KEYBOARD.row_time[5]
.sym 10153 KEYBOARD.row_time[6]
.sym 10154 KEYBOARD.row_time[7]
.sym 10156 KEYBOARD.row_time[4]
.sym 10157 KEYBOARD.row_time[5]
.sym 10158 KEYBOARD.row_time[6]
.sym 10159 KEYBOARD.row_time[7]
.sym 10163 $abc$92916$n851
.sym 10164 $abc$92916$n870
.sym 10165 $abc$92916$n854
.sym 10166 $abc$92916$n852_1
.sym 10167 $abc$92916$n853
.sym 10168 $abc$92916$n875
.sym 10169 $abc$92916$n874
.sym 10170 KEYBOARD.report[6][5]
.sym 10237 $abc$92916$n616
.sym 10238 $abc$92916$n642
.sym 10239 $abc$92916$n643
.sym 10240 $false
.sym 10242 $abc$92916$n649
.sym 10243 KEYBOARD.row_time[2]
.sym 10244 KEYBOARD.row_time[3]
.sym 10245 $false
.sym 10247 $abc$92916$n616
.sym 10248 $abc$92916$n648
.sym 10249 KEYBOARD.row_time[0]
.sym 10250 KEYBOARD.row_time[1]
.sym 10252 KEYBOARD.row_time[4]
.sym 10253 KEYBOARD.row_time[5]
.sym 10254 KEYBOARD.row_time[6]
.sym 10255 KEYBOARD.row_time[7]
.sym 10257 $abc$92916$n673
.sym 10258 KEYBOARD.kbd_code_hid[7]
.sym 10259 KEYBOARD.kbd_code_hid[6]
.sym 10260 KEYBOARD.kbd_code_hid[3]
.sym 10262 KEYBOARD.kbd_code_hid[2]
.sym 10263 KEYBOARD.kbd_code_hid[1]
.sym 10264 KEYBOARD.kbd_code_hid[0]
.sym 10265 $false
.sym 10267 KEYBOARD.row_time[4]
.sym 10268 KEYBOARD.row_time[5]
.sym 10269 KEYBOARD.row_time[6]
.sym 10270 KEYBOARD.row_time[7]
.sym 10272 KEYBOARD.report[0][0]
.sym 10273 $auto$rtlil.cc:1692:NotGate$92753
.sym 10274 $abc$92916$n673
.sym 10275 $false
.sym 10276 $auto$dff2dffe.cc:175:make_patterns_logic$91231
.sym 10277 CLK$2$2
.sym 10278 $logic_not$top.v:66$10_Y$2
.sym 10279 $abc$92916$n999_1
.sym 10280 $abc$92916$n1038
.sym 10281 $abc$92916$n1036
.sym 10282 $abc$92916$n1058
.sym 10283 $abc$92916$n1003
.sym 10284 $abc$92916$n1000
.sym 10285 KEYBOARD.report[6][2]
.sym 10286 KEYBOARD.report[6][3]
.sym 10353 $abc$92916$n1010_1
.sym 10354 $abc$92916$n1037
.sym 10355 $abc$92916$n1038
.sym 10356 $abc$92916$n1035
.sym 10358 KEYBOARD.report[0][0]
.sym 10359 $abc$92916$n1009
.sym 10360 $abc$92916$n999_1
.sym 10361 $abc$92916$n1006
.sym 10363 KEYBOARD.report[0][4]
.sym 10364 $abc$92916$n1034_1
.sym 10365 $2\INT[0:0]
.sym 10366 $false
.sym 10368 KEYBOARD.row_time[12]
.sym 10369 KEYBOARD.row_time[14]
.sym 10370 KEYBOARD.row_time[15]
.sym 10371 KEYBOARD.row_time[13]
.sym 10373 KEYBOARD.report[0][0]
.sym 10374 $abc$92916$n1010_1
.sym 10375 $abc$92916$n998
.sym 10376 $2\INT[0:0]
.sym 10378 $abc$92916$n672
.sym 10379 KEYBOARD.kbd_code_hid[4]
.sym 10380 KEYBOARD.kbd_code_hid[5]
.sym 10381 $false
.sym 10383 KEYBOARD.report[0][4]
.sym 10384 $abc$92916$n1009
.sym 10385 $abc$92916$n1036
.sym 10386 $false
.sym 10388 $add$top.v:89$20_Y[7]
.sym 10389 $abc$92916$n1054
.sym 10390 $auto$simplemap.cc:250:simplemap_eqne$80251[1]
.sym 10391 $false
.sym 10392 $auto$dff2dffe.cc:175:make_patterns_logic$76937
.sym 10393 CLK$2$2
.sym 10394 $false
.sym 10395 $abc$92916$n871
.sym 10396 $abc$92916$n873
.sym 10397 $abc$92916$n879
.sym 10398 $abc$92916$n882
.sym 10399 $abc$92916$n1015
.sym 10400 $abc$92916$n881
.sym 10401 KEYBOARD.report[5][0]
.sym 10402 KEYBOARD.report[5][4]
.sym 10469 $abc$92916$n1004
.sym 10470 KEYBOARD.report[6][5]
.sym 10471 $abc$92916$n1001
.sym 10472 KEYBOARD.report[5][5]
.sym 10474 KEYBOARD.report[3][5]
.sym 10475 $abc$92916$n1002_1
.sym 10476 $abc$92916$n1043
.sym 10477 $abc$92916$n1044
.sym 10479 KEYBOARD.report[5][4]
.sym 10480 KEYBOARD.report[5][5]
.sym 10481 KEYBOARD.report[5][6]
.sym 10482 KEYBOARD.report[5][7]
.sym 10484 KEYBOARD.report[0][6]
.sym 10485 $abc$92916$n1009
.sym 10486 $abc$92916$n1049
.sym 10487 $abc$92916$n1052
.sym 10489 KEYBOARD.kbd_code_hid[4]
.sym 10490 KEYBOARD.kbd_code_hid[5]
.sym 10491 KEYBOARD.report[5][4]
.sym 10492 KEYBOARD.report[5][5]
.sym 10494 KEYBOARD.report[0][5]
.sym 10495 $abc$92916$n1009
.sym 10496 $abc$92916$n1042_1
.sym 10497 $abc$92916$n1045
.sym 10499 KEYBOARD.kbd_code_hid[7]
.sym 10500 KEYBOARD.kbd_code_hid[6]
.sym 10501 KEYBOARD.report[5][6]
.sym 10502 KEYBOARD.report[5][7]
.sym 10504 $add$top.v:89$20_Y[2]
.sym 10505 $abc$92916$n1019_1
.sym 10506 $auto$simplemap.cc:250:simplemap_eqne$80251[1]
.sym 10507 $false
.sym 10508 $auto$dff2dffe.cc:175:make_patterns_logic$76937
.sym 10509 CLK$2$2
.sym 10510 $false
.sym 10511 $abc$92916$n1023
.sym 10512 $abc$92916$n1021
.sym 10513 $abc$92916$n1026
.sym 10514 $abc$92916$n1029_1
.sym 10515 $abc$92916$n1027
.sym 10516 $abc$92916$n1030
.sym 10517 $abc$92916$n1028
.sym 10518 KEYBOARD.report[3][3]
.sym 10585 KEYBOARD.report[0][2]
.sym 10586 $abc$92916$n1010_1
.sym 10587 $abc$92916$n1020
.sym 10588 $2\INT[0:0]
.sym 10590 $false
.sym 10591 wr_cnt[0]
.sym 10592 $false
.sym 10593 $false
.sym 10595 KEYBOARD.report[0][2]
.sym 10596 $abc$92916$n1009
.sym 10597 $abc$92916$n1021
.sym 10598 $abc$92916$n1024
.sym 10600 KEYBOARD.report[3][6]
.sym 10601 $abc$92916$n1002_1
.sym 10602 $abc$92916$n1050
.sym 10603 $abc$92916$n1051
.sym 10605 $8\report_data_adr[7:0][0]
.sym 10606 $abc$92916$n733
.sym 10607 $add$top.v:184$103_Y[0]
.sym 10608 $abc$92916$n687
.sym 10610 $abc$92916$n1004
.sym 10611 KEYBOARD.report[6][6]
.sym 10612 $abc$92916$n1001
.sym 10613 KEYBOARD.report[5][6]
.sym 10615 $techmap\KEYBOARD.$procmux$5651_Y[6]
.sym 10616 $false
.sym 10617 $false
.sym 10618 $false
.sym 10620 $techmap\KEYBOARD.$procmux$5651_Y[5]
.sym 10621 $false
.sym 10622 $false
.sym 10623 $false
.sym 10624 $auto$dff2dffe.cc:175:make_patterns_logic$89305
.sym 10625 CLK$2$2
.sym 10626 $logic_not$top.v:66$10_Y$2
.sym 10627 $abc$92916$n1004
.sym 10629 $abc$92916$n1010_1
.sym 10630 $abc$92916$n1022
.sym 10631 $abc$92916$n1008
.sym 10632 KEYBOARD.report[5][2]
.sym 10634 KEYBOARD.report[5][3]
.sym 10706 KEYBOARD.kbd_code_hid[2]
.sym 10707 KEYBOARD.kbd_code_hid[1]
.sym 10708 KEYBOARD.kbd_code_hid[0]
.sym 10709 $false
.sym 10711 KEYBOARD.kbd_code_hid[2]
.sym 10712 KEYBOARD.kbd_code_hid[1]
.sym 10713 KEYBOARD.kbd_code_hid[0]
.sym 10714 $false
.sym 10716 i2c_input_data_type[3]
.sym 10717 $false
.sym 10718 $false
.sym 10719 $false
.sym 10721 UART.tx_activity
.sym 10722 $false
.sym 10723 $false
.sym 10724 $false
.sym 10726 $false
.sym 10727 UART.tx_bit_counter[3]
.sym 10728 $true$2
.sym 10729 $auto$alumacc.cc:484:replace_alu$57730[2]
.sym 10731 i2c_input_data_type[1]
.sym 10732 $false
.sym 10733 $false
.sym 10734 $false
.sym 10736 $auto$alumacc.cc:470:replace_alu$57551.B_buf[3]
.sym 10737 $false
.sym 10738 $false
.sym 10739 $false
.sym 10740 $auto$dff2dffe.cc:175:make_patterns_logic$85121
.sym 10741 CLK$2$2
.sym 10742 $eq$top.v:243$154_Y
.sym 10744 $8\report_data_adr[7:0][4]
.sym 10745 $8\report_data_adr[7:0][5]
.sym 10746 $8\report_data_adr[7:0][6]
.sym 10747 $auto$alumacc.cc:484:replace_alu$57647[6]
.sym 10748 $abc$92916$n981
.sym 10749 $abc$92916$n982
.sym 10750 UART.tx_bit_counter[2]
.sym 10779 $true
.sym 10816 UART.tx_bit_counter[0]$2
.sym 10817 $false
.sym 10818 UART.tx_bit_counter[0]
.sym 10819 $false
.sym 10820 $false
.sym 10821 $auto$alumacc.cc:484:replace_alu$57730[1]
.sym 10823 UART.tx_bit_counter[1]
.sym 10824 $true$2
.sym 10826 $auto$alumacc.cc:484:replace_alu$57730[2]$2
.sym 10827 $false
.sym 10828 UART.tx_bit_counter[2]
.sym 10829 $true$2
.sym 10830 $auto$alumacc.cc:484:replace_alu$57730[1]
.sym 10835 $auto$alumacc.cc:484:replace_alu$57730[2]$2
.sym 10837 $abc$92916$n679
.sym 10838 $2\INT[0:0]
.sym 10839 $false
.sym 10840 $false
.sym 10842 $auto$simplemap.cc:250:simplemap_eqne$80251[1]
.sym 10843 $false
.sym 10844 $false
.sym 10845 $false
.sym 10847 UART.tx_bit_counter[0]
.sym 10848 UART.tx_bit_counter[1]
.sym 10849 $false
.sym 10850 $false
.sym 10852 $3\report_wr_en[0:0]
.sym 10853 $false
.sym 10854 $false
.sym 10855 $false
.sym 10856 $auto$dff2dffe.cc:175:make_patterns_logic$74683
.sym 10857 CLK$2$2
.sym 10858 $auto$rtlil.cc:1692:NotGate$92667
.sym 10859 $abc$92916$n989_1
.sym 10860 $abc$92916$n704
.sym 10861 $abc$92916$n990
.sym 10862 $2\INT[0:0]
.sym 10863 $abc$92916$n755
.sym 10864 $abc$92916$n983
.sym 10865 $abc$92916$n988
.sym 10866 KEYBOARD.isr
.sym 10933 $abc$92916$n738
.sym 10934 $abc$92916$n739
.sym 10935 $false
.sym 10936 $false
.sym 10938 $abc$92916$n704
.sym 10939 $abc$92916$n676
.sym 10940 $abc$92916$n687
.sym 10941 $abc$92916$n740
.sym 10943 $abc$92916$n740
.sym 10944 $abc$92916$n676
.sym 10945 $abc$92916$n743
.sym 10946 $false
.sym 10948 $abc$92916$n725
.sym 10949 $abc$92916$n742
.sym 10950 $abc$92916$n744
.sym 10951 $false
.sym 10953 $abc$92916$n742
.sym 10954 $abc$92916$n738
.sym 10955 $false
.sym 10956 $false
.sym 10958 $abc$92916$n679
.sym 10959 RESET$2
.sym 10960 $auto$simplemap.cc:250:simplemap_eqne$80251[1]
.sym 10961 $abc$92916$n704
.sym 10963 RESET$2
.sym 10964 $3\report_wr_en[0:0]
.sym 10965 $auto$simplemap.cc:250:simplemap_eqne$80251[1]
.sym 10966 $false
.sym 10968 RESET$2
.sym 10969 $abc$92916$n676
.sym 10970 $abc$92916$n687
.sym 10971 $false
.sym 10975 $abc$92916$n786
.sym 10976 $abc$92916$n762_1
.sym 10977 $auto$dff2dffe.cc:175:make_patterns_logic$84333
.sym 10978 $abc$92916$n683
.sym 10979 $abc$92916$n761
.sym 10980 $abc$92916$n760
.sym 10981 $abc$92916$n682
.sym 10982 last_isr
.sym 11049 $abc$92916$n689
.sym 11050 $abc$92916$n726_1
.sym 11051 $abc$92916$n733
.sym 11052 $abc$92916$n731
.sym 11054 $abc$92916$n677
.sym 11055 $auto$simplemap.cc:250:simplemap_eqne$80251[1]
.sym 11056 $false
.sym 11057 $false
.sym 11059 $abc$92916$n676
.sym 11060 $abc$92916$n686
.sym 11061 $false
.sym 11062 $false
.sym 11064 RESET$2
.sym 11065 $abc$92916$n679
.sym 11066 $auto$simplemap.cc:250:simplemap_eqne$80251[1]
.sym 11067 $false
.sym 11069 $auto$simplemap.cc:250:simplemap_eqne$76135[8]$2
.sym 11070 I2C.is_read
.sym 11071 $false
.sym 11072 $false
.sym 11074 $abc$92916$n678_1
.sym 11075 $auto$simplemap.cc:250:simplemap_eqne$80251[1]
.sym 11076 $false
.sym 11077 $false
.sym 11079 $abc$92916$n726_1
.sym 11080 $abc$92916$n731
.sym 11081 $abc$92916$n689
.sym 11082 $false
.sym 11084 $abc$92916$n725
.sym 11085 $abc$92916$n732
.sym 11086 $auto$dff2dffe.cc:175:make_patterns_logic$80258
.sym 11087 $false
.sym 11091 $abc$92916$n763
.sym 11092 $abc$92916$n715
.sym 11093 $auto$dff2dffe.cc:175:make_patterns_logic$84067
.sym 11094 $abc$92916$n695
.sym 11095 $abc$92916$n714
.sym 11096 $abc$92916$n688
.sym 11097 $auto$dff2dffe.cc:175:make_patterns_logic$74485
.sym 11098 LED3$2
.sym 11165 $abc$92916$n714
.sym 11166 $abc$92916$n704
.sym 11167 $abc$92916$n685
.sym 11168 $false
.sym 11170 $abc$92916$n686
.sym 11171 $abc$92916$n676
.sym 11172 $abc$92916$n683
.sym 11173 $false
.sym 11175 $abc$92916$n738
.sym 11176 $abc$92916$n811
.sym 11177 $false
.sym 11178 $false
.sym 11180 $abc$92916$n714
.sym 11181 $abc$92916$n683
.sym 11182 $false
.sym 11183 $false
.sym 11185 $abc$92916$n710
.sym 11186 $abc$92916$n738
.sym 11187 $abc$92916$n811
.sym 11188 $false
.sym 11190 RESET$2
.sym 11191 $abc$92916$n695
.sym 11192 $auto$rtlil.cc:1692:NotGate$92623
.sym 11193 $abc$92916$n676
.sym 11195 $abc$92916$n711
.sym 11196 $abc$92916$n685
.sym 11197 $false
.sym 11198 $false
.sym 11200 I2C.wr
.sym 11201 $false
.sym 11202 $false
.sym 11203 $false
.sym 11204 $auto$dff2dffe.cc:175:make_patterns_logic$83913
.sym 11205 CLK$2$2
.sym 11206 $false
.sym 11207 $abc$92916$n702
.sym 11208 $auto$wreduce.cc:310:run$57529[3]
.sym 11209 $auto$dff2dffe.cc:175:make_patterns_logic$83232
.sym 11210 $abc$92916$n790
.sym 11211 $abc$92916$n694
.sym 11212 $abc$92916$n701
.sym 11213 LED2$2
.sym 11214 LED4$2
.sym 11281 $abc$92916$n697
.sym 11282 $abc$92916$n699
.sym 11283 $auto$simplemap.cc:250:simplemap_eqne$80251[1]
.sym 11284 $false
.sym 11286 $abc$92916$n678_1
.sym 11287 $abc$92916$n682
.sym 11288 $false
.sym 11289 $false
.sym 11291 $abc$92916$n682
.sym 11292 UART.tx_activity
.sym 11293 uart_double_ff
.sym 11294 last_uart_active
.sym 11296 $abc$92916$n678_1
.sym 11297 $abc$92916$n694
.sym 11298 $abc$92916$n696
.sym 11299 $2\uart_double_ff[0:0]
.sym 11301 $abc$92916$n695
.sym 11302 $abc$92916$n682
.sym 11303 $auto$dff2dffe.cc:158:make_patterns_logic$73200
.sym 11304 $false
.sym 11306 $abc$92916$n710
.sym 11307 $abc$92916$n711
.sym 11308 $auto$dff2dffe.cc:158:make_patterns_logic$73200
.sym 11309 $abc$92916$n693
.sym 11311 UART.tx_activity
.sym 11312 last_uart_active
.sym 11313 $abc$92916$n701
.sym 11314 $auto$dff2dffe.cc:175:make_patterns_logic$73101
.sym 11316 $2\uart_double_ff[0:0]
.sym 11317 $false
.sym 11318 $false
.sym 11319 $false
.sym 11320 $auto$dff2dffe.cc:175:make_patterns_logic$84512
.sym 11321 CLK$2$2
.sym 11322 $logic_not$top.v:66$10_Y$2
.sym 11323 $abc$92916$n791
.sym 11324 $auto$dff2dffe.cc:175:make_patterns_logic$73101
.sym 11325 $abc$92916$n697
.sym 11326 $2\uart_double_ff[0:0]
.sym 11327 $abc$92916$n708
.sym 11328 $abc$92916$n717
.sym 11329 $abc$92916$n792
.sym 11330 last_trans
.sym 11397 $abc$92916$n795
.sym 11398 i2c_input_data_type[3]
.sym 11399 $false
.sym 11400 $false
.sym 11402 $abc$92916$n677
.sym 11403 $abc$92916$n694
.sym 11404 $abc$92916$n708
.sym 11405 I2C.is_read
.sym 11407 $abc$92916$n794
.sym 11408 i2c_input_data_type[3]
.sym 11409 $false
.sym 11410 $false
.sym 11412 $abc$92916$n795
.sym 11413 i2c_input_data_type[1]
.sym 11414 $false
.sym 11415 $false
.sym 11422 $abc$92916$n793
.sym 11423 $abc$92916$n808
.sym 11424 $abc$92916$n947
.sym 11425 i2c_input_data_type[1]
.sym 11427 I2C.received_byte[0]
.sym 11428 $abc$92916$n1097
.sym 11429 I2C.is_read
.sym 11430 $false
.sym 11436 $auto$dff2dffe.cc:175:make_patterns_logic$71223
.sym 11437 CLK$2$2
.sym 11438 $auto$rtlil.cc:1692:NotGate$92623
.sym 11439 $abc$92916$n1177
.sym 11440 $abc$92916$n1168
.sym 11441 $abc$92916$n1175
.sym 11442 $abc$92916$n1172
.sym 11443 $abc$92916$n1176
.sym 11444 $abc$92916$n1170_1
.sym 11445 $abc$92916$n1173
.sym 11446 $abc$92916$n1174
.sym 11513 $false
.sym 11514 $false
.sym 11515 $false
.sym 11516 $false
.sym 11518 $false
.sym 11519 $false
.sym 11520 $false
.sym 11521 $false
.sym 11523 I2C.is_read
.sym 11524 $techmap\I2C.$procmux$19804_Y
.sym 11525 I2C.i2c_state_machine
.sym 11526 I2C.i2c_start_latency
.sym 11528 I2C.wr
.sym 11529 I2C_HID_DESC.last_rd_request
.sym 11530 RESET$2
.sym 11531 $false
.sym 11538 I2C.i2c_state_machine
.sym 11539 I2C.i2c_start_latency
.sym 11540 $false
.sym 11541 $false
.sym 11548 I2C.wr
.sym 11549 $false
.sym 11550 $false
.sym 11551 $false
.sym 11552 $true
.sym 11553 CLK$2$2
.sym 11554 $logic_not$top.v:66$10_Y$2
.sym 11555 $abc$92916$n1158
.sym 11556 $abc$92916$n1169
.sym 11557 $abc$92916$n1121
.sym 11558 $abc$92916$n1157
.sym 11559 $auto$alumacc.cc:470:replace_alu$57572.B_buf[1]
.sym 11560 $auto$alumacc.cc:483:replace_alu$57573[1]
.sym 11561 I2C.i2c_bit_counter[1]
.sym 11562 I2C.SCL_LAST
.sym 11591 $true
.sym 11628 $auto$alumacc.cc:483:replace_alu$57573[0]$2
.sym 11629 $false
.sym 11630 $auto$alumacc.cc:483:replace_alu$57573[0]
.sym 11631 $false
.sym 11632 $false
.sym 11633 $auto$alumacc.cc:484:replace_alu$57574[1]
.sym 11635 $false
.sym 11636 $auto$alumacc.cc:483:replace_alu$57573[1]
.sym 11638 $auto$alumacc.cc:484:replace_alu$57574[2]
.sym 11640 $false
.sym 11641 $auto$alumacc.cc:483:replace_alu$57573[2]
.sym 11643 $auto$alumacc.cc:484:replace_alu$57574[3]$2
.sym 11645 $false
.sym 11646 $auto$alumacc.cc:483:replace_alu$57573[3]
.sym 11652 $auto$alumacc.cc:484:replace_alu$57574[3]$2
.sym 11654 $auto$alumacc.cc:483:replace_alu$57687[0]
.sym 11655 $false
.sym 11656 $false
.sym 11657 $false
.sym 11671 $abc$92916$n1120
.sym 11672 $abc$92916$n1117
.sym 11673 $abc$92916$n1153
.sym 11674 $abc$92916$n1160
.sym 11675 $abc$92916$n1135
.sym 11676 $abc$92916$n1152
.sym 11677 $abc$92916$n1151
.sym 11678 $abc$92916$n1122
.sym 11750 $false
.sym 11751 $logic_not$top.v:66$10_Y$2
.sym 11752 rststate[0]
.sym 11753 $false
.sym 11755 $techmap\I2C.$procmux$19804_Y
.sym 11756 I2C.i2c_bit_counter[2]
.sym 11757 $false
.sym 11758 $false
.sym 11765 $auto$alumacc.cc:470:replace_alu$57572.B_buf[2]
.sym 11766 $false
.sym 11767 $false
.sym 11768 $false
.sym 11770 $abc$92916$n1160
.sym 11771 $abc$92916$n1157
.sym 11772 $auto$alumacc.cc:470:replace_alu$57572.B_buf[2]
.sym 11773 $false
.sym 11780 $abc$92916$n946
.sym 11781 $add$top.v:66$11_Y[0]
.sym 11782 $false
.sym 11783 $false
.sym 11784 $true
.sym 11785 CLK$2$2
.sym 11786 $false
.sym 11861 $auto$dff2dffe.cc:175:make_patterns_logic$81361
.sym 11887 $techmap\I2C.FLT_SCL.$procmux$1018_Y[0]
.sym 11888 $auto$wreduce.cc:310:run$57520[0]
.sym 11889 $auto$wreduce.cc:310:run$57520[2]
.sym 11890 $auto$dff2dffe.cc:158:make_patterns_logic$92290
.sym 11891 $abc$92916$n933
.sym 11892 I2C.FLT_SCL.counter[2]
.sym 11893 I2C.FLT_SCL.counter[1]
.sym 11894 I2C.FLT_SCL.counter[0]
.sym 11962 $abc$92916$n615
.sym 11963 $abc$92916$n632
.sym 11964 KEYBOARD.row_time[2]
.sym 11965 KEYBOARD.row_time[3]
.sym 11972 KEYBOARD.row_time[2]
.sym 11973 KEYBOARD.row_time[3]
.sym 11974 $false
.sym 11975 $false
.sym 11977 $abc$92916$n615
.sym 11978 $abc$92916$n619
.sym 11979 KEYBOARD.row_time[2]
.sym 11980 KEYBOARD.row_time[3]
.sym 11987 $abc$92916$n622
.sym 11988 $abc$92916$n632
.sym 11989 $abc$92916$n633
.sym 11990 $abc$92916$n625
.sym 11992 $abc$92916$n622
.sym 11993 $abc$92916$n632
.sym 11994 $abc$92916$n633
.sym 11995 $abc$92916$n625
.sym 12006 KBD_COLUMNS[4]$2
.sym 12008 $abc$92916$n1224
.sym 12010 $abc$92916$n1233
.sym 12011 $abc$92916$n1243_1
.sym 12012 $auto$wreduce.cc:310:run$57525[0]
.sym 12013 $auto$wreduce.cc:310:run$57524[0]
.sym 12014 $abc$92916$n1232
.sym 12015 KEYBOARD.report[6][6]
.sym 12118 $abc$92916$n663
.sym 12119 $abc$92916$n617
.sym 12120 $abc$92916$n629
.sym 12121 $abc$92916$n619
.sym 12123 $abc$92916$n633
.sym 12124 KEYBOARD.row_time[2]
.sym 12125 KEYBOARD.row_time[3]
.sym 12126 $false
.sym 12128 $abc$92916$n617
.sym 12129 $abc$92916$n629
.sym 12130 $abc$92916$n619
.sym 12131 $abc$92916$n630
.sym 12133 KEYBOARD.kbd_code_hid[4]
.sym 12134 $false
.sym 12135 $false
.sym 12136 $false
.sym 12138 KEYBOARD.kbd_code_hid[1]
.sym 12139 $false
.sym 12140 $false
.sym 12141 $false
.sym 12143 KEYBOARD.kbd_code_hid[7]
.sym 12144 $false
.sym 12145 $false
.sym 12146 $false
.sym 12153 KEYBOARD.kbd_code_hid[0]
.sym 12154 $false
.sym 12155 $false
.sym 12156 $false
.sym 12157 $auto$dff2dffe.cc:175:make_patterns_logic$85564
.sym 12158 CLK$2$2
.sym 12159 $auto$rtlil.cc:1692:NotGate$92753
.sym 12160 $abc$92916$n1228_1
.sym 12161 $abc$92916$n1225_1
.sym 12162 $abc$92916$n855
.sym 12163 $auto$dff2dffe.cc:175:make_patterns_logic$85564
.sym 12164 $auto$wreduce.cc:310:run$57527[0]
.sym 12165 $abc$92916$n1229_1
.sym 12166 $abc$92916$n1247_1
.sym 12167 $abc$92916$n845
.sym 12234 $abc$92916$n852_1
.sym 12235 $abc$92916$n853
.sym 12236 $abc$92916$n854
.sym 12237 $false
.sym 12239 $abc$92916$n871
.sym 12240 $abc$92916$n874
.sym 12241 $abc$92916$n875
.sym 12242 $false
.sym 12244 KEYBOARD.kbd_code_hid[1]
.sym 12245 KEYBOARD.kbd_code_hid[0]
.sym 12246 KEYBOARD.report[6][0]
.sym 12247 KEYBOARD.report[6][1]
.sym 12249 KEYBOARD.kbd_code_hid[4]
.sym 12250 KEYBOARD.kbd_code_hid[5]
.sym 12251 KEYBOARD.report[6][4]
.sym 12252 KEYBOARD.report[6][5]
.sym 12254 KEYBOARD.kbd_code_hid[3]
.sym 12255 KEYBOARD.kbd_code_hid[2]
.sym 12256 KEYBOARD.report[6][2]
.sym 12257 KEYBOARD.report[6][3]
.sym 12259 KEYBOARD.report[6][0]
.sym 12260 KEYBOARD.report[6][1]
.sym 12261 KEYBOARD.report[6][2]
.sym 12262 KEYBOARD.report[6][3]
.sym 12264 KEYBOARD.report[6][4]
.sym 12265 KEYBOARD.report[6][5]
.sym 12266 KEYBOARD.report[6][6]
.sym 12267 KEYBOARD.report[6][7]
.sym 12269 KEYBOARD.kbd_code_hid[5]
.sym 12270 $false
.sym 12271 $false
.sym 12272 $false
.sym 12273 $auto$dff2dffe.cc:175:make_patterns_logic$85564
.sym 12274 CLK$2$2
.sym 12275 $auto$rtlil.cc:1692:NotGate$92753
.sym 12278 $auto$alumacc.cc:484:replace_alu$57671[1]
.sym 12279 $abc$92916$n1055_1
.sym 12280 $abc$92916$n1057
.sym 12281 $abc$92916$n1006
.sym 12282 $abc$92916$n1054
.sym 12283 $abc$92916$n1056
.sym 12350 KEYBOARD.report[1][0]
.sym 12351 $abc$92916$n1005
.sym 12352 $abc$92916$n1000
.sym 12353 $abc$92916$n1003
.sym 12355 $abc$92916$n1005
.sym 12356 KEYBOARD.report[1][4]
.sym 12357 KEYBOARD.report[5][4]
.sym 12358 $abc$92916$n1001
.sym 12360 $abc$92916$n1008
.sym 12361 KEYBOARD.report[4][4]
.sym 12362 KEYBOARD.report[6][4]
.sym 12363 $abc$92916$n1004
.sym 12365 $abc$92916$n1004
.sym 12366 KEYBOARD.report[6][7]
.sym 12367 $abc$92916$n1001
.sym 12368 KEYBOARD.report[5][7]
.sym 12370 $abc$92916$n1004
.sym 12371 KEYBOARD.report[6][0]
.sym 12372 $false
.sym 12373 $false
.sym 12375 $abc$92916$n1002_1
.sym 12376 KEYBOARD.report[3][0]
.sym 12377 KEYBOARD.report[5][0]
.sym 12378 $abc$92916$n1001
.sym 12380 KEYBOARD.kbd_code_hid[2]
.sym 12381 $false
.sym 12382 $false
.sym 12383 $false
.sym 12385 KEYBOARD.kbd_code_hid[3]
.sym 12386 $false
.sym 12387 $false
.sym 12388 $false
.sym 12389 $auto$dff2dffe.cc:175:make_patterns_logic$85564
.sym 12390 CLK$2$2
.sym 12391 $auto$rtlil.cc:1692:NotGate$92753
.sym 12392 $abc$92916$n878
.sym 12393 $abc$92916$n1016
.sym 12394 $abc$92916$n1014
.sym 12395 KEYBOARD.report[2][4]
.sym 12396 KEYBOARD.report[2][0]
.sym 12397 KEYBOARD.report[2][5]
.sym 12398 KEYBOARD.report[2][6]
.sym 12399 KEYBOARD.report[2][1]
.sym 12466 $abc$92916$n872
.sym 12467 $abc$92916$n873
.sym 12468 $false
.sym 12469 $false
.sym 12471 KEYBOARD.report[5][0]
.sym 12472 KEYBOARD.report[5][1]
.sym 12473 KEYBOARD.report[5][2]
.sym 12474 KEYBOARD.report[5][3]
.sym 12476 $abc$92916$n880
.sym 12477 $abc$92916$n881
.sym 12478 $abc$92916$n882
.sym 12479 $false
.sym 12481 KEYBOARD.kbd_code_hid[1]
.sym 12482 KEYBOARD.kbd_code_hid[0]
.sym 12483 KEYBOARD.report[5][0]
.sym 12484 KEYBOARD.report[5][1]
.sym 12486 $abc$92916$n1004
.sym 12487 KEYBOARD.report[6][1]
.sym 12488 $abc$92916$n1001
.sym 12489 KEYBOARD.report[5][1]
.sym 12491 KEYBOARD.kbd_code_hid[3]
.sym 12492 KEYBOARD.kbd_code_hid[2]
.sym 12493 KEYBOARD.report[5][2]
.sym 12494 KEYBOARD.report[5][3]
.sym 12496 $techmap\KEYBOARD.$procmux$5651_Y[0]
.sym 12497 $false
.sym 12498 $false
.sym 12499 $false
.sym 12501 $techmap\KEYBOARD.$procmux$5651_Y[4]
.sym 12502 $false
.sym 12503 $false
.sym 12504 $false
.sym 12505 $auto$dff2dffe.cc:175:make_patterns_logic$87074
.sym 12506 CLK$2$2
.sym 12507 $logic_not$top.v:66$10_Y$2
.sym 12508 $abc$92916$n1002_1
.sym 12509 $abc$92916$n1037
.sym 12510 $abc$92916$n1009
.sym 12511 $abc$92916$n867
.sym 12512 $abc$92916$n1024
.sym 12513 $abc$92916$n900
.sym 12514 KEYBOARD.report[3][2]
.sym 12515 KEYBOARD.report[3][1]
.sym 12582 $abc$92916$n1004
.sym 12583 KEYBOARD.report[6][2]
.sym 12584 $abc$92916$n1001
.sym 12585 KEYBOARD.report[5][2]
.sym 12587 KEYBOARD.report[3][2]
.sym 12588 $abc$92916$n1002_1
.sym 12589 $abc$92916$n1022
.sym 12590 $abc$92916$n1023
.sym 12592 KEYBOARD.report[0][3]
.sym 12593 $abc$92916$n1010_1
.sym 12594 $abc$92916$n1027
.sym 12595 $2\INT[0:0]
.sym 12597 $abc$92916$n1002_1
.sym 12598 KEYBOARD.report[3][3]
.sym 12599 KEYBOARD.report[5][3]
.sym 12600 $abc$92916$n1001
.sym 12602 KEYBOARD.report[0][3]
.sym 12603 $abc$92916$n1009
.sym 12604 $abc$92916$n1028
.sym 12605 $abc$92916$n1031
.sym 12607 $abc$92916$n1004
.sym 12608 KEYBOARD.report[6][3]
.sym 12609 $false
.sym 12610 $false
.sym 12612 KEYBOARD.report[1][3]
.sym 12613 $abc$92916$n1005
.sym 12614 $abc$92916$n1029_1
.sym 12615 $abc$92916$n1030
.sym 12617 $techmap\KEYBOARD.$procmux$5651_Y[3]
.sym 12618 $false
.sym 12619 $false
.sym 12620 $false
.sym 12621 $auto$dff2dffe.cc:175:make_patterns_logic$89305
.sym 12622 CLK$2$2
.sym 12623 $logic_not$top.v:66$10_Y$2
.sym 12624 $abc$92916$n908
.sym 12625 $abc$92916$n910
.sym 12626 $abc$92916$n907
.sym 12627 $abc$92916$n909
.sym 12628 $abc$92916$n863
.sym 12629 $abc$92916$n1007
.sym 12630 $sub$top.v:122$51_Y[2]
.sym 12631 KEYBOARD.report[2][2]
.sym 12698 wr_cnt[0]
.sym 12699 wr_cnt[1]
.sym 12700 $sub$top.v:122$51_Y[0]
.sym 12701 $sub$top.v:122$51_Y[2]
.sym 12708 wr_cnt[0]
.sym 12709 wr_cnt[1]
.sym 12710 wr_cnt[2]
.sym 12711 wr_cnt[3]
.sym 12713 $abc$92916$n1008
.sym 12714 KEYBOARD.report[4][2]
.sym 12715 $false
.sym 12716 $false
.sym 12718 wr_cnt[0]
.sym 12719 wr_cnt[1]
.sym 12720 $sub$top.v:122$51_Y[0]
.sym 12721 $sub$top.v:122$51_Y[2]
.sym 12723 $techmap\KEYBOARD.$procmux$5651_Y[2]
.sym 12724 $false
.sym 12725 $false
.sym 12726 $false
.sym 12733 $techmap\KEYBOARD.$procmux$5651_Y[3]
.sym 12734 $false
.sym 12735 $false
.sym 12736 $false
.sym 12737 $auto$dff2dffe.cc:175:make_patterns_logic$87074
.sym 12738 CLK$2$2
.sym 12739 $logic_not$top.v:66$10_Y$2
.sym 12740 $abc$92916$n965
.sym 12741 $auto$alumacc.cc:483:replace_alu$57552[3]
.sym 12742 $abc$92916$n687
.sym 12743 $abc$92916$n964
.sym 12745 $abc$92916$n966
.sym 12746 $auto$alumacc.cc:483:replace_alu$57552[1]
.sym 12747 UART.tx_bit_counter[1]
.sym 12776 $false
.sym 12813 $auto$alumacc.cc:484:replace_alu$57647[3]
.sym 12815 wr_cnt[3]
.sym 12816 ring_wr[0]
.sym 12818 $auto$alumacc.cc:484:replace_alu$57647[4]
.sym 12819 $false
.sym 12820 $false
.sym 12821 ring_wr[1]
.sym 12822 $auto$alumacc.cc:484:replace_alu$57647[3]
.sym 12823 $auto$alumacc.cc:484:replace_alu$57647[5]
.sym 12824 $false
.sym 12825 $false
.sym 12826 ring_wr[2]
.sym 12827 $auto$alumacc.cc:484:replace_alu$57647[4]
.sym 12828 $auto$alumacc.cc:484:replace_alu$57647[6]$2
.sym 12829 $false
.sym 12830 $false
.sym 12831 ring_wr[3]
.sym 12832 $auto$alumacc.cc:484:replace_alu$57647[5]
.sym 12837 $auto$alumacc.cc:484:replace_alu$57647[6]$2
.sym 12839 $2\ring_wr[3:0][2]
.sym 12840 $abc$92916$n982
.sym 12841 $2\INT[0:0]
.sym 12842 $false
.sym 12844 $8\report_data_adr[7:0][5]
.sym 12845 $abc$92916$n983
.sym 12846 $abc$92916$n687
.sym 12847 $false
.sym 12849 $auto$alumacc.cc:470:replace_alu$57551.B_buf[2]
.sym 12850 $false
.sym 12851 $false
.sym 12852 $false
.sym 12853 $auto$dff2dffe.cc:175:make_patterns_logic$85121
.sym 12854 CLK$2$2
.sym 12855 $eq$top.v:243$154_Y
.sym 12856 $abc$92916$n765
.sym 12857 $abc$92916$n766
.sym 12858 $abc$92916$n757
.sym 12859 $abc$92916$n783
.sym 12860 $abc$92916$n772
.sym 12861 $abc$92916$n767_1
.sym 12862 $abc$92916$n773_1
.sym 12863 ring_wr[1]
.sym 12930 $8\report_data_adr[7:0][6]
.sym 12931 $abc$92916$n990
.sym 12932 $abc$92916$n687
.sym 12933 $false
.sym 12935 $auto$dff2dffe.cc:158:make_patterns_logic$73200
.sym 12936 KEYBOARD.isr
.sym 12937 last_isr
.sym 12938 $false
.sym 12940 $add$top.v:184$103_Y[6]
.sym 12941 $2\ring_rd[3:0][3]
.sym 12942 $abc$92916$n733
.sym 12943 $false
.sym 12945 KEYBOARD.isr
.sym 12946 last_isr
.sym 12947 $false
.sym 12948 $false
.sym 12950 i2c_input_data_type[1]
.sym 12951 i2c_input_data_type[3]
.sym 12952 i2c_input_data_type[2]
.sym 12953 $false
.sym 12955 $add$top.v:184$103_Y[5]
.sym 12956 $2\ring_rd[3:0][2]
.sym 12957 $abc$92916$n733
.sym 12958 $false
.sym 12960 $2\ring_wr[3:0][3]
.sym 12961 $abc$92916$n989_1
.sym 12962 $2\INT[0:0]
.sym 12963 $false
.sym 12965 $techmap\KEYBOARD.$procmux$18803_CMP
.sym 12966 $false
.sym 12967 $false
.sym 12968 $false
.sym 12969 RESET$2
.sym 12970 CLK$2$2
.sym 12971 $false
.sym 12972 $auto$dff2dffe.cc:175:make_patterns_logic$78149
.sym 12973 $abc$92916$n756
.sym 12974 $abc$92916$n753
.sym 12975 $abc$92916$n758
.sym 12976 $abc$92916$n747
.sym 12977 $abc$92916$n754
.sym 12978 $abc$92916$n748
.sym 12979 temp_output_report[1]
.sym 13046 $abc$92916$n758
.sym 13047 $abc$92916$n757
.sym 13048 $abc$92916$n701
.sym 13049 $abc$92916$n715
.sym 13051 $abc$92916$n759
.sym 13052 $abc$92916$n763
.sym 13053 I2C.is_read
.sym 13054 $false
.sym 13056 $abc$92916$n676
.sym 13057 $abc$92916$n685
.sym 13058 $false
.sym 13059 $false
.sym 13061 $abc$92916$n682
.sym 13062 $auto$dff2dffe.cc:158:make_patterns_logic$73200
.sym 13063 $abc$92916$n685
.sym 13064 $false
.sym 13066 $abc$92916$n677
.sym 13067 $abc$92916$n733
.sym 13068 $abc$92916$n749_1
.sym 13069 $auto$simplemap.cc:250:simplemap_eqne$80251[1]
.sym 13071 $abc$92916$n761
.sym 13072 $abc$92916$n762_1
.sym 13073 $abc$92916$n686
.sym 13074 $abc$92916$n728
.sym 13076 KEYBOARD.isr
.sym 13077 last_isr
.sym 13078 $false
.sym 13079 $false
.sym 13081 KEYBOARD.isr
.sym 13082 $false
.sym 13083 $false
.sym 13084 $false
.sym 13085 $auto$dff2dffe.cc:175:make_patterns_logic$84333
.sym 13086 CLK$2$2
.sym 13087 $logic_not$top.v:66$10_Y$2
.sym 13088 $auto$rtlil.cc:1692:NotGate$92623
.sym 13089 $auto$alumacc.cc:483:replace_alu$57552[2]
.sym 13090 $abc$92916$n728
.sym 13091 $abc$92916$n686
.sym 13092 i2c_input_data_type[3]
.sym 13093 i2c_input_data_type[1]
.sym 13094 i2c_input_data_type[2]
.sym 13095 i2c_input_data_type[0]
.sym 13162 i2c_input_data_type[1]
.sym 13163 i2c_input_data_type[0]
.sym 13164 i2c_input_data_type[3]
.sym 13165 i2c_input_data_type[2]
.sym 13167 $abc$92916$n676
.sym 13168 $auto$rtlil.cc:1692:NotGate$92623
.sym 13169 $abc$92916$n687
.sym 13170 $false
.sym 13172 $abc$92916$n701
.sym 13173 $abc$92916$n715
.sym 13174 $abc$92916$n744
.sym 13175 $false
.sym 13177 $abc$92916$n687
.sym 13178 $abc$92916$n688
.sym 13179 $false
.sym 13180 $false
.sym 13182 $abc$92916$n695
.sym 13183 $2\uart_double_ff[0:0]
.sym 13184 $abc$92916$n676
.sym 13185 $abc$92916$n715
.sym 13187 I2C.wr
.sym 13188 last_wr
.sym 13189 $false
.sym 13190 $false
.sym 13192 $abc$92916$n687
.sym 13193 $abc$92916$n676
.sym 13194 $abc$92916$n685
.sym 13195 $abc$92916$n704
.sym 13197 temp_output_report[1]
.sym 13198 $false
.sym 13199 $false
.sym 13200 $false
.sym 13201 $auto$dff2dffe.cc:175:make_patterns_logic$83232
.sym 13202 CLK$2$2
.sym 13203 $logic_not$top.v:66$10_Y$2
.sym 13208 $auto$alumacc.cc:484:replace_alu$57553[3]
.sym 13210 temp_output_report[2]
.sym 13211 temp_output_report[0]
.sym 13278 $abc$92916$n677
.sym 13279 $abc$92916$n694
.sym 13280 $2\uart_double_ff[0:0]
.sym 13281 $false
.sym 13283 $false
.sym 13284 $false
.sym 13285 KEYBOARD.row_counter[3]
.sym 13286 $auto$alumacc.cc:484:replace_alu$57721[2]
.sym 13288 $abc$92916$n789
.sym 13289 $abc$92916$n790
.sym 13290 $false
.sym 13291 $false
.sym 13293 I2C.is_read
.sym 13294 $auto$dff2dffe.cc:175:make_patterns_logic$73101
.sym 13295 $abc$92916$n791
.sym 13296 $abc$92916$n701
.sym 13298 $abc$92916$n695
.sym 13299 $auto$rtlil.cc:1692:NotGate$92623
.sym 13300 $false
.sym 13301 $false
.sym 13303 $abc$92916$n702
.sym 13304 $abc$92916$n697
.sym 13305 $auto$simplemap.cc:250:simplemap_eqne$80251[1]
.sym 13306 $false
.sym 13308 temp_output_report[0]
.sym 13309 $false
.sym 13310 $false
.sym 13311 $false
.sym 13313 temp_output_report[2]
.sym 13314 $false
.sym 13315 $false
.sym 13316 $false
.sym 13317 $auto$dff2dffe.cc:175:make_patterns_logic$83232
.sym 13318 CLK$2$2
.sym 13319 $logic_not$top.v:66$10_Y$2
.sym 13320 $abc$92916$n1185_1
.sym 13321 $abc$92916$n729
.sym 13322 $abc$92916$n1131
.sym 13323 $abc$92916$n1132_1
.sym 13324 $abc$92916$n1182_1
.sym 13325 UART_TX_DATA[4]
.sym 13326 UART_TX_DATA[5]
.sym 13327 UART_TX_DATA[1]
.sym 13394 $abc$92916$n793
.sym 13395 $abc$92916$n808
.sym 13396 $abc$92916$n809
.sym 13397 $abc$92916$n792
.sym 13399 $abc$92916$n702
.sym 13400 $abc$92916$n708
.sym 13401 $false
.sym 13402 $false
.sym 13404 I2C_TRANS
.sym 13405 last_trans
.sym 13406 $false
.sym 13407 $false
.sym 13409 I2C_TRANS
.sym 13410 last_trans
.sym 13411 $false
.sym 13412 $false
.sym 13414 $abc$92916$n697
.sym 13415 $auto$simplemap.cc:250:simplemap_eqne$80251[1]
.sym 13416 $false
.sym 13417 $false
.sym 13419 $abc$92916$n677
.sym 13420 $abc$92916$n694
.sym 13421 $abc$92916$n708
.sym 13422 $abc$92916$n718
.sym 13424 $abc$92916$n702
.sym 13425 $abc$92916$n708
.sym 13426 I2C.is_read
.sym 13427 $false
.sym 13429 I2C_TRANS
.sym 13430 $false
.sym 13431 $false
.sym 13432 $false
.sym 13433 $auto$dff2dffe.cc:175:make_patterns_logic$84067
.sym 13434 CLK$2$2
.sym 13435 $logic_not$top.v:66$10_Y$2
.sym 13436 $abc$92916$n1171
.sym 13437 $abc$92916$n1129
.sym 13438 $abc$92916$n823
.sym 13439 $abc$92916$n1130
.sym 13440 $abc$92916$n1119
.sym 13441 $abc$92916$n1164_1
.sym 13442 I2C.SDA_DIR
.sym 13443 I2C.is_read
.sym 13510 $abc$92916$n1135
.sym 13511 $abc$92916$n1121
.sym 13512 $abc$92916$n1119
.sym 13513 $false
.sym 13515 $abc$92916$n1170_1
.sym 13516 $abc$92916$n1169
.sym 13517 $abc$92916$n820
.sym 13518 $abc$92916$n823
.sym 13520 $abc$92916$n1109
.sym 13521 $abc$92916$n1101
.sym 13522 $techmap\I2C.$sub$i2c_slave.v:143$226_Y[2]
.sym 13523 $false
.sym 13525 $abc$92916$n1121
.sym 13526 $abc$92916$n825
.sym 13527 $abc$92916$n1173
.sym 13528 $auto$simplemap.cc:250:simplemap_eqne$60443[0]
.sym 13530 $abc$92916$n1107
.sym 13531 $abc$92916$n1099
.sym 13532 $techmap\I2C.$sub$i2c_slave.v:143$226_Y[2]
.sym 13533 $false
.sym 13535 $abc$92916$n1177
.sym 13536 $abc$92916$n1172
.sym 13537 $abc$92916$n1174
.sym 13538 $abc$92916$n1171
.sym 13540 $abc$92916$n1105
.sym 13541 $abc$92916$n1097
.sym 13542 $techmap\I2C.$sub$i2c_slave.v:143$226_Y[2]
.sym 13543 $false
.sym 13545 $abc$92916$n1176
.sym 13546 $abc$92916$n1175
.sym 13547 $abc$92916$n825
.sym 13548 $auto$simplemap.cc:250:simplemap_eqne$60443[0]
.sym 13552 $abc$92916$n1125
.sym 13553 $abc$92916$n1140
.sym 13554 $abc$92916$n1124
.sym 13555 $abc$92916$n1116
.sym 13556 $auto$alumacc.cc:483:replace_alu$57687[0]
.sym 13557 $abc$92916$n1154
.sym 13558 I2C.i2c_bit_counter[0]
.sym 13559 I2C.wr
.sym 13626 $abc$92916$n825
.sym 13627 $abc$92916$n1155
.sym 13628 $abc$92916$n823
.sym 13629 $auto$alumacc.cc:484:replace_alu$57574[3]
.sym 13631 $abc$92916$n1122
.sym 13632 $auto$alumacc.cc:484:replace_alu$57574[3]
.sym 13633 $abc$92916$n1119
.sym 13634 $abc$92916$n1128
.sym 13636 $abc$92916$n1122
.sym 13637 $auto$alumacc.cc:484:replace_alu$57574[3]
.sym 13638 $false
.sym 13639 $false
.sym 13641 $abc$92916$n1151
.sym 13642 $abc$92916$n823
.sym 13643 $false
.sym 13644 $false
.sym 13646 $techmap\I2C.$procmux$19804_Y
.sym 13647 I2C.i2c_bit_counter[1]
.sym 13648 $false
.sym 13649 $false
.sym 13651 $auto$alumacc.cc:470:replace_alu$57572.B_buf[1]
.sym 13652 $false
.sym 13653 $false
.sym 13654 $false
.sym 13656 $abc$92916$n1158
.sym 13657 $abc$92916$n1157
.sym 13658 $auto$alumacc.cc:470:replace_alu$57572.B_buf[1]
.sym 13659 $false
.sym 13661 I2C.FLT_SCL.out
.sym 13662 $false
.sym 13663 $false
.sym 13664 $false
.sym 13665 $true
.sym 13666 CLK$2$2
.sym 13667 $false
.sym 13668 $abc$92916$n1127_1
.sym 13669 $abc$92916$n1136
.sym 13670 $abc$92916$n1128
.sym 13671 $abc$92916$n1115
.sym 13672 $abc$92916$n1166
.sym 13673 $abc$92916$n1137
.sym 13674 $abc$92916$n1123
.sym 13675 I2C.i2c_state_machine
.sym 13742 $abc$92916$n820
.sym 13743 $abc$92916$n1121
.sym 13744 $false
.sym 13745 $false
.sym 13747 $abc$92916$n1118
.sym 13748 I2C.SCL_LAST
.sym 13749 I2C.FLT_SCL.out
.sym 13750 $false
.sym 13752 $auto$alumacc.cc:484:replace_alu$57574[3]
.sym 13753 I2C.SCL_LAST
.sym 13754 I2C.FLT_SCL.out
.sym 13755 $abc$92916$n820
.sym 13757 $abc$92916$n1155
.sym 13758 $abc$92916$n823
.sym 13759 $techmap\I2C.$sub$i2c_slave.v:143$226_Y[2]
.sym 13760 $auto$alumacc.cc:484:replace_alu$57574[3]
.sym 13762 $abc$92916$n1118
.sym 13763 $abc$92916$n1122
.sym 13764 $false
.sym 13765 $false
.sym 13767 $abc$92916$n1118
.sym 13768 $abc$92916$n1122
.sym 13769 $auto$alumacc.cc:484:replace_alu$57574[3]
.sym 13770 $abc$92916$n1153
.sym 13772 $abc$92916$n1120
.sym 13773 $abc$92916$n1117
.sym 13774 $auto$alumacc.cc:484:replace_alu$57574[3]
.sym 13775 $abc$92916$n1152
.sym 13777 I2C.SCL_LAST
.sym 13778 I2C.FLT_SCL.out
.sym 13779 $false
.sym 13780 $false
.sym 13828 $auto$wreduce.cc:310:run$57529[3]
.sym 13858 $auto$rtlil.cc:1692:NotGate$92893
.sym 13884 $auto$dff2dffe.cc:175:make_patterns_logic$92275
.sym 13885 $abc$92916$n652
.sym 13886 $techmap\I2C.FLT_SCL.$procmux$1018_Y[1]
.sym 13887 $abc$92916$n612
.sym 13888 $abc$92916$n934
.sym 13889 $abc$92916$n650
.sym 13890 $abc$92916$n644
.sym 13891 I2C.FLT_SCL.out
.sym 13959 $abc$92916$n933
.sym 13960 $auto$wreduce.cc:310:run$57520[0]
.sym 13961 $false
.sym 13962 $false
.sym 13964 $false
.sym 13965 I2C.FLT_SCL.counter[0]
.sym 13966 $false
.sym 13967 $true$2
.sym 13969 $false
.sym 13970 I2C.FLT_SCL.counter[2]
.sym 13971 $true$2
.sym 13972 $auto$alumacc.cc:484:replace_alu$57691[1]
.sym 13974 $abc$92916$n933
.sym 13975 I2C.FLT_SCL.out
.sym 13976 I2C.SCLF
.sym 13977 $false
.sym 13979 I2C.FLT_SCL.counter[0]
.sym 13980 I2C.FLT_SCL.counter[1]
.sym 13981 I2C.FLT_SCL.counter[2]
.sym 13982 $false
.sym 13984 $abc$92916$n933
.sym 13985 $auto$wreduce.cc:310:run$57520[2]
.sym 13986 $false
.sym 13987 $false
.sym 13989 $techmap\I2C.FLT_SCL.$procmux$1018_Y[1]
.sym 13990 $false
.sym 13991 $false
.sym 13992 $false
.sym 13994 $techmap\I2C.FLT_SCL.$procmux$1018_Y[0]
.sym 13995 $false
.sym 13996 $false
.sym 13997 $false
.sym 13998 $auto$dff2dffe.cc:158:make_patterns_logic$92290
.sym 13999 CLK$2$2
.sym 14000 $logic_not$top.v:66$10_Y$2
.sym 14003 KBD_COLUMNS[5]$2
.sym 14007 $auto$alumacc.cc:484:replace_alu$57691[1]
.sym 14008 $abc$92916$n655
.sym 14009 $abc$92916$n659
.sym 14010 $abc$92916$n654
.sym 14011 $auto$rtlil.cc:1692:NotGate$92753
.sym 14012 $abc$92916$n664
.sym 14115 $abc$92916$n1230
.sym 14116 $abc$92916$n1225_1
.sym 14117 $abc$92916$n1233
.sym 14118 $abc$92916$n1232
.sym 14125 $abc$92916$n641
.sym 14126 $auto$wreduce.cc:310:run$57525[0]
.sym 14127 $false
.sym 14128 $false
.sym 14130 $abc$92916$n647
.sym 14131 $abc$92916$n653
.sym 14132 KEYBOARD.COLS_SHADOW[3]
.sym 14133 $abc$92916$n651
.sym 14135 $false
.sym 14136 $false
.sym 14137 $false
.sym 14138 $false
.sym 14140 $false
.sym 14141 $true$2
.sym 14142 $false
.sym 14143 $false
.sym 14145 $abc$92916$n647
.sym 14146 $abc$92916$n653
.sym 14147 $auto$wreduce.cc:310:run$57524[0]
.sym 14148 KEYBOARD.COLS_SHADOW[3]
.sym 14150 KEYBOARD.kbd_code_hid[6]
.sym 14151 $false
.sym 14152 $false
.sym 14153 $false
.sym 14154 $auto$dff2dffe.cc:175:make_patterns_logic$85564
.sym 14155 CLK$2$2
.sym 14156 $auto$rtlil.cc:1692:NotGate$92753
.sym 14157 $abc$92916$n627
.sym 14158 $abc$92916$n660
.sym 14159 $abc$92916$n1221
.sym 14160 KEYBOARD.temp[3]
.sym 14161 KEYBOARD.temp[2]
.sym 14162 KEYBOARD.kbd_code[1]
.sym 14163 KEYBOARD.temp[0]
.sym 14164 KEYBOARD.temp[7]
.sym 14231 $auto$wreduce.cc:310:run$57527[0]
.sym 14232 $auto$wreduce.cc:310:run$57528[0]
.sym 14233 $abc$92916$n1229_1
.sym 14234 $abc$92916$n1218
.sym 14236 $abc$92916$n1228_1
.sym 14237 $abc$92916$n1226_1
.sym 14238 $abc$92916$n1227
.sym 14239 $false
.sym 14241 KEYBOARD.kbd_code_hid[7]
.sym 14242 KEYBOARD.kbd_code_hid[6]
.sym 14243 KEYBOARD.report[6][6]
.sym 14244 KEYBOARD.report[6][7]
.sym 14246 $abc$92916$n870
.sym 14247 $abc$92916$n845
.sym 14248 $abc$92916$n856
.sym 14249 $false
.sym 14251 $false
.sym 14252 $false
.sym 14253 $false
.sym 14254 $false
.sym 14256 $abc$92916$n621
.sym 14257 $abc$92916$n627
.sym 14258 $false
.sym 14259 $false
.sym 14261 $abc$92916$n1218
.sym 14262 $abc$92916$n1229_1
.sym 14263 $abc$92916$n1226_1
.sym 14264 $false
.sym 14266 $auto$rtlil.cc:1692:NotGate$92753
.sym 14267 $abc$92916$n846
.sym 14268 $abc$92916$n851
.sym 14269 $abc$92916$n855
.sym 14273 $abc$92916$n917
.sym 14274 $abc$92916$n916
.sym 14275 $abc$92916$n638
.sym 14276 $abc$92916$n915
.sym 14277 $abc$92916$n918
.sym 14278 $techmap\KEYBOARD.$procmux$5651_Y[0]
.sym 14279 $abc$92916$n1017_1
.sym 14280 KEYBOARD.report[3][7]
.sym 14309 $true
.sym 14346 wr_cnt[0]$3
.sym 14347 $false
.sym 14348 wr_cnt[0]
.sym 14349 $false
.sym 14350 $false
.sym 14351 $auto$alumacc.cc:484:replace_alu$57671[1]$2
.sym 14353 wr_cnt[1]
.sym 14354 $true$2
.sym 14360 $auto$alumacc.cc:484:replace_alu$57671[1]$2
.sym 14362 KEYBOARD.report[0][7]
.sym 14363 $abc$92916$n1009
.sym 14364 $abc$92916$n1056
.sym 14365 $abc$92916$n1059
.sym 14367 $abc$92916$n1008
.sym 14368 KEYBOARD.report[4][7]
.sym 14369 $false
.sym 14370 $false
.sym 14372 $abc$92916$n1008
.sym 14373 KEYBOARD.report[4][0]
.sym 14374 $abc$92916$n1007
.sym 14375 KEYBOARD.report[2][0]
.sym 14377 KEYBOARD.report[0][7]
.sym 14378 $abc$92916$n1010_1
.sym 14379 $abc$92916$n1055_1
.sym 14380 $2\INT[0:0]
.sym 14382 KEYBOARD.report[3][7]
.sym 14383 $abc$92916$n1002_1
.sym 14384 $abc$92916$n1057
.sym 14385 $abc$92916$n1058
.sym 14389 $abc$92916$n1043
.sym 14390 $abc$92916$n1059
.sym 14391 $abc$92916$n653
.sym 14392 $abc$92916$n1045
.sym 14393 $abc$92916$n1052
.sym 14394 $abc$92916$n919
.sym 14395 $abc$92916$n914
.sym 14396 KEYBOARD.report[5][1]
.sym 14463 $abc$92916$n883
.sym 14464 $abc$92916$n879
.sym 14465 $auto$rtlil.cc:1692:NotGate$92753
.sym 14466 $abc$92916$n846
.sym 14468 $abc$92916$n1007
.sym 14469 KEYBOARD.report[2][1]
.sym 14470 $false
.sym 14471 $false
.sym 14473 KEYBOARD.report[3][1]
.sym 14474 $abc$92916$n1002_1
.sym 14475 $abc$92916$n1015
.sym 14476 $abc$92916$n1016
.sym 14478 $techmap\KEYBOARD.$procmux$5651_Y[4]
.sym 14479 $false
.sym 14480 $false
.sym 14481 $false
.sym 14483 $techmap\KEYBOARD.$procmux$5651_Y[0]
.sym 14484 $false
.sym 14485 $false
.sym 14486 $false
.sym 14488 $techmap\KEYBOARD.$procmux$5651_Y[5]
.sym 14489 $false
.sym 14490 $false
.sym 14491 $false
.sym 14493 $techmap\KEYBOARD.$procmux$5651_Y[6]
.sym 14494 $false
.sym 14495 $false
.sym 14496 $false
.sym 14498 $techmap\KEYBOARD.$procmux$5651_Y[1]
.sym 14499 $false
.sym 14500 $false
.sym 14501 $false
.sym 14502 $auto$dff2dffe.cc:175:make_patterns_logic$90124
.sym 14503 CLK$2$2
.sym 14504 $logic_not$top.v:66$10_Y$2
.sym 14505 $abc$92916$n902
.sym 14506 $abc$92916$n901
.sym 14507 $abc$92916$n897
.sym 14508 $abc$92916$n898
.sym 14509 $abc$92916$n866
.sym 14510 $abc$92916$n899
.sym 14511 KEYBOARD.report[0][5]
.sym 14512 KEYBOARD.report[0][3]
.sym 14579 wr_cnt[0]
.sym 14580 wr_cnt[1]
.sym 14581 $sub$top.v:122$51_Y[0]
.sym 14582 $sub$top.v:122$51_Y[2]
.sym 14584 $abc$92916$n1007
.sym 14585 KEYBOARD.report[2][4]
.sym 14586 KEYBOARD.report[3][4]
.sym 14587 $abc$92916$n1002_1
.sym 14589 wr_cnt[0]
.sym 14590 wr_cnt[1]
.sym 14591 $sub$top.v:122$51_Y[0]
.sym 14592 $sub$top.v:122$51_Y[2]
.sym 14594 KEYBOARD.report[3][0]
.sym 14595 KEYBOARD.report[3][1]
.sym 14596 KEYBOARD.report[3][2]
.sym 14597 KEYBOARD.report[3][3]
.sym 14599 $abc$92916$n1007
.sym 14600 KEYBOARD.report[2][2]
.sym 14601 $abc$92916$n1005
.sym 14602 KEYBOARD.report[1][2]
.sym 14604 KEYBOARD.kbd_code_hid[3]
.sym 14605 KEYBOARD.kbd_code_hid[2]
.sym 14606 KEYBOARD.report[3][2]
.sym 14607 KEYBOARD.report[3][3]
.sym 14609 $techmap\KEYBOARD.$procmux$5651_Y[2]
.sym 14610 $false
.sym 14611 $false
.sym 14612 $false
.sym 14614 $techmap\KEYBOARD.$procmux$5651_Y[1]
.sym 14615 $false
.sym 14616 $false
.sym 14617 $false
.sym 14618 $auto$dff2dffe.cc:175:make_patterns_logic$89305
.sym 14619 CLK$2$2
.sym 14620 $logic_not$top.v:66$10_Y$2
.sym 14621 $abc$92916$n1050
.sym 14622 $abc$92916$n906
.sym 14623 $techmap\KEYBOARD.$procmux$5651_Y[1]
.sym 14624 $abc$92916$n1031
.sym 14625 $abc$92916$n911
.sym 14626 $abc$92916$n862
.sym 14627 KEYBOARD.report[2][7]
.sym 14628 KEYBOARD.report[2][3]
.sym 14695 KEYBOARD.kbd_code_hid[4]
.sym 14696 KEYBOARD.kbd_code_hid[5]
.sym 14697 KEYBOARD.report[2][4]
.sym 14698 KEYBOARD.report[2][5]
.sym 14700 KEYBOARD.kbd_code_hid[1]
.sym 14701 KEYBOARD.kbd_code_hid[0]
.sym 14702 KEYBOARD.report[2][0]
.sym 14703 KEYBOARD.report[2][1]
.sym 14705 $abc$92916$n908
.sym 14706 $abc$92916$n909
.sym 14707 $abc$92916$n910
.sym 14708 $false
.sym 14710 KEYBOARD.kbd_code_hid[3]
.sym 14711 KEYBOARD.kbd_code_hid[2]
.sym 14712 KEYBOARD.report[2][2]
.sym 14713 KEYBOARD.report[2][3]
.sym 14715 KEYBOARD.report[2][0]
.sym 14716 KEYBOARD.report[2][1]
.sym 14717 KEYBOARD.report[2][2]
.sym 14718 KEYBOARD.report[2][3]
.sym 14720 wr_cnt[0]
.sym 14721 wr_cnt[1]
.sym 14722 $sub$top.v:122$51_Y[0]
.sym 14723 $sub$top.v:122$51_Y[2]
.sym 14725 $false
.sym 14726 wr_cnt[2]
.sym 14727 $true$2
.sym 14728 $auto$alumacc.cc:484:replace_alu$57671[1]
.sym 14730 $techmap\KEYBOARD.$procmux$5651_Y[2]
.sym 14731 $false
.sym 14732 $false
.sym 14733 $false
.sym 14734 $auto$dff2dffe.cc:175:make_patterns_logic$90124
.sym 14735 CLK$2$2
.sym 14736 $logic_not$top.v:66$10_Y$2
.sym 14737 $abc$92916$n751
.sym 14738 $auto$simplemap.cc:309:simplemap_lut$69070[7]
.sym 14739 $abc$92916$n750
.sym 14741 $abc$92916$n752
.sym 14742 $abc$92916$n759
.sym 14744 UART.tx_bit_counter[0]
.sym 14811 $abc$92916$n966
.sym 14812 wr_cnt[3]
.sym 14813 ring_wr[0]
.sym 14814 $abc$92916$n687
.sym 14816 $auto$alumacc.cc:470:replace_alu$57551.B_buf[3]
.sym 14817 $false
.sym 14818 $false
.sym 14819 $false
.sym 14821 wr_cnt[0]
.sym 14822 wr_cnt[1]
.sym 14823 wr_cnt[2]
.sym 14824 wr_cnt[3]
.sym 14826 $2\ring_wr[3:0][0]
.sym 14827 $abc$92916$n965
.sym 14828 $2\INT[0:0]
.sym 14829 $false
.sym 14836 $add$top.v:184$103_Y[3]
.sym 14837 $2\ring_rd[3:0][0]
.sym 14838 $abc$92916$n733
.sym 14839 $false
.sym 14841 UART.tx_bit_counter[0]
.sym 14842 UART.tx_bit_counter[1]
.sym 14843 $false
.sym 14844 $false
.sym 14846 $auto$alumacc.cc:483:replace_alu$57552[1]
.sym 14847 $false
.sym 14848 $false
.sym 14849 $false
.sym 14850 $auto$dff2dffe.cc:175:make_patterns_logic$85121
.sym 14851 CLK$2$2
.sym 14852 $eq$top.v:243$154_Y
.sym 14853 $abc$92916$n775
.sym 14854 $abc$92916$n774
.sym 14855 $abc$92916$n781
.sym 14856 $abc$92916$n779
.sym 14857 $abc$92916$n749_1
.sym 14858 $abc$92916$n780
.sym 14859 $abc$92916$n776
.sym 14860 ring_wr[3]
.sym 14927 $abc$92916$n774
.sym 14928 $abc$92916$n676
.sym 14929 $abc$92916$n783
.sym 14930 $abc$92916$n766
.sym 14932 $abc$92916$n767_1
.sym 14933 $abc$92916$n757
.sym 14934 $abc$92916$n752
.sym 14935 $abc$92916$n773_1
.sym 14937 $abc$92916$n676
.sym 14938 $abc$92916$n686
.sym 14939 $abc$92916$n728
.sym 14940 $false
.sym 14942 $abc$92916$n768
.sym 14943 $abc$92916$n733
.sym 14944 $abc$92916$n686
.sym 14945 $abc$92916$n728
.sym 14947 $abc$92916$n686
.sym 14948 $abc$92916$n734
.sym 14949 I2C.byte_counter[2]
.sym 14950 $false
.sym 14952 $abc$92916$n755
.sym 14953 $abc$92916$n768
.sym 14954 $abc$92916$n772
.sym 14955 $abc$92916$n761
.sym 14957 i2c_input_data_type[1]
.sym 14958 i2c_input_data_type[0]
.sym 14959 i2c_input_data_type[3]
.sym 14960 i2c_input_data_type[2]
.sym 14962 $2\ring_wr[3:0][1]
.sym 14963 $false
.sym 14964 $false
.sym 14965 $false
.sym 14966 $auto$dff2dffe.cc:175:make_patterns_logic$73370
.sym 14967 CLK$2$2
.sym 14968 $logic_not$top.v:66$10_Y$2
.sym 14969 $abc$92916$n733
.sym 14970 $auto$alumacc.cc:483:replace_alu$57552[0]
.sym 14972 $abc$92916$n1180_1
.sym 14973 $techmap\UART.$sub$uart.v:40$540_Y[0]
.sym 14974 $abc$92916$n730
.sym 14975 $abc$92916$n734
.sym 14976 UART.tx_line
.sym 15043 $abc$92916$n747
.sym 15044 $abc$92916$n756
.sym 15045 $abc$92916$n744
.sym 15046 $abc$92916$n760
.sym 15048 $abc$92916$n753
.sym 15049 $abc$92916$n758
.sym 15050 $abc$92916$n757
.sym 15051 $false
.sym 15053 $abc$92916$n730
.sym 15054 $abc$92916$n754
.sym 15055 $false
.sym 15056 $false
.sym 15058 $abc$92916$n749_1
.sym 15059 $abc$92916$n734
.sym 15060 $abc$92916$n759
.sym 15061 I2C.is_read
.sym 15063 $abc$92916$n755
.sym 15064 i2c_input_data_type[0]
.sym 15065 $abc$92916$n753
.sym 15066 $abc$92916$n748
.sym 15068 I2C.byte_counter[2]
.sym 15069 I2C.byte_counter[3]
.sym 15070 I2C.byte_counter[0]
.sym 15071 I2C.byte_counter[1]
.sym 15073 $abc$92916$n683
.sym 15074 $abc$92916$n749_1
.sym 15075 $abc$92916$n734
.sym 15076 I2C.is_read
.sym 15078 I2C.received_byte[1]
.sym 15079 $false
.sym 15080 $false
.sym 15081 $false
.sym 15082 $auto$dff2dffe.cc:175:make_patterns_logic$78149
.sym 15083 CLK$2$2
.sym 15084 $false
.sym 15085 $abc$92916$n718
.sym 15086 $abc$92916$n720_1
.sym 15087 $2\ring_rd[3:0][1]
.sym 15088 $abc$92916$n719
.sym 15089 ring_rd[0]
.sym 15090 ring_rd[1]
.sym 15091 ring_rd[2]
.sym 15092 ring_rd[3]
.sym 15159 I2C.wr
.sym 15160 last_wr
.sym 15161 $false
.sym 15162 $false
.sym 15164 $auto$alumacc.cc:470:replace_alu$57551.B_buf[2]
.sym 15165 $false
.sym 15166 $false
.sym 15167 $false
.sym 15169 $abc$92916$n729
.sym 15170 $abc$92916$n730
.sym 15171 I2C.byte_counter[0]
.sym 15172 I2C.byte_counter[1]
.sym 15174 $abc$92916$n687
.sym 15175 $abc$92916$n688
.sym 15176 $false
.sym 15177 $false
.sym 15179 $abc$92916$n1086_1
.sym 15180 $abc$92916$n1067_1
.sym 15181 $2\uart_double_ff[0:0]
.sym 15182 $abc$92916$n688
.sym 15184 $abc$92916$n1079
.sym 15185 $abc$92916$n809
.sym 15186 $2\uart_double_ff[0:0]
.sym 15187 $abc$92916$n688
.sym 15189 $abc$92916$n1084
.sym 15190 $abc$92916$n794
.sym 15191 $2\uart_double_ff[0:0]
.sym 15192 $abc$92916$n688
.sym 15194 $abc$92916$n1075
.sym 15195 $abc$92916$n808
.sym 15196 $2\uart_double_ff[0:0]
.sym 15197 $abc$92916$n688
.sym 15198 $auto$dff2dffe.cc:175:make_patterns_logic$79939
.sym 15199 CLK$2$2
.sym 15200 $false
.sym 15201 $add$top.v:177$101_Y[0]
.sym 15202 $2\ring_rd[3:0][2]
.sym 15204 $2\ring_rd[3:0][3]
.sym 15205 $2\ring_rd[3:0][0]
.sym 15206 $auto$wreduce.cc:310:run$57522[5]
.sym 15207 $add$top.v:177$101_Y[3]
.sym 15208 KEYBOARD.row_counter[2]
.sym 15237 $true
.sym 15274 $auto$alumacc.cc:483:replace_alu$57552[0]$2
.sym 15275 $false
.sym 15276 $auto$alumacc.cc:483:replace_alu$57552[0]
.sym 15277 $false
.sym 15278 $false
.sym 15279 $auto$alumacc.cc:484:replace_alu$57553[1]
.sym 15281 $false
.sym 15282 $auto$alumacc.cc:483:replace_alu$57552[1]
.sym 15284 $auto$alumacc.cc:484:replace_alu$57553[2]
.sym 15286 $false
.sym 15287 $auto$alumacc.cc:483:replace_alu$57552[2]
.sym 15289 $auto$alumacc.cc:484:replace_alu$57553[3]$2
.sym 15291 $false
.sym 15292 $auto$alumacc.cc:483:replace_alu$57552[3]
.sym 15298 $auto$alumacc.cc:484:replace_alu$57553[3]$2
.sym 15305 I2C.received_byte[2]
.sym 15306 $false
.sym 15307 $false
.sym 15308 $false
.sym 15310 I2C.received_byte[0]
.sym 15311 $false
.sym 15312 $false
.sym 15313 $false
.sym 15314 $auto$dff2dffe.cc:175:make_patterns_logic$78149
.sym 15315 CLK$2$2
.sym 15316 $false
.sym 15317 $abc$92916$n1186
.sym 15318 $abc$92916$n1134
.sym 15319 $abc$92916$n1184
.sym 15320 $abc$92916$n1179
.sym 15321 $abc$92916$n1133
.sym 15322 $abc$92916$n740
.sym 15323 UART_TX_DATA[6]
.sym 15324 UART_TX_DATA[2]
.sym 15391 UART_TX_DATA[4]
.sym 15392 UART_TX_DATA[0]
.sym 15393 $techmap\UART.$sub$uart.v:40$540_Y[2]
.sym 15394 $false
.sym 15396 I2C.byte_counter[2]
.sym 15397 I2C.byte_counter[3]
.sym 15398 $false
.sym 15399 $false
.sym 15401 $abc$92916$n1132_1
.sym 15402 I2C.byte_counter[4]
.sym 15403 I2C.byte_counter[6]
.sym 15404 I2C.byte_counter[7]
.sym 15406 $abc$92916$n729
.sym 15407 I2C.byte_counter[0]
.sym 15408 I2C.byte_counter[1]
.sym 15409 I2C.byte_counter[5]
.sym 15411 UART_TX_DATA[5]
.sym 15412 UART_TX_DATA[1]
.sym 15413 $techmap\UART.$sub$uart.v:40$540_Y[2]
.sym 15414 $false
.sym 15416 I2C.received_byte[4]
.sym 15417 $abc$92916$n1105
.sym 15418 I2C.is_read
.sym 15419 $false
.sym 15421 I2C.received_byte[5]
.sym 15422 $abc$92916$n1107
.sym 15423 I2C.is_read
.sym 15424 $false
.sym 15426 I2C.received_byte[1]
.sym 15427 $abc$92916$n1099
.sym 15428 I2C.is_read
.sym 15429 $false
.sym 15430 $auto$dff2dffe.cc:175:make_patterns_logic$71223
.sym 15431 CLK$2$2
.sym 15432 $auto$rtlil.cc:1692:NotGate$92623
.sym 15433 $techmap\I2C.$procmux$19804_Y
.sym 15435 $abc$92916$n831_1
.sym 15436 $abc$92916$n735
.sym 15437 $abc$92916$n1183
.sym 15438 $auto$alumacc.cc:483:replace_alu$57684[1]
.sym 15439 UART_TX_DATA[7]
.sym 15440 UART_TX_DATA[3]
.sym 15507 $abc$92916$n1111
.sym 15508 $abc$92916$n1103
.sym 15509 $abc$92916$n831_1
.sym 15510 $techmap\I2C.$sub$i2c_slave.v:143$226_Y[2]
.sym 15512 $abc$92916$n1130
.sym 15513 $abc$92916$n1133
.sym 15514 $false
.sym 15515 $false
.sym 15517 I2C.FLT_SCL.out
.sym 15518 I2C.FLT_SDA.out
.sym 15519 I2C.SDA_LAST
.sym 15520 I2C.i2c_state_machine
.sym 15522 $abc$92916$n1131
.sym 15523 $techmap\I2C.$procmux$19804_Y
.sym 15524 $false
.sym 15525 $false
.sym 15527 I2C.FLT_SCL.out
.sym 15528 I2C.FLT_SDA.out
.sym 15529 I2C.SDA_LAST
.sym 15530 I2C.SDA_DIR
.sym 15532 $abc$92916$n1130
.sym 15533 $abc$92916$n1135
.sym 15534 $abc$92916$n823
.sym 15535 $auto$alumacc.cc:484:replace_alu$57574[3]
.sym 15537 $abc$92916$n1119
.sym 15538 I2C.i2c_state_machine
.sym 15539 $abc$92916$n1168
.sym 15540 $false
.sym 15542 $abc$92916$n820
.sym 15543 $abc$92916$n1164_1
.sym 15544 I2C.received_byte[0]
.sym 15545 $false
.sym 15546 $true
.sym 15547 CLK$2$2
.sym 15548 $false
.sym 15549 $abc$92916$n822
.sym 15550 $auto$alumacc.cc:470:replace_alu$57683.C[1]
.sym 15551 $abc$92916$n825
.sym 15552 $abc$92916$n819
.sym 15553 $auto$wreduce.cc:310:run$57516[0]
.sym 15554 I2C.byte_counter[0]
.sym 15555 I2C.byte_counter[1]
.sym 15556 I2C.SDA_LAST
.sym 15623 I2C.FLT_SCL.out
.sym 15624 I2C.FLT_SDA.out
.sym 15625 I2C.SDA_LAST
.sym 15626 I2C.wr
.sym 15628 $abc$92916$n1135
.sym 15629 $abc$92916$n1117
.sym 15630 $abc$92916$n820
.sym 15631 $auto$alumacc.cc:484:replace_alu$57574[3]
.sym 15633 $auto$alumacc.cc:484:replace_alu$57680[7]
.sym 15634 $abc$92916$n820
.sym 15635 $auto$alumacc.cc:484:replace_alu$57574[3]
.sym 15636 $abc$92916$n823
.sym 15638 $abc$92916$n1117
.sym 15639 $abc$92916$n1119
.sym 15640 $auto$alumacc.cc:484:replace_alu$57574[3]
.sym 15641 I2C.FLT_SDA.out
.sym 15643 $techmap\I2C.$procmux$19804_Y
.sym 15644 I2C.i2c_bit_counter[0]
.sym 15645 $false
.sym 15646 $false
.sym 15648 $abc$92916$n1155
.sym 15649 $auto$simplemap.cc:250:simplemap_eqne$60443[0]
.sym 15650 $auto$alumacc.cc:484:replace_alu$57574[3]
.sym 15651 $false
.sym 15653 $abc$92916$n1154
.sym 15654 $abc$92916$n1151
.sym 15655 $auto$alumacc.cc:483:replace_alu$57687[0]
.sym 15656 $abc$92916$n823
.sym 15658 $abc$92916$n1125
.sym 15659 $abc$92916$n1124
.sym 15660 $abc$92916$n1117
.sym 15661 $abc$92916$n1115
.sym 15662 $true
.sym 15663 CLK$2$2
.sym 15664 $false
.sym 15665 $abc$92916$n1162
.sym 15666 $abc$92916$n1155
.sym 15667 $abc$92916$n824
.sym 15668 $auto$alumacc.cc:483:replace_alu$57573[3]
.sym 15669 $abc$92916$n1118
.sym 15670 $auto$simplemap.cc:250:simplemap_eqne$60443[4]
.sym 15671 I2C.i2c_bit_counter[3]
.sym 15672 I2C.is_ack
.sym 15739 $abc$92916$n820
.sym 15740 $abc$92916$n1137
.sym 15741 $abc$92916$n1128
.sym 15742 $abc$92916$n1136
.sym 15744 $abc$92916$n1122
.sym 15745 $abc$92916$n1118
.sym 15746 $abc$92916$n1120
.sym 15747 $false
.sym 15749 $abc$92916$n1129
.sym 15750 $abc$92916$n1135
.sym 15751 $auto$alumacc.cc:484:replace_alu$57574[3]
.sym 15752 $false
.sym 15754 $abc$92916$n1120
.sym 15755 $abc$92916$n1116
.sym 15756 $abc$92916$n1123
.sym 15757 $abc$92916$n823
.sym 15759 $abc$92916$n1129
.sym 15760 $abc$92916$n1135
.sym 15761 $auto$alumacc.cc:484:replace_alu$57574[3]
.sym 15762 $false
.sym 15764 $auto$alumacc.cc:484:replace_alu$57574[3]
.sym 15765 $abc$92916$n1122
.sym 15766 $abc$92916$n1118
.sym 15767 $false
.sym 15769 $abc$92916$n1118
.sym 15770 $abc$92916$n1122
.sym 15771 $auto$alumacc.cc:484:replace_alu$57574[3]
.sym 15772 $abc$92916$n820
.sym 15774 $abc$92916$n1116
.sym 15775 $abc$92916$n1166
.sym 15776 $abc$92916$n820
.sym 15777 $abc$92916$n823
.sym 15778 $true
.sym 15779 CLK$2$2
.sym 15780 $logic_not$top.v:66$10_Y$2
.sym 15825 RESET
.sym 15881 $abc$92916$n850
.sym 15883 $abc$92916$n637
.sym 15884 $abc$92916$n645
.sym 15885 $abc$92916$n849
.sym 15886 $abc$92916$n635
.sym 15887 $abc$92916$n620
.sym 15888 $abc$92916$n848
.sym 15956 $techmap\I2C.FLT_SCL.$procmux$1018_Y[0]
.sym 15957 $abc$92916$n934
.sym 15958 $false
.sym 15959 $false
.sym 15961 $abc$92916$n653
.sym 15962 KEYBOARD.is_pressed
.sym 15963 KEYBOARD.COLS_SHADOW[3]
.sym 15964 $abc$92916$n647
.sym 15966 I2C.FLT_SCL.counter[0]
.sym 15967 I2C.FLT_SCL.counter[1]
.sym 15968 $false
.sym 15969 $false
.sym 15971 $abc$92916$n644
.sym 15972 $abc$92916$n638
.sym 15973 $abc$92916$n613
.sym 15974 $abc$92916$n650
.sym 15976 $techmap\I2C.FLT_SCL.$procmux$1018_Y[1]
.sym 15977 $auto$wreduce.cc:310:run$57520[2]
.sym 15978 I2C.FLT_SCL.out
.sym 15979 I2C.SCLF
.sym 15981 $abc$92916$n651
.sym 15982 $abc$92916$n652
.sym 15983 $false
.sym 15984 $false
.sym 15986 $abc$92916$n645
.sym 15987 $abc$92916$n647
.sym 15988 $false
.sym 15989 $false
.sym 15991 I2C.SCLF
.sym 15992 $false
.sym 15993 $false
.sym 15994 $false
.sym 15995 $auto$dff2dffe.cc:175:make_patterns_logic$92275
.sym 15996 CLK$2$2
.sym 15997 $logic_not$top.v:66$10_Y$2
.sym 15998 KBD_COLUMNS[6]$2
.sym 16000 KBD_COLUMNS[7]$2
.sym 16002 $abc$92916$n1223_1
.sym 16003 $abc$92916$n1230
.sym 16004 $abc$92916$n1234_1
.sym 16005 $abc$92916$n1242
.sym 16006 $abc$92916$n1235_1
.sym 16007 $auto$wreduce.cc:310:run$57523[0]
.sym 16008 KEYBOARD.ROWS_EN[8]
.sym 16009 KEYBOARD.ROWS_EN[14]
.sym 16074 $true
.sym 16111 I2C.FLT_SCL.counter[0]$2
.sym 16112 $false
.sym 16113 I2C.FLT_SCL.counter[0]
.sym 16114 $false
.sym 16115 $false
.sym 16116 $auto$alumacc.cc:484:replace_alu$57691[1]$2
.sym 16118 I2C.FLT_SCL.counter[1]
.sym 16119 $true$2
.sym 16125 $auto$alumacc.cc:484:replace_alu$57691[1]$2
.sym 16127 $abc$92916$n656
.sym 16128 KEYBOARD.is_pressed
.sym 16129 KEYBOARD.COLS_SHADOW[1]
.sym 16130 $abc$92916$n651
.sym 16132 $abc$92916$n660
.sym 16133 $abc$92916$n662
.sym 16134 $false
.sym 16135 $false
.sym 16137 $abc$92916$n655
.sym 16138 $abc$92916$n657
.sym 16139 $false
.sym 16140 $false
.sym 16142 $abc$92916$n659
.sym 16143 $abc$92916$n654
.sym 16144 $abc$92916$n612
.sym 16145 $abc$92916$n664
.sym 16147 $abc$92916$n665
.sym 16148 KEYBOARD.is_pressed
.sym 16149 KEYBOARD.COLS_SHADOW[0]
.sym 16150 $abc$92916$n662
.sym 16154 $abc$92916$n1239
.sym 16155 $abc$92916$n1236
.sym 16156 $techmap\KEYBOARD.$procmux$8869_Y[7]
.sym 16157 $techmap\KEYBOARD.$procmux$8869_Y[2]
.sym 16158 $abc$92916$n1244_1
.sym 16159 $abc$92916$n1248
.sym 16160 $abc$92916$n636
.sym 16161 I2C.FLT_SDA.out
.sym 16228 KEYBOARD.RAM.r_data[7]
.sym 16229 KEYBOARD.temp[7]
.sym 16230 $abc$92916$n628
.sym 16231 KEYBOARD.COLS_SHADOW[7]
.sym 16233 $abc$92916$n661
.sym 16234 KEYBOARD.is_pressed
.sym 16235 KEYBOARD.COLS_SHADOW[2]
.sym 16236 $abc$92916$n657
.sym 16238 KEYBOARD.temp[7]
.sym 16239 KEYBOARD.RAM.r_data[7]
.sym 16240 $abc$92916$n628
.sym 16241 $false
.sym 16243 KEYBOARD.COLS_SHADOW[3]
.sym 16244 $abc$92916$n653
.sym 16245 $abc$92916$n647
.sym 16246 $false
.sym 16248 KEYBOARD.COLS_SHADOW[2]
.sym 16249 $abc$92916$n661
.sym 16250 $abc$92916$n657
.sym 16251 $false
.sym 16253 $abc$92916$n662
.sym 16254 $abc$92916$n1234_1
.sym 16255 $abc$92916$n1239
.sym 16256 $abc$92916$n1236
.sym 16258 KEYBOARD.COLS_SHADOW[0]
.sym 16259 $abc$92916$n665
.sym 16260 $abc$92916$n662
.sym 16261 $false
.sym 16263 KEYBOARD.COLS_SHADOW[7]
.sym 16264 $abc$92916$n1221
.sym 16265 $abc$92916$n621
.sym 16266 $false
.sym 16267 RESET$2
.sym 16268 CLK$2$2
.sym 16269 $false
.sym 16270 $abc$92916$n639
.sym 16271 $abc$92916$n1227
.sym 16272 $auto$wreduce.cc:310:run$57526[0]
.sym 16273 $abc$92916$n1226_1
.sym 16274 $abc$92916$n1240_1
.sym 16275 $abc$92916$n1237_1
.sym 16276 $auto$wreduce.cc:310:run$57522[0]
.sym 16277 KEYBOARD.report[4][7]
.sym 16344 KEYBOARD.kbd_code_hid[3]
.sym 16345 KEYBOARD.kbd_code_hid[2]
.sym 16346 KEYBOARD.report[1][2]
.sym 16347 KEYBOARD.report[1][3]
.sym 16349 KEYBOARD.kbd_code_hid[4]
.sym 16350 KEYBOARD.kbd_code_hid[5]
.sym 16351 KEYBOARD.report[1][4]
.sym 16352 KEYBOARD.report[1][5]
.sym 16354 $abc$92916$n639
.sym 16355 $abc$92916$n614
.sym 16356 $abc$92916$n641
.sym 16357 $false
.sym 16359 $abc$92916$n916
.sym 16360 $abc$92916$n917
.sym 16361 $abc$92916$n918
.sym 16362 $false
.sym 16364 KEYBOARD.kbd_code_hid[1]
.sym 16365 KEYBOARD.kbd_code_hid[0]
.sym 16366 KEYBOARD.report[1][0]
.sym 16367 KEYBOARD.report[1][1]
.sym 16369 $auto$rtlil.cc:1692:NotGate$92753
.sym 16370 KEYBOARD.kbd_code_hid[0]
.sym 16371 $false
.sym 16372 $false
.sym 16374 $abc$92916$n1008
.sym 16375 KEYBOARD.report[4][1]
.sym 16376 $abc$92916$n1005
.sym 16377 KEYBOARD.report[1][1]
.sym 16379 $techmap\KEYBOARD.$procmux$5651_Y[7]
.sym 16380 $false
.sym 16381 $false
.sym 16382 $false
.sym 16383 $auto$dff2dffe.cc:175:make_patterns_logic$89305
.sym 16384 CLK$2$2
.sym 16385 $logic_not$top.v:66$10_Y$2
.sym 16386 $auto$wreduce.cc:310:run$57521[0]
.sym 16387 $auto$dff2dffe.cc:175:make_patterns_logic$90769
.sym 16388 $abc$92916$n913
.sym 16389 KEYBOARD.is_pressed
.sym 16390 KEYBOARD.temp[1]
.sym 16391 KEYBOARD.temp[6]
.sym 16392 KEYBOARD.kbd_code[0]
.sym 16393 KEYBOARD.temp[4]
.sym 16460 $abc$92916$n1008
.sym 16461 KEYBOARD.report[4][5]
.sym 16462 $false
.sym 16463 $false
.sym 16465 $abc$92916$n1007
.sym 16466 KEYBOARD.report[2][7]
.sym 16467 $abc$92916$n1005
.sym 16468 KEYBOARD.report[1][7]
.sym 16470 KEYBOARD.temp[3]
.sym 16471 KEYBOARD.RAM.r_data[3]
.sym 16472 $abc$92916$n628
.sym 16473 $false
.sym 16475 $abc$92916$n1007
.sym 16476 KEYBOARD.report[2][5]
.sym 16477 $abc$92916$n1005
.sym 16478 KEYBOARD.report[1][5]
.sym 16480 $abc$92916$n1007
.sym 16481 KEYBOARD.report[2][6]
.sym 16482 $abc$92916$n1005
.sym 16483 KEYBOARD.report[1][6]
.sym 16485 KEYBOARD.kbd_code_hid[7]
.sym 16486 KEYBOARD.kbd_code_hid[6]
.sym 16487 KEYBOARD.report[1][6]
.sym 16488 KEYBOARD.report[1][7]
.sym 16490 $abc$92916$n919
.sym 16491 $abc$92916$n915
.sym 16492 $auto$rtlil.cc:1692:NotGate$92753
.sym 16493 $abc$92916$n846
.sym 16495 $techmap\KEYBOARD.$procmux$5651_Y[1]
.sym 16496 $false
.sym 16497 $false
.sym 16498 $false
.sym 16499 $auto$dff2dffe.cc:175:make_patterns_logic$87074
.sym 16500 CLK$2$2
.sym 16501 $logic_not$top.v:66$10_Y$2
.sym 16502 $abc$92916$n877
.sym 16503 $abc$92916$n896
.sym 16504 $abc$92916$n661
.sym 16505 $abc$92916$n665
.sym 16506 $sub$top.v:122$51_Y[0]
.sym 16507 $auto$dff2dffe.cc:175:make_patterns_logic$89305
.sym 16508 $auto$dff2dffe.cc:175:make_patterns_logic$87074
.sym 16509 KEYBOARD.ram_adr[5]
.sym 16576 KEYBOARD.kbd_code_hid[7]
.sym 16577 KEYBOARD.kbd_code_hid[6]
.sym 16578 KEYBOARD.report[3][6]
.sym 16579 KEYBOARD.report[3][7]
.sym 16581 KEYBOARD.kbd_code_hid[1]
.sym 16582 KEYBOARD.kbd_code_hid[0]
.sym 16583 KEYBOARD.report[3][0]
.sym 16584 KEYBOARD.report[3][1]
.sym 16586 $abc$92916$n902
.sym 16587 $abc$92916$n898
.sym 16588 $auto$rtlil.cc:1692:NotGate$92753
.sym 16589 $abc$92916$n846
.sym 16591 $abc$92916$n899
.sym 16592 $abc$92916$n900
.sym 16593 $abc$92916$n901
.sym 16594 $false
.sym 16596 KEYBOARD.report[3][4]
.sym 16597 KEYBOARD.report[3][5]
.sym 16598 KEYBOARD.report[3][6]
.sym 16599 KEYBOARD.report[3][7]
.sym 16601 KEYBOARD.kbd_code_hid[4]
.sym 16602 KEYBOARD.kbd_code_hid[5]
.sym 16603 KEYBOARD.report[3][4]
.sym 16604 KEYBOARD.report[3][5]
.sym 16606 KEYBOARD.report[0][5]
.sym 16607 $auto$rtlil.cc:1692:NotGate$92753
.sym 16608 $abc$92916$n1203
.sym 16609 $false
.sym 16611 KEYBOARD.report[0][3]
.sym 16612 $auto$rtlil.cc:1692:NotGate$92753
.sym 16613 $abc$92916$n1199
.sym 16614 $false
.sym 16615 $auto$dff2dffe.cc:175:make_patterns_logic$91231
.sym 16616 CLK$2$2
.sym 16617 $logic_not$top.v:66$10_Y$2
.sym 16618 $auto$dff2dffe.cc:175:make_patterns_logic$90124
.sym 16619 $abc$92916$n894
.sym 16620 $abc$92916$n904
.sym 16621 $abc$92916$n905
.sym 16622 $abc$92916$n858
.sym 16623 $abc$92916$n869
.sym 16624 $abc$92916$n857
.sym 16625 KEYBOARD.ROWS_EN[13]
.sym 16692 $abc$92916$n1008
.sym 16693 KEYBOARD.report[4][6]
.sym 16694 $false
.sym 16695 $false
.sym 16697 $abc$92916$n911
.sym 16698 $abc$92916$n907
.sym 16699 $auto$rtlil.cc:1692:NotGate$92753
.sym 16700 $abc$92916$n846
.sym 16702 $auto$rtlil.cc:1692:NotGate$92753
.sym 16703 KEYBOARD.kbd_code_hid[1]
.sym 16704 $false
.sym 16705 $false
.sym 16707 $abc$92916$n1008
.sym 16708 KEYBOARD.report[4][3]
.sym 16709 $abc$92916$n1007
.sym 16710 KEYBOARD.report[2][3]
.sym 16712 KEYBOARD.kbd_code_hid[7]
.sym 16713 KEYBOARD.kbd_code_hid[6]
.sym 16714 KEYBOARD.report[2][6]
.sym 16715 KEYBOARD.report[2][7]
.sym 16717 KEYBOARD.report[2][4]
.sym 16718 KEYBOARD.report[2][5]
.sym 16719 KEYBOARD.report[2][6]
.sym 16720 KEYBOARD.report[2][7]
.sym 16722 $techmap\KEYBOARD.$procmux$5651_Y[7]
.sym 16723 $false
.sym 16724 $false
.sym 16725 $false
.sym 16727 $techmap\KEYBOARD.$procmux$5651_Y[3]
.sym 16728 $false
.sym 16729 $false
.sym 16730 $false
.sym 16731 $auto$dff2dffe.cc:175:make_patterns_logic$90124
.sym 16732 CLK$2$2
.sym 16733 $logic_not$top.v:66$10_Y$2
.sym 16734 $auto$simplemap.cc:309:simplemap_lut$69160[0]
.sym 16736 $techmap$techmap\KEYBOARD.$shl$matrix_kbd.v:51$296.$procmux$66087_Y[13]
.sym 16737 $techmap\KEYBOARD.$procmux$5651_Y[3]
.sym 16738 KEYBOARD.ram_adr[7]
.sym 16739 KEYBOARD.ram_adr[0]
.sym 16808 I2C.byte_counter[2]
.sym 16809 I2C.byte_counter[3]
.sym 16810 $false
.sym 16811 $false
.sym 16813 $false
.sym 16814 UART.tx_bit_counter[0]
.sym 16815 $false
.sym 16816 $true$2
.sym 16818 $abc$92916$n730
.sym 16819 $abc$92916$n751
.sym 16820 I2C.byte_counter[0]
.sym 16821 I2C.byte_counter[1]
.sym 16828 $abc$92916$n730
.sym 16829 $abc$92916$n751
.sym 16830 I2C.byte_counter[0]
.sym 16831 I2C.byte_counter[1]
.sym 16833 $abc$92916$n730
.sym 16834 $abc$92916$n751
.sym 16835 I2C.byte_counter[0]
.sym 16836 I2C.byte_counter[1]
.sym 16843 $auto$simplemap.cc:309:simplemap_lut$69070[7]
.sym 16844 $false
.sym 16845 $false
.sym 16846 $false
.sym 16847 $auto$dff2dffe.cc:175:make_patterns_logic$85121
.sym 16848 CLK$2$2
.sym 16849 $eq$top.v:243$154_Y
.sym 16850 $abc$92916$n769_1
.sym 16851 $abc$92916$n768
.sym 16852 $abc$92916$n1081
.sym 16853 $abc$92916$n1082
.sym 16854 $abc$92916$n778
.sym 16855 $abc$92916$n771
.sym 16856 $2\ring_wr[3:0][1]
.sym 16857 $abc$92916$n1077_1
.sym 16924 $abc$92916$n776
.sym 16925 $abc$92916$n750
.sym 16926 $abc$92916$n780
.sym 16927 $false
.sym 16929 $abc$92916$n775
.sym 16930 $abc$92916$n733
.sym 16931 $abc$92916$n781
.sym 16932 $false
.sym 16934 $abc$92916$n755
.sym 16935 $abc$92916$n769_1
.sym 16936 $abc$92916$n782
.sym 16937 $abc$92916$n759
.sym 16939 $abc$92916$n755
.sym 16940 $abc$92916$n769_1
.sym 16941 I2C.received_byte[3]
.sym 16942 I2C.received_byte[2]
.sym 16944 $abc$92916$n750
.sym 16945 $abc$92916$n752
.sym 16946 $false
.sym 16947 $false
.sym 16949 $abc$92916$n755
.sym 16950 i2c_input_data_type[0]
.sym 16951 I2C.received_byte[0]
.sym 16952 I2C.received_byte[1]
.sym 16954 $abc$92916$n773_1
.sym 16955 $abc$92916$n777
.sym 16956 $abc$92916$n779
.sym 16957 $false
.sym 16959 $2\ring_wr[3:0][3]
.sym 16960 $false
.sym 16961 $false
.sym 16962 $false
.sym 16963 $auto$dff2dffe.cc:175:make_patterns_logic$73370
.sym 16964 CLK$2$2
.sym 16965 $logic_not$top.v:66$10_Y$2
.sym 16966 $abc$92916$n1080
.sym 16967 $2\ring_wr[3:0][0]
.sym 16968 $abc$92916$n1084
.sym 16969 $abc$92916$n1079
.sym 16970 $2\ring_wr[3:0][2]
.sym 16971 $auto$dff2dffe.cc:175:make_patterns_logic$84986
.sym 16972 $2\ring_wr[3:0][3]
.sym 16973 I2C.received_byte[6]
.sym 17040 $abc$92916$n734
.sym 17041 I2C.byte_counter[2]
.sym 17042 $false
.sym 17043 $false
.sym 17045 $auto$simplemap.cc:309:simplemap_lut$69070[7]
.sym 17046 $false
.sym 17047 $false
.sym 17048 $false
.sym 17055 $auto$alumacc.cc:483:replace_alu$57552[1]
.sym 17056 $auto$simplemap.cc:309:simplemap_lut$69070[7]
.sym 17057 $false
.sym 17058 $false
.sym 17060 $false
.sym 17061 $false
.sym 17062 $auto$alumacc.cc:483:replace_alu$57552[0]
.sym 17063 $true$2
.sym 17065 I2C.byte_counter[4]
.sym 17066 I2C.byte_counter[5]
.sym 17067 I2C.byte_counter[6]
.sym 17068 I2C.byte_counter[7]
.sym 17070 $abc$92916$n730
.sym 17071 $abc$92916$n735
.sym 17072 I2C.byte_counter[3]
.sym 17073 $false
.sym 17075 $abc$92916$n1184
.sym 17076 $abc$92916$n1179
.sym 17077 $auto$alumacc.cc:484:replace_alu$57553[3]
.sym 17078 $techmap\UART.$sub$uart.v:40$540_Y[0]
.sym 17079 $auto$dff2dffe.cc:175:make_patterns_logic$85121
.sym 17080 CLK$2$2
.sym 17081 $eq$top.v:243$154_Y
.sym 17084 $add$top.v:98$31_Y[2]
.sym 17085 $add$top.v:98$31_Y[3]
.sym 17086 $auto$alumacc.cc:484:replace_alu$57668[3]
.sym 17087 $abc$92916$n971_1
.sym 17088 $abc$92916$n969
.sym 17089 $abc$92916$n970
.sym 17156 $abc$92916$n719
.sym 17157 $abc$92916$n720_1
.sym 17158 $false
.sym 17159 $false
.sym 17161 ring_wr[0]
.sym 17162 ring_wr[2]
.sym 17163 ring_rd[0]
.sym 17164 ring_rd[2]
.sym 17166 $abc$92916$n718
.sym 17167 ring_rd[0]
.sym 17168 ring_rd[1]
.sym 17169 $false
.sym 17171 ring_wr[1]
.sym 17172 ring_wr[3]
.sym 17173 ring_rd[1]
.sym 17174 ring_rd[3]
.sym 17176 $2\ring_rd[3:0][0]
.sym 17177 $false
.sym 17178 $false
.sym 17179 $false
.sym 17181 $2\ring_rd[3:0][1]
.sym 17182 $false
.sym 17183 $false
.sym 17184 $false
.sym 17186 $2\ring_rd[3:0][2]
.sym 17187 $false
.sym 17188 $false
.sym 17189 $false
.sym 17191 $2\ring_rd[3:0][3]
.sym 17192 $false
.sym 17193 $false
.sym 17194 $false
.sym 17195 $auto$dff2dffe.cc:175:make_patterns_logic$73607
.sym 17196 CLK$2$2
.sym 17197 $logic_not$top.v:66$10_Y$2
.sym 17200 $add$top.v:177$101_Y[2]
.sym 17201 $auto$alumacc.cc:484:replace_alu$57653[2]
.sym 17202 $auto$alumacc.cc:483:replace_alu$57618[5]
.sym 17203 $auto$alumacc.cc:483:replace_alu$57618[7]
.sym 17204 $auto$dff2dffe.cc:175:make_patterns_logic$84852
.sym 17205 I2C.received_byte[4]
.sym 17272 $false
.sym 17273 $true$2
.sym 17274 ring_rd[0]
.sym 17275 $false
.sym 17277 $add$top.v:177$101_Y[2]
.sym 17278 ring_rd[2]
.sym 17279 $abc$92916$n718
.sym 17280 $false
.sym 17287 $add$top.v:177$101_Y[3]
.sym 17288 ring_rd[3]
.sym 17289 $abc$92916$n718
.sym 17290 $false
.sym 17292 $add$top.v:177$101_Y[0]
.sym 17293 ring_rd[0]
.sym 17294 $abc$92916$n718
.sym 17295 $false
.sym 17297 KEYBOARD.row_counter[2]
.sym 17298 $auto$wreduce.cc:310:run$57529[2]
.sym 17299 $auto$rtlil.cc:1692:NotGate$92893$2
.sym 17300 $false
.sym 17302 $false
.sym 17303 $false
.sym 17304 ring_rd[3]
.sym 17305 $auto$alumacc.cc:484:replace_alu$57653[2]
.sym 17307 $auto$wreduce.cc:310:run$57522[5]
.sym 17308 $false
.sym 17309 $false
.sym 17310 $false
.sym 17311 RESET$2
.sym 17312 CLK$2$2
.sym 17313 $false
.sym 17314 $add$top.v:123$53_Y[3]
.sym 17315 $add$top.v:123$53_Y[0]
.sym 17316 wr_cnt[1]
.sym 17317 wr_cnt[3]
.sym 17319 wr_cnt[2]
.sym 17320 wr_cnt[0]
.sym 17388 UART_TX_DATA[6]
.sym 17389 UART_TX_DATA[2]
.sym 17390 $techmap\UART.$sub$uart.v:40$540_Y[2]
.sym 17391 $false
.sym 17393 I2C.received_byte[3]
.sym 17394 I2C.received_byte[4]
.sym 17395 I2C.received_byte[5]
.sym 17396 I2C.received_byte[1]
.sym 17398 $abc$92916$n1186
.sym 17399 $abc$92916$n1185_1
.sym 17400 $abc$92916$n1180_1
.sym 17401 $false
.sym 17403 $abc$92916$n1183
.sym 17404 $abc$92916$n1182_1
.sym 17405 $abc$92916$n1180_1
.sym 17406 $false
.sym 17408 $abc$92916$n1134
.sym 17409 I2C.received_byte[2]
.sym 17410 I2C.received_byte[7]
.sym 17411 I2C.received_byte[6]
.sym 17413 wr_cnt[0]
.sym 17414 wr_cnt[1]
.sym 17415 wr_cnt[2]
.sym 17416 wr_cnt[3]
.sym 17418 I2C.received_byte[6]
.sym 17419 $abc$92916$n1109
.sym 17420 I2C.is_read
.sym 17421 $false
.sym 17423 I2C.received_byte[2]
.sym 17424 $abc$92916$n1101
.sym 17425 I2C.is_read
.sym 17426 $false
.sym 17427 $auto$dff2dffe.cc:175:make_patterns_logic$71223
.sym 17428 CLK$2$2
.sym 17429 $auto$rtlil.cc:1692:NotGate$92623
.sym 17430 $abc$92916$n1142
.sym 17431 $abc$92916$n1141
.sym 17432 $auto$dff2dffe.cc:175:make_patterns_logic$85053
.sym 17433 $abc$92916$n833
.sym 17434 $auto$dff2dffe.cc:175:make_patterns_logic$84785
.sym 17436 $techmap$auto$alumacc.cc:470:replace_alu$57683.$not$/usr/bin/../share/yosys/ice40/arith_map.v:42$58930_Y[1]
.sym 17437 I2C.received_byte[7]
.sym 17504 I2C.FLT_SCL.out
.sym 17505 I2C.FLT_SDA.out
.sym 17506 I2C.SDA_LAST
.sym 17507 $false
.sym 17514 $abc$92916$n825
.sym 17515 $auto$simplemap.cc:250:simplemap_eqne$60443[0]
.sym 17516 $false
.sym 17517 $false
.sym 17519 I2C.byte_counter[0]
.sym 17520 I2C.byte_counter[1]
.sym 17521 $false
.sym 17522 $false
.sym 17524 UART_TX_DATA[7]
.sym 17525 UART_TX_DATA[3]
.sym 17526 $techmap\UART.$sub$uart.v:40$540_Y[2]
.sym 17527 $false
.sym 17529 $techmap\I2C.$procmux$19804_Y
.sym 17530 I2C.byte_counter[1]
.sym 17531 $false
.sym 17532 $false
.sym 17534 I2C.received_byte[7]
.sym 17535 $abc$92916$n1111
.sym 17536 I2C.is_read
.sym 17537 $false
.sym 17539 I2C.received_byte[3]
.sym 17540 $abc$92916$n1103
.sym 17541 I2C.is_read
.sym 17542 $false
.sym 17543 $auto$dff2dffe.cc:175:make_patterns_logic$71223
.sym 17544 CLK$2$2
.sym 17545 $auto$rtlil.cc:1692:NotGate$92623
.sym 17546 $auto$alumacc.cc:483:replace_alu$57684[4]
.sym 17547 $auto$simplemap.cc:250:simplemap_eqne$60443[0]
.sym 17548 $auto$alumacc.cc:483:replace_alu$57684[3]
.sym 17549 $auto$wreduce.cc:310:run$57516[7]
.sym 17550 $auto$alumacc.cc:483:replace_alu$57684[2]
.sym 17552 $auto$alumacc.cc:483:replace_alu$57684[7]
.sym 17553 I2C.byte_counter[5]
.sym 17620 $abc$92916$n823
.sym 17621 $abc$92916$n824
.sym 17622 $auto$alumacc.cc:484:replace_alu$57574[3]
.sym 17623 $false
.sym 17625 $techmap\I2C.$procmux$19804_Y
.sym 17626 I2C.byte_counter[0]
.sym 17627 $false
.sym 17628 $false
.sym 17630 $auto$alumacc.cc:470:replace_alu$57572.B_buf[1]
.sym 17631 $auto$alumacc.cc:483:replace_alu$57687[0]
.sym 17632 $false
.sym 17633 $false
.sym 17635 $abc$92916$n820
.sym 17636 $abc$92916$n822
.sym 17637 I2C.SCL_LAST
.sym 17638 I2C.FLT_SCL.out
.sym 17640 $false
.sym 17641 $true$2
.sym 17642 $auto$alumacc.cc:470:replace_alu$57683.C[1]
.sym 17643 $false
.sym 17645 $auto$alumacc.cc:470:replace_alu$57683.C[1]
.sym 17646 $abc$92916$n1141
.sym 17647 $auto$wreduce.cc:310:run$57516[0]
.sym 17648 $abc$92916$n1139
.sym 17650 $abc$92916$n1139
.sym 17651 $abc$92916$n1141
.sym 17652 $auto$alumacc.cc:470:replace_alu$57683.C[1]
.sym 17653 $auto$alumacc.cc:483:replace_alu$57684[1]
.sym 17655 I2C.FLT_SDA.out
.sym 17656 $false
.sym 17657 $false
.sym 17658 $false
.sym 17659 $true
.sym 17660 CLK$2$2
.sym 17661 $false
.sym 17664 $techmap\I2C.$sub$i2c_slave.v:143$226_Y[2]
.sym 17665 $auto$simplemap.cc:250:simplemap_eqne$60443[3]
.sym 17666 $auto$simplemap.cc:309:simplemap_lut$68433[2]
.sym 17667 $auto$alumacc.cc:470:replace_alu$57572.B_buf[3]
.sym 17669 KEYBOARD.ROWS_EN[5]
.sym 17736 $abc$92916$n1155
.sym 17737 $abc$92916$n823
.sym 17738 $auto$simplemap.cc:250:simplemap_eqne$60443[3]
.sym 17739 $auto$alumacc.cc:484:replace_alu$57574[3]
.sym 17741 $abc$92916$n820
.sym 17742 I2C.SCL_LAST
.sym 17743 I2C.FLT_SCL.out
.sym 17744 $false
.sym 17746 $auto$simplemap.cc:250:simplemap_eqne$60443[3]
.sym 17747 $auto$simplemap.cc:250:simplemap_eqne$60443[4]
.sym 17748 $auto$simplemap.cc:309:simplemap_lut$68433[2]
.sym 17749 $false
.sym 17751 $techmap\I2C.$procmux$19804_Y
.sym 17752 I2C.i2c_bit_counter[3]
.sym 17753 $false
.sym 17754 $false
.sym 17756 $techmap\I2C.$procmux$19804_Y
.sym 17757 I2C.is_ack
.sym 17758 $false
.sym 17759 $false
.sym 17761 $false
.sym 17762 $false
.sym 17763 $true$2
.sym 17764 $auto$simplemap.cc:309:simplemap_lut$68433[2]
.sym 17766 $auto$alumacc.cc:483:replace_alu$57573[3]
.sym 17767 $abc$92916$n1157
.sym 17768 $abc$92916$n1162
.sym 17769 $false
.sym 17771 I2C.is_ack
.sym 17772 $abc$92916$n1127_1
.sym 17773 $abc$92916$n823
.sym 17774 $false
.sym 17775 $true
.sym 17776 CLK$2$2
.sym 17777 $false
.sym 17952 KEYBOARD.kbd_code_hid[7]
.sym 17953 KEYBOARD.kbd_code_hid[6]
.sym 17954 KEYBOARD.kbd_code_hid[4]
.sym 17955 KEYBOARD.kbd_code_hid[5]
.sym 17962 KEYBOARD.temp[6]
.sym 17963 KEYBOARD.RAM.r_data[6]
.sym 17964 $abc$92916$n628
.sym 17965 KEYBOARD.COLS_SHADOW[6]
.sym 17967 $abc$92916$n646
.sym 17968 KEYBOARD.is_pressed
.sym 17969 KEYBOARD.COLS_SHADOW[4]
.sym 17970 $abc$92916$n641
.sym 17972 KEYBOARD.kbd_code_hid[2]
.sym 17973 KEYBOARD.kbd_code_hid[1]
.sym 17974 KEYBOARD.kbd_code_hid[0]
.sym 17975 $false
.sym 17977 $abc$92916$n637
.sym 17978 $abc$92916$n631
.sym 17979 $abc$92916$n621
.sym 17980 $abc$92916$n636
.sym 17982 $abc$92916$n634
.sym 17983 $abc$92916$n627
.sym 17984 $abc$92916$n621
.sym 17985 $abc$92916$n631
.sym 17987 $auto$alumacc.cc:484:replace_alu$57563[7]
.sym 17988 $abc$92916$n850
.sym 17989 KEYBOARD.kbd_code_hid[3]
.sym 17990 $abc$92916$n849
.sym 18108 $abc$92916$n1234_1
.sym 18109 $abc$92916$n1224
.sym 18110 $abc$92916$n1235_1
.sym 18111 $abc$92916$n657
.sym 18113 $abc$92916$n1231
.sym 18114 $abc$92916$n647
.sym 18115 $false
.sym 18116 $false
.sym 18118 $abc$92916$n651
.sym 18119 $abc$92916$n656
.sym 18120 KEYBOARD.COLS_SHADOW[1]
.sym 18121 $false
.sym 18123 $abc$92916$n1243_1
.sym 18124 $abc$92916$n1234_1
.sym 18125 $abc$92916$n657
.sym 18126 $false
.sym 18128 $abc$92916$n651
.sym 18129 $auto$wreduce.cc:310:run$57523[0]
.sym 18130 $false
.sym 18131 $false
.sym 18133 $false
.sym 18134 $true$2
.sym 18135 $false
.sym 18136 $false
.sym 18138 $techmap$techmap\KEYBOARD.$shl$matrix_kbd.v:51$296.$procmux$66087_Y[8]
.sym 18139 $false
.sym 18140 $false
.sym 18141 $false
.sym 18143 $techmap$techmap\KEYBOARD.$shl$matrix_kbd.v:51$296.$procmux$66087_Y[14]
.sym 18144 $false
.sym 18145 $false
.sym 18146 $false
.sym 18147 $auto$dff2dffe.cc:175:make_patterns_logic$91425$2
.sym 18148 CLK$2$2
.sym 18149 $auto$rtlil.cc:1692:NotGate$92861
.sym 18224 $abc$92916$n1231
.sym 18225 $abc$92916$n1240_1
.sym 18226 $abc$92916$n651
.sym 18227 $false
.sym 18229 $abc$92916$n662
.sym 18230 $abc$92916$n665
.sym 18231 KEYBOARD.COLS_SHADOW[0]
.sym 18232 $false
.sym 18234 $abc$92916$n1248
.sym 18235 $abc$92916$n1247_1
.sym 18236 $abc$92916$n1240_1
.sym 18237 $techmap\KEYBOARD.$procmux$8869_Y[2]
.sym 18239 $abc$92916$n1236
.sym 18240 $abc$92916$n662
.sym 18241 $abc$92916$n1242
.sym 18242 $abc$92916$n1244_1
.sym 18244 $abc$92916$n657
.sym 18245 $abc$92916$n661
.sym 18246 KEYBOARD.COLS_SHADOW[2]
.sym 18247 $abc$92916$n1236
.sym 18249 $abc$92916$n1234_1
.sym 18250 $abc$92916$n1230
.sym 18251 $abc$92916$n1244_1
.sym 18252 $false
.sym 18254 KEYBOARD.temp[7]
.sym 18255 KEYBOARD.RAM.r_data[7]
.sym 18256 $abc$92916$n628
.sym 18257 KEYBOARD.COLS_SHADOW[7]
.sym 18259 I2C.SDAF
.sym 18260 $false
.sym 18261 $false
.sym 18262 $false
.sym 18263 $auto$dff2dffe.cc:175:make_patterns_logic$92215
.sym 18264 CLK$2$2
.sym 18265 $logic_not$top.v:66$10_Y$2
.sym 18340 $abc$92916$n640
.sym 18341 KEYBOARD.is_pressed
.sym 18342 KEYBOARD.COLS_SHADOW[5]
.sym 18343 $false
.sym 18345 $abc$92916$n614
.sym 18346 $abc$92916$n640
.sym 18347 $auto$wreduce.cc:310:run$57526[0]
.sym 18348 KEYBOARD.COLS_SHADOW[5]
.sym 18350 $false
.sym 18351 $true$2
.sym 18352 $false
.sym 18353 $false
.sym 18355 $abc$92916$n1218
.sym 18356 $abc$92916$n1219_1
.sym 18357 KEYBOARD.COLS_SHADOW[6]
.sym 18358 $abc$92916$n614
.sym 18360 $abc$92916$n614
.sym 18361 $abc$92916$n640
.sym 18362 KEYBOARD.COLS_SHADOW[5]
.sym 18363 $abc$92916$n641
.sym 18365 $abc$92916$n657
.sym 18366 $abc$92916$n661
.sym 18367 $auto$wreduce.cc:310:run$57522[0]
.sym 18368 KEYBOARD.COLS_SHADOW[2]
.sym 18370 $false
.sym 18371 $false
.sym 18372 $false
.sym 18373 $false
.sym 18375 $techmap\KEYBOARD.$procmux$5651_Y[7]
.sym 18376 $false
.sym 18377 $false
.sym 18378 $false
.sym 18379 $auto$dff2dffe.cc:175:make_patterns_logic$88296
.sym 18380 CLK$2$2
.sym 18381 $logic_not$top.v:66$10_Y$2
.sym 18382 KEYBOARD.RAM.r_data[0]
.sym 18384 KEYBOARD.RAM.r_data[1]
.sym 18386 KEYBOARD.RAM.r_data[2]
.sym 18388 KEYBOARD.RAM.r_data[3]
.sym 18456 $false
.sym 18457 I2C.FLT_SDA.counter[0]
.sym 18458 $false
.sym 18459 $true$2
.sym 18461 $abc$92916$n913
.sym 18462 $abc$92916$n914
.sym 18463 $abc$92916$n885
.sym 18464 $false
.sym 18466 $auto$rtlil.cc:1692:NotGate$92753
.sym 18467 $abc$92916$n846
.sym 18468 $abc$92916$n859
.sym 18469 $false
.sym 18471 $auto$rtlil.cc:1692:NotGate$92753
.sym 18472 $false
.sym 18473 $false
.sym 18474 $false
.sym 18476 KEYBOARD.COLS_SHADOW[1]
.sym 18477 $abc$92916$n656
.sym 18478 $abc$92916$n651
.sym 18479 $false
.sym 18481 KEYBOARD.COLS_SHADOW[6]
.sym 18482 $abc$92916$n1219_1
.sym 18483 $abc$92916$n1218
.sym 18484 $false
.sym 18486 $abc$92916$n662
.sym 18487 $abc$92916$n1237_1
.sym 18488 $abc$92916$n1223_1
.sym 18489 $abc$92916$n1236
.sym 18491 KEYBOARD.COLS_SHADOW[4]
.sym 18492 $abc$92916$n646
.sym 18493 $abc$92916$n641
.sym 18494 $false
.sym 18495 RESET$2
.sym 18496 CLK$2$2
.sym 18497 $false
.sym 18498 KEYBOARD.RAM.r_data[4]
.sym 18500 KEYBOARD.RAM.r_data[5]
.sym 18502 KEYBOARD.RAM.r_data[6]
.sym 18504 KEYBOARD.RAM.r_data[7]
.sym 18572 $auto$rtlil.cc:1692:NotGate$92753
.sym 18573 $abc$92916$n846
.sym 18574 $abc$92916$n857
.sym 18575 $abc$92916$n871
.sym 18577 $auto$rtlil.cc:1692:NotGate$92753
.sym 18578 $abc$92916$n846
.sym 18579 $abc$92916$n858
.sym 18580 $abc$92916$n865
.sym 18582 KEYBOARD.temp[2]
.sym 18583 KEYBOARD.RAM.r_data[2]
.sym 18584 $abc$92916$n628
.sym 18585 $false
.sym 18587 KEYBOARD.temp[0]
.sym 18588 KEYBOARD.RAM.r_data[0]
.sym 18589 $abc$92916$n628
.sym 18590 $false
.sym 18592 $false
.sym 18593 wr_cnt[0]
.sym 18594 $false
.sym 18595 $true$2
.sym 18597 $abc$92916$n896
.sym 18598 $abc$92916$n887
.sym 18599 $abc$92916$n897
.sym 18600 $false
.sym 18602 $abc$92916$n877
.sym 18603 $abc$92916$n878
.sym 18604 $abc$92916$n884
.sym 18605 $abc$92916$n885
.sym 18607 $false
.sym 18608 $false
.sym 18609 $false
.sym 18610 $false
.sym 18611 $auto$dff2dffe.cc:175:make_patterns_logic$91425$2
.sym 18612 CLK$2$2
.sym 18613 $false
.sym 18614 KEYBOARD.kbd_code_hid[0]
.sym 18615 KEYBOARD.kbd_code_hid[1]
.sym 18616 KEYBOARD.kbd_code_hid[2]
.sym 18617 KEYBOARD.kbd_code_hid[3]
.sym 18618 KEYBOARD.kbd_code_hid[4]
.sym 18619 KEYBOARD.kbd_code_hid[5]
.sym 18620 KEYBOARD.kbd_code_hid[6]
.sym 18621 KEYBOARD.kbd_code_hid[7]
.sym 18688 $abc$92916$n904
.sym 18689 $abc$92916$n905
.sym 18690 $abc$92916$n906
.sym 18691 $abc$92916$n885
.sym 18693 KEYBOARD.kbd_code_hid[7]
.sym 18694 KEYBOARD.kbd_code_hid[6]
.sym 18695 KEYBOARD.report[4][6]
.sym 18696 KEYBOARD.report[4][7]
.sym 18698 $auto$rtlil.cc:1692:NotGate$92753
.sym 18699 $abc$92916$n846
.sym 18700 $abc$92916$n858
.sym 18701 $false
.sym 18703 $auto$rtlil.cc:1692:NotGate$92753
.sym 18704 $abc$92916$n846
.sym 18705 $abc$92916$n859
.sym 18706 $false
.sym 18708 $abc$92916$n863
.sym 18709 $abc$92916$n862
.sym 18710 $abc$92916$n859
.sym 18711 $false
.sym 18713 KEYBOARD.report[4][0]
.sym 18714 KEYBOARD.report[4][1]
.sym 18715 KEYBOARD.report[4][2]
.sym 18716 KEYBOARD.report[4][3]
.sym 18718 $abc$92916$n858
.sym 18719 $abc$92916$n864
.sym 18720 $false
.sym 18721 $false
.sym 18723 $techmap$techmap\KEYBOARD.$shl$matrix_kbd.v:51$296.$procmux$66087_Y[13]
.sym 18724 $false
.sym 18725 $false
.sym 18726 $false
.sym 18727 $auto$dff2dffe.cc:175:make_patterns_logic$91425$2
.sym 18728 CLK$2$2
.sym 18729 $auto$rtlil.cc:1692:NotGate$92861
.sym 18804 $auto$rtlil.cc:1692:NotGate$92893$2
.sym 18805 KEYBOARD.row_counter[0]
.sym 18806 KEYBOARD.row_counter[1]
.sym 18807 $false
.sym 18814 $auto$wreduce.cc:310:run$57529[1]
.sym 18815 $auto$wreduce.cc:310:run$57529[0]
.sym 18816 $auto$wreduce.cc:310:run$57529[2]
.sym 18817 $false
.sym 18819 $auto$rtlil.cc:1692:NotGate$92753
.sym 18820 KEYBOARD.kbd_code_hid[3]
.sym 18821 $false
.sym 18822 $false
.sym 18824 $false
.sym 18825 $false
.sym 18826 $false
.sym 18827 $false
.sym 18829 $auto$wreduce.cc:310:run$57529[0]
.sym 18830 $false
.sym 18831 $false
.sym 18832 $false
.sym 18843 $auto$dff2dffe.cc:175:make_patterns_logic$91425$2
.sym 18844 CLK$2$2
.sym 18845 $false
.sym 18920 $abc$92916$n770
.sym 18921 I2C.received_byte[4]
.sym 18922 I2C.received_byte[5]
.sym 18923 $false
.sym 18925 $abc$92916$n769_1
.sym 18926 $abc$92916$n771
.sym 18927 $false
.sym 18928 $false
.sym 18930 $abc$92916$n752
.sym 18931 $abc$92916$n1082
.sym 18932 $abc$92916$n771
.sym 18933 $false
.sym 18935 I2C.received_byte[5]
.sym 18936 I2C.received_byte[4]
.sym 18937 $abc$92916$n770
.sym 18938 $false
.sym 18940 I2C.received_byte[0]
.sym 18941 I2C.received_byte[3]
.sym 18942 I2C.received_byte[1]
.sym 18943 I2C.received_byte[2]
.sym 18945 I2C.received_byte[0]
.sym 18946 I2C.received_byte[3]
.sym 18947 I2C.received_byte[1]
.sym 18948 I2C.received_byte[2]
.sym 18950 $abc$92916$n969
.sym 18951 ring_wr[0]
.sym 18952 ring_wr[1]
.sym 18953 $false
.sym 18955 $abc$92916$n752
.sym 18956 $abc$92916$n770
.sym 18957 $abc$92916$n771
.sym 18958 I2C.received_byte[4]
.sym 19036 I2C.received_byte[5]
.sym 19037 I2C.received_byte[4]
.sym 19038 $abc$92916$n1081
.sym 19039 $false
.sym 19041 $add$top.v:98$31_Y[0]
.sym 19042 ring_wr[0]
.sym 19043 $abc$92916$n969
.sym 19044 $false
.sym 19046 $abc$92916$n1081
.sym 19047 $abc$92916$n1076
.sym 19048 $abc$92916$n728
.sym 19049 I2C.received_byte[2]
.sym 19051 $abc$92916$n1080
.sym 19052 $abc$92916$n1076
.sym 19053 $abc$92916$n728
.sym 19054 I2C.received_byte[1]
.sym 19056 $add$top.v:98$31_Y[2]
.sym 19057 ring_wr[2]
.sym 19058 $abc$92916$n969
.sym 19059 $false
.sym 19061 $abc$92916$n833
.sym 19062 $abc$92916$n825
.sym 19063 $auto$simplemap.cc:250:simplemap_eqne$60443[0]
.sym 19064 $false
.sym 19066 $add$top.v:98$31_Y[3]
.sym 19067 ring_wr[3]
.sym 19068 $abc$92916$n969
.sym 19069 $false
.sym 19071 I2C.FLT_SDA.out
.sym 19072 $false
.sym 19073 $false
.sym 19074 $false
.sym 19075 $auto$dff2dffe.cc:175:make_patterns_logic$84986
.sym 19076 CLK$2$2
.sym 19077 $false
.sym 19114 $true
.sym 19151 ring_wr[0]$2
.sym 19152 $false
.sym 19153 ring_wr[0]
.sym 19154 $false
.sym 19155 $false
.sym 19156 $auto$alumacc.cc:484:replace_alu$57668[1]
.sym 19158 $false
.sym 19159 ring_wr[1]
.sym 19161 $auto$alumacc.cc:484:replace_alu$57668[2]
.sym 19162 $false
.sym 19163 $false
.sym 19164 ring_wr[2]
.sym 19165 $auto$alumacc.cc:484:replace_alu$57668[1]
.sym 19166 $auto$alumacc.cc:484:replace_alu$57668[3]$2
.sym 19167 $false
.sym 19168 $false
.sym 19169 ring_wr[3]
.sym 19170 $auto$alumacc.cc:484:replace_alu$57668[2]
.sym 19175 $auto$alumacc.cc:484:replace_alu$57668[3]$2
.sym 19177 $add$top.v:98$31_Y[0]
.sym 19178 $add$top.v:98$31_Y[3]
.sym 19179 ring_rd[0]
.sym 19180 ring_rd[3]
.sym 19182 $abc$92916$n970
.sym 19183 ring_wr[0]
.sym 19184 ring_wr[1]
.sym 19185 ring_rd[1]
.sym 19187 $abc$92916$n971_1
.sym 19188 $add$top.v:98$31_Y[4]
.sym 19189 $add$top.v:98$31_Y[2]
.sym 19190 ring_rd[2]
.sym 19230 $true
.sym 19267 ring_rd[0]$2
.sym 19268 $false
.sym 19269 ring_rd[0]
.sym 19270 $false
.sym 19271 $false
.sym 19272 $auto$alumacc.cc:484:replace_alu$57653[1]
.sym 19274 $false
.sym 19275 ring_rd[1]
.sym 19277 $auto$alumacc.cc:484:replace_alu$57653[2]$2
.sym 19278 $false
.sym 19279 $false
.sym 19280 ring_rd[2]
.sym 19281 $auto$alumacc.cc:484:replace_alu$57653[1]
.sym 19286 $auto$alumacc.cc:484:replace_alu$57653[2]$2
.sym 19288 I2C.received_byte[5]
.sym 19289 $false
.sym 19290 $false
.sym 19291 $false
.sym 19293 I2C.received_byte[7]
.sym 19294 $false
.sym 19295 $false
.sym 19296 $false
.sym 19298 $abc$92916$n833
.sym 19299 $abc$92916$n825
.sym 19300 $auto$simplemap.cc:250:simplemap_eqne$60443[0]
.sym 19301 $false
.sym 19303 I2C.FLT_SDA.out
.sym 19304 $false
.sym 19305 $false
.sym 19306 $false
.sym 19307 $auto$dff2dffe.cc:175:make_patterns_logic$84852
.sym 19308 CLK$2$2
.sym 19309 $false
.sym 19384 $false
.sym 19385 $false
.sym 19386 wr_cnt[3]
.sym 19387 $auto$alumacc.cc:484:replace_alu$57650[2]
.sym 19389 $false
.sym 19390 $true$2
.sym 19391 wr_cnt[0]
.sym 19392 $false
.sym 19394 $2\INT[0:0]
.sym 19395 wr_cnt[0]
.sym 19396 wr_cnt[1]
.sym 19397 $false
.sym 19399 $2\INT[0:0]
.sym 19400 $abc$92916$n740
.sym 19401 $add$top.v:123$53_Y[3]
.sym 19402 $false
.sym 19409 $2\INT[0:0]
.sym 19410 $abc$92916$n740
.sym 19411 $add$top.v:123$53_Y[2]
.sym 19412 $false
.sym 19414 $abc$92916$n740
.sym 19415 $add$top.v:123$53_Y[0]
.sym 19416 $2\INT[0:0]
.sym 19417 $false
.sym 19423 $auto$dff2dffe.cc:175:make_patterns_logic$74485
.sym 19424 CLK$2$2
.sym 19425 $logic_not$top.v:66$10_Y$2
.sym 19500 I2C.byte_counter[3]
.sym 19501 I2C.byte_counter[4]
.sym 19502 I2C.byte_counter[5]
.sym 19503 I2C.byte_counter[6]
.sym 19505 $auto$alumacc.cc:483:replace_alu$57684[2]
.sym 19506 $auto$alumacc.cc:483:replace_alu$57684[7]
.sym 19507 $abc$92916$n735
.sym 19508 $abc$92916$n1142
.sym 19510 $abc$92916$n831_1
.sym 19511 $abc$92916$n833
.sym 19512 $false
.sym 19513 $false
.sym 19515 $abc$92916$n819
.sym 19516 $techmap\I2C.$sub$i2c_slave.v:143$226_Y[2]
.sym 19517 $false
.sym 19518 $false
.sym 19520 $abc$92916$n818
.sym 19521 $abc$92916$n831_1
.sym 19522 $false
.sym 19523 $false
.sym 19530 $auto$alumacc.cc:483:replace_alu$57684[1]
.sym 19531 $false
.sym 19532 $false
.sym 19533 $false
.sym 19535 I2C.FLT_SDA.out
.sym 19536 $false
.sym 19537 $false
.sym 19538 $false
.sym 19539 $auto$dff2dffe.cc:175:make_patterns_logic$85053
.sym 19540 CLK$2$2
.sym 19541 $false
.sym 19616 $techmap\I2C.$procmux$19804_Y
.sym 19617 I2C.byte_counter[4]
.sym 19618 $false
.sym 19619 $false
.sym 19621 $false
.sym 19622 $auto$alumacc.cc:483:replace_alu$57687[0]
.sym 19623 $false
.sym 19624 $true$2
.sym 19626 $techmap\I2C.$procmux$19804_Y
.sym 19627 I2C.byte_counter[3]
.sym 19628 $false
.sym 19629 $false
.sym 19631 $false
.sym 19632 $false
.sym 19633 $auto$alumacc.cc:483:replace_alu$57684[7]
.sym 19634 $auto$alumacc.cc:470:replace_alu$57683.C[7]
.sym 19636 $techmap\I2C.$procmux$19804_Y
.sym 19637 I2C.byte_counter[2]
.sym 19638 $false
.sym 19639 $false
.sym 19646 $techmap\I2C.$procmux$19804_Y
.sym 19647 I2C.byte_counter[7]
.sym 19648 $false
.sym 19649 $false
.sym 19651 $auto$alumacc.cc:483:replace_alu$57684[5]
.sym 19652 $abc$92916$n1141
.sym 19653 $auto$wreduce.cc:310:run$57516[5]
.sym 19654 $abc$92916$n1139
.sym 19655 $true
.sym 19656 CLK$2$2
.sym 19657 $false
.sym 19694 $true
.sym 19731 $auto$alumacc.cc:483:replace_alu$57687[0]$2
.sym 19732 $false
.sym 19733 $auto$alumacc.cc:483:replace_alu$57687[0]
.sym 19734 $false
.sym 19735 $false
.sym 19736 $auto$alumacc.cc:484:replace_alu$57688[1]
.sym 19738 $auto$alumacc.cc:470:replace_alu$57572.B_buf[1]
.sym 19739 $true$2
.sym 19741 $auto$alumacc.cc:484:replace_alu$57688[2]
.sym 19742 $false
.sym 19743 $auto$alumacc.cc:470:replace_alu$57572.B_buf[2]
.sym 19744 $true$2
.sym 19745 $auto$alumacc.cc:484:replace_alu$57688[1]
.sym 19746 $auto$simplemap.cc:309:simplemap_lut$68433[2]$2
.sym 19747 $false
.sym 19748 $auto$alumacc.cc:470:replace_alu$57572.B_buf[3]
.sym 19749 $true$2
.sym 19750 $auto$alumacc.cc:484:replace_alu$57688[2]
.sym 19755 $auto$simplemap.cc:309:simplemap_lut$68433[2]$2
.sym 19757 $auto$alumacc.cc:483:replace_alu$57573[3]
.sym 19758 $false
.sym 19759 $false
.sym 19760 $false
.sym 19767 $techmap$techmap\KEYBOARD.$shl$matrix_kbd.v:51$296.$procmux$66087_Y[13]
.sym 19768 $false
.sym 19769 $false
.sym 19770 $false
.sym 19771 $auto$dff2dffe.cc:175:make_patterns_logic$91425$2
.sym 19772 CLK$2$2
.sym 19773 $auto$wreduce.cc:310:run$57529[3]$2
.sym 19819 $false
.sym 19821 KEYBOARD.ROWS_EN[0]
.sym 19822 $false
.sym 19824 KEYBOARD.ROWS_EN[1]
.sym 19874 $abc$92916$n634
.sym 19875 $abc$92916$n847
.sym 19877 $abc$92916$n1231
.sym 19878 $abc$92916$n613
.sym 19881 KEYBOARD.report[0][7]
.sym 19950 KEYBOARD.COLS_SHADOW[7]
.sym 19952 KEYBOARD.COLS_SHADOW[6]
.sym 19953 KEYBOARD.COLS_SHADOW[5]
.sym 19956 KEYBOARD.COLS_SHADOW[4]
.sym 19957 KEYBOARD.COLS_SHADOW[0]
.sym 20088 KEYBOARD.COLS_SHADOW[2]
.sym 20089 I2C.SCLF
.sym 20094 I2C.SDAF
.sym 20190 $abc$92916$n860
.sym 20191 $techmap\KEYBOARD.$procmux$5651_Y[4]
.sym 20192 $abc$92916$n1219_1
.sym 20193 $abc$92916$n846
.sym 20194 $abc$92916$n861
.sym 20195 $abc$92916$n859
.sym 20196 KEYBOARD.report[3][0]
.sym 20197 KEYBOARD.report[3][4]
.sym 20292 $auto$dff2dffe.cc:175:make_patterns_logic$91231
.sym 20293 $abc$92916$n885
.sym 20294 $abc$92916$n656
.sym 20295 $abc$92916$n640
.sym 20296 $abc$92916$n646
.sym 20297 $auto$wreduce.cc:310:run$57522[6]
.sym 20298 KEYBOARD.row_counter[3]
.sym 20299 KEYBOARD.temp[5]
.sym 20394 $abc$92916$n1001
.sym 20395 $abc$92916$n1005
.sym 20396 $abc$92916$n1199
.sym 20397 $abc$92916$n1203
.sym 20398 $abc$92916$n865
.sym 20399 KEYBOARD.ram_adr[3]
.sym 20400 KEYBOARD.ram_adr[4]
.sym 20401 KEYBOARD.ram_adr[6]
.sym 20402 $undef
.sym 20403 $undef
.sym 20404 $undef
.sym 20405 $undef
.sym 20406 $undef
.sym 20407 $undef
.sym 20408 $undef
.sym 20409 $undef
.sym 20410 KEYBOARD.ram_adr[0]
.sym 20411 KEYBOARD.ram_adr[1]
.sym 20412 $false
.sym 20413 KEYBOARD.ram_adr[2]
.sym 20414 KEYBOARD.ram_adr[3]
.sym 20415 KEYBOARD.ram_adr[4]
.sym 20416 KEYBOARD.ram_adr[5]
.sym 20417 KEYBOARD.ram_adr[6]
.sym 20418 KEYBOARD.ram_adr[7]
.sym 20419 $false
.sym 20420 $false
.sym 20421 CLK$2$2
.sym 20422 $true
.sym 20423 KEYBOARD.temp[0]
.sym 20424 $undef
.sym 20425 KEYBOARD.temp[1]
.sym 20426 $undef
.sym 20427 KEYBOARD.temp[2]
.sym 20428 $undef
.sym 20429 KEYBOARD.temp[3]
.sym 20430 $undef
.sym 20431 KEYBOARD.ram_wr
.sym 20496 $abc$92916$n868
.sym 20497 $abc$92916$n856
.sym 20498 $abc$92916$n864
.sym 20499 $abc$92916$n888
.sym 20500 $auto$dff2dffe.cc:175:make_patterns_logic$88296
.sym 20501 $abc$92916$n887
.sym 20502 $abc$92916$n889
.sym 20503 $abc$92916$n884
.sym 20504 $undef
.sym 20505 $undef
.sym 20506 $undef
.sym 20507 $undef
.sym 20508 $undef
.sym 20509 $undef
.sym 20510 $undef
.sym 20511 $undef
.sym 20512 KEYBOARD.ram_adr[0]
.sym 20513 KEYBOARD.ram_adr[1]
.sym 20514 $false
.sym 20515 KEYBOARD.ram_adr[2]
.sym 20516 KEYBOARD.ram_adr[3]
.sym 20517 KEYBOARD.ram_adr[4]
.sym 20518 KEYBOARD.ram_adr[5]
.sym 20519 KEYBOARD.ram_adr[6]
.sym 20520 KEYBOARD.ram_adr[7]
.sym 20521 $false
.sym 20522 $false
.sym 20523 CLK$2$2
.sym 20524 $true
.sym 20525 $true$2
.sym 20526 KEYBOARD.temp[5]
.sym 20527 $undef
.sym 20528 KEYBOARD.temp[6]
.sym 20529 $undef
.sym 20530 KEYBOARD.temp[7]
.sym 20531 $undef
.sym 20532 KEYBOARD.temp[4]
.sym 20533 $undef
.sym 20598 KEYBOARD.kbd_code[7]
.sym 20599 KEYBOARD.kbd_code[5]
.sym 20600 KEYBOARD.kbd_code[6]
.sym 20601 KEYBOARD.kbd_code[4]
.sym 20602 KEYBOARD.kbd_code[2]
.sym 20603 KEYBOARD.row_counter[1]
.sym 20604 KEYBOARD.kbd_code[3]
.sym 20605 KEYBOARD.row_counter[0]
.sym 20614 $false
.sym 20615 $false
.sym 20617 $false
.sym 20618 $false
.sym 20619 $false
.sym 20620 $false
.sym 20621 $false
.sym 20622 $false
.sym 20625 $false
.sym 20626 $false$2
.sym 20627 $false
.sym 20628 $false
.sym 20629 $false
.sym 20630 $false
.sym 20631 $false
.sym 20632 $false
.sym 20633 $false
.sym 20634 $false
.sym 20635 $false
.sym 20700 $add$top.v:98$31_Y[0]
.sym 20701 $abc$92916$n782
.sym 20702 $techmap$techmap\KEYBOARD.$shl$matrix_kbd.v:51$296.$procmux$66087_Y[8]
.sym 20704 $abc$92916$n777
.sym 20705 $auto$wreduce.cc:310:run$57529[1]
.sym 20707 I2C.received_byte[5]
.sym 20716 KEYBOARD.kbd_code[0]
.sym 20717 KEYBOARD.kbd_code[1]
.sym 20719 KEYBOARD.kbd_code[2]
.sym 20720 KEYBOARD.kbd_code[3]
.sym 20721 KEYBOARD.kbd_code[4]
.sym 20722 KEYBOARD.kbd_code[5]
.sym 20723 KEYBOARD.kbd_code[6]
.sym 20724 KEYBOARD.kbd_code[7]
.sym 20727 CLK$2$2
.sym 20728 $true
.sym 20729 $true$2
.sym 20804 $auto$alumacc.cc:484:replace_alu$57694[1]
.sym 20805 $abc$92916$n770
.sym 20806 $abc$92916$n1075
.sym 20807 $auto$dff2dffe.cc:175:make_patterns_logic$84919
.sym 20808 ring_wr[0]
.sym 20809 ring_wr[2]
.sym 20904 $auto$alumacc.cc:483:replace_alu$57618[3]
.sym 20905 $abc$92916$n1086_1
.sym 20906 $add$top.v:98$31_Y[4]
.sym 20907 $abc$92916$n1076
.sym 20908 $techmap\UART.$sub$uart.v:40$540_Y[2]
.sym 20909 $auto$alumacc.cc:483:replace_alu$57618[6]
.sym 20910 $auto$alumacc.cc:483:replace_alu$57618[4]
.sym 20911 I2C.received_byte[0]
.sym 21013 $auto$alumacc.cc:484:replace_alu$57619[7]
.sym 21110 $add$top.v:123$53_Y[2]
.sym 21111 $auto$alumacc.cc:484:replace_alu$57650[2]
.sym 21113 $auto$alumacc.cc:483:replace_alu$57618[2]
.sym 21114 KEYBOARD.ROWS_EN[2]
.sym 21115 KEYBOARD.ROWS_EN[0]
.sym 21210 $techmap$auto$alumacc.cc:470:replace_alu$57683.$not$/usr/bin/../share/yosys/ice40/arith_map.v:42$58930_Y[7]
.sym 21211 $techmap$auto$alumacc.cc:470:replace_alu$57683.$not$/usr/bin/../share/yosys/ice40/arith_map.v:42$58930_Y[6]
.sym 21212 $techmap$auto$alumacc.cc:470:replace_alu$57683.$not$/usr/bin/../share/yosys/ice40/arith_map.v:42$58930_Y[2]
.sym 21213 $auto$alumacc.cc:483:replace_alu$57684[5]
.sym 21214 $techmap$auto$alumacc.cc:470:replace_alu$57683.$not$/usr/bin/../share/yosys/ice40/arith_map.v:42$58930_Y[5]
.sym 21215 $auto$alumacc.cc:483:replace_alu$57684[6]
.sym 21216 $abc$92916$n818
.sym 21217 I2C.received_byte[3]
.sym 21312 $abc$92916$n1139
.sym 21313 $techmap$auto$alumacc.cc:470:replace_alu$57683.$not$/usr/bin/../share/yosys/ice40/arith_map.v:42$58930_Y[4]
.sym 21314 I2C.byte_counter[7]
.sym 21315 I2C.byte_counter[3]
.sym 21316 I2C.byte_counter[6]
.sym 21318 I2C.byte_counter[4]
.sym 21319 I2C.byte_counter[2]
.sym 21416 $auto$wreduce.cc:310:run$57516[2]
.sym 21417 $auto$wreduce.cc:310:run$57516[3]
.sym 21418 $auto$wreduce.cc:310:run$57516[4]
.sym 21419 $auto$wreduce.cc:310:run$57516[5]
.sym 21420 $auto$wreduce.cc:310:run$57516[6]
.sym 21421 $auto$alumacc.cc:470:replace_alu$57683.C[7]
.sym 21591 $false
.sym 21593 KEYBOARD.ROWS_EN[2]
.sym 21594 $false
.sym 21596 KEYBOARD.ROWS_EN[3]
.sym 21651 $auto$alumacc.cc:484:replace_alu$57558[7]
.sym 21721 KEYBOARD.RAM.r_data[6]
.sym 21722 KEYBOARD.temp[6]
.sym 21723 $abc$92916$n628
.sym 21724 KEYBOARD.COLS_SHADOW[6]
.sym 21726 $abc$92916$n848
.sym 21727 $auto$alumacc.cc:484:replace_alu$57558[7]
.sym 21728 $false
.sym 21729 $false
.sym 21736 $abc$92916$n641
.sym 21737 $abc$92916$n646
.sym 21738 KEYBOARD.COLS_SHADOW[4]
.sym 21739 $false
.sym 21741 KEYBOARD.is_pressed
.sym 21742 $abc$92916$n620
.sym 21743 $abc$92916$n635
.sym 21744 $abc$92916$n614
.sym 21756 KEYBOARD.report[0][7]
.sym 21757 $auto$rtlil.cc:1692:NotGate$92753
.sym 21758 $abc$92916$n849
.sym 21759 $false
.sym 21760 $auto$dff2dffe.cc:175:make_patterns_logic$91231
.sym 21761 CLK$2$2
.sym 21762 $logic_not$top.v:66$10_Y$2
.sym 21774 $auto$rtlil.cc:1692:NotGate$92861
.sym 21877 KBD_COLUMNS[7]$2
.sym 21878 $false
.sym 21879 $false
.sym 21880 $false
.sym 21887 KBD_COLUMNS[6]$2
.sym 21888 $false
.sym 21889 $false
.sym 21890 $false
.sym 21892 KBD_COLUMNS[5]$2
.sym 21893 $false
.sym 21894 $false
.sym 21895 $false
.sym 21907 KBD_COLUMNS[4]$2
.sym 21908 $false
.sym 21909 $false
.sym 21910 $false
.sym 21912 KBD_COLUMNS[0]$2
.sym 21913 $false
.sym 21914 $false
.sym 21915 $false
.sym 21916 $true
.sym 21917 CLK$2$2
.sym 21918 $false
.sym 21919 $auto$wreduce.cc:310:run$57528[0]
.sym 21920 KEYBOARD.report[4][5]
.sym 21921 KEYBOARD.report[4][0]
.sym 21923 KEYBOARD.report[4][4]
.sym 21993 KBD_COLUMNS[2]$2
.sym 21994 $false
.sym 21995 $false
.sym 21996 $false
.sym 21998 SCL$2
.sym 21999 $false
.sym 22000 $false
.sym 22001 $false
.sym 22023 I2C.SDA_IN
.sym 22024 $false
.sym 22025 $false
.sym 22026 $false
.sym 22032 $true
.sym 22033 CLK$2$2
.sym 22034 $false
.sym 22035 KEYBOARD.report[1][7]
.sym 22036 KEYBOARD.report[1][2]
.sym 22037 KEYBOARD.report[1][4]
.sym 22038 KEYBOARD.report[1][1]
.sym 22039 KEYBOARD.report[1][6]
.sym 22040 KEYBOARD.report[1][0]
.sym 22041 KEYBOARD.report[1][3]
.sym 22042 KEYBOARD.report[1][5]
.sym 22109 KEYBOARD.report[1][4]
.sym 22110 KEYBOARD.report[1][5]
.sym 22111 KEYBOARD.report[1][6]
.sym 22112 KEYBOARD.report[1][7]
.sym 22114 $auto$rtlil.cc:1692:NotGate$92753
.sym 22115 KEYBOARD.kbd_code_hid[4]
.sym 22116 $false
.sym 22117 $false
.sym 22119 KEYBOARD.temp[6]
.sym 22120 KEYBOARD.RAM.r_data[6]
.sym 22121 $abc$92916$n628
.sym 22122 $false
.sym 22124 $techmap\KEYBOARD.$procmux$18803_CMP
.sym 22125 $abc$92916$n847
.sym 22126 RESET$2
.sym 22127 $false
.sym 22129 KEYBOARD.report[1][0]
.sym 22130 KEYBOARD.report[1][1]
.sym 22131 KEYBOARD.report[1][2]
.sym 22132 KEYBOARD.report[1][3]
.sym 22134 $abc$92916$n860
.sym 22135 $abc$92916$n861
.sym 22136 $false
.sym 22137 $false
.sym 22139 $techmap\KEYBOARD.$procmux$5651_Y[0]
.sym 22140 $false
.sym 22141 $false
.sym 22142 $false
.sym 22144 $techmap\KEYBOARD.$procmux$5651_Y[4]
.sym 22145 $false
.sym 22146 $false
.sym 22147 $false
.sym 22148 $auto$dff2dffe.cc:175:make_patterns_logic$89305
.sym 22149 CLK$2$2
.sym 22150 $logic_not$top.v:66$10_Y$2
.sym 22151 $abc$92916$n927
.sym 22152 $techmap\I2C.FLT_SDA.$procmux$1018_Y[0]
.sym 22153 $abc$92916$n928
.sym 22154 $auto$dff2dffe.cc:175:make_patterns_logic$92215
.sym 22155 $auto$dff2dffe.cc:158:make_patterns_logic$92230
.sym 22156 I2C.FLT_SDA.counter[2]
.sym 22157 I2C.FLT_SDA.counter[1]
.sym 22158 I2C.FLT_SDA.counter[0]
.sym 22225 RESET$2
.sym 22226 $abc$92916$n847
.sym 22227 $techmap\KEYBOARD.$procmux$18803_CMP
.sym 22228 $false
.sym 22230 $abc$92916$n847
.sym 22231 $techmap\KEYBOARD.$procmux$18803_CMP
.sym 22232 RESET$2
.sym 22233 $false
.sym 22235 KEYBOARD.temp[1]
.sym 22236 KEYBOARD.RAM.r_data[1]
.sym 22237 $abc$92916$n628
.sym 22238 $false
.sym 22240 KEYBOARD.temp[5]
.sym 22241 KEYBOARD.RAM.r_data[5]
.sym 22242 $abc$92916$n628
.sym 22243 $false
.sym 22245 KEYBOARD.temp[4]
.sym 22246 KEYBOARD.RAM.r_data[4]
.sym 22247 $abc$92916$n628
.sym 22248 $false
.sym 22250 KEYBOARD.row_counter[3]
.sym 22251 $auto$wreduce.cc:310:run$57529[3]$2
.sym 22252 $auto$rtlil.cc:1692:NotGate$92893$2
.sym 22253 $false
.sym 22255 $auto$wreduce.cc:310:run$57522[6]
.sym 22256 $false
.sym 22257 $false
.sym 22258 $false
.sym 22260 KEYBOARD.COLS_SHADOW[5]
.sym 22261 $abc$92916$n640
.sym 22262 $abc$92916$n614
.sym 22263 $false
.sym 22264 RESET$2
.sym 22265 CLK$2$2
.sym 22266 $false
.sym 22267 $techmap\I2C.FLT_SDA.$procmux$1018_Y[1]
.sym 22268 $auto$wreduce.cc:310:run$57521[2]
.sym 22269 KEYBOARD.ROWS_EN[15]
.sym 22270 KEYBOARD.ROWS_EN[11]
.sym 22273 KEYBOARD.ROWS_EN[10]
.sym 22341 wr_cnt[0]
.sym 22342 wr_cnt[1]
.sym 22343 $sub$top.v:122$51_Y[0]
.sym 22344 $sub$top.v:122$51_Y[2]
.sym 22346 wr_cnt[0]
.sym 22347 wr_cnt[1]
.sym 22348 $sub$top.v:122$51_Y[0]
.sym 22349 $sub$top.v:122$51_Y[2]
.sym 22351 KEYBOARD.kbd_code_hid[2]
.sym 22352 KEYBOARD.kbd_code_hid[1]
.sym 22353 KEYBOARD.kbd_code_hid[0]
.sym 22354 $false
.sym 22356 KEYBOARD.kbd_code_hid[2]
.sym 22357 KEYBOARD.kbd_code_hid[1]
.sym 22358 KEYBOARD.kbd_code_hid[0]
.sym 22359 $false
.sym 22361 $abc$92916$n866
.sym 22362 $abc$92916$n867
.sym 22363 $false
.sym 22364 $false
.sym 22366 $auto$wreduce.cc:310:run$57529[3]$2
.sym 22367 $false
.sym 22368 $false
.sym 22369 $false
.sym 22371 $false
.sym 22372 $false
.sym 22373 $false
.sym 22374 $false
.sym 22376 $false
.sym 22377 $false
.sym 22378 $false
.sym 22379 $false
.sym 22380 $auto$dff2dffe.cc:175:make_patterns_logic$91425$2
.sym 22381 CLK$2$2
.sym 22382 $false
.sym 22383 $techmap\KEYBOARD.$procmux$5651_Y[2]
.sym 22384 $abc$92916$n892
.sym 22386 $abc$92916$n893
.sym 22387 $abc$92916$n890
.sym 22388 $techmap\KEYBOARD.$procmux$5651_Y[7]
.sym 22389 $abc$92916$n891
.sym 22390 I2C.received_byte[1]
.sym 22457 KEYBOARD.report[4][4]
.sym 22458 KEYBOARD.report[4][5]
.sym 22459 KEYBOARD.report[4][6]
.sym 22460 KEYBOARD.report[4][7]
.sym 22462 $auto$rtlil.cc:1692:NotGate$92753
.sym 22463 $abc$92916$n846
.sym 22464 $abc$92916$n857
.sym 22465 $false
.sym 22467 $abc$92916$n869
.sym 22468 $abc$92916$n868
.sym 22469 $abc$92916$n865
.sym 22470 $false
.sym 22472 $auto$rtlil.cc:1692:NotGate$92753
.sym 22473 $abc$92916$n846
.sym 22474 $abc$92916$n858
.sym 22475 $abc$92916$n865
.sym 22477 $abc$92916$n856
.sym 22478 $abc$92916$n887
.sym 22479 $abc$92916$n888
.sym 22480 $abc$92916$n889
.sym 22482 $abc$92916$n885
.sym 22483 $abc$92916$n846
.sym 22484 $auto$rtlil.cc:1692:NotGate$92753
.sym 22485 $abc$92916$n858
.sym 22487 $abc$92916$n894
.sym 22488 $abc$92916$n890
.sym 22489 $auto$rtlil.cc:1692:NotGate$92753
.sym 22490 $abc$92916$n846
.sym 22492 $abc$92916$n864
.sym 22493 $abc$92916$n858
.sym 22494 $auto$rtlil.cc:1692:NotGate$92753
.sym 22495 $abc$92916$n846
.sym 22499 $techmap\KEYBOARD.$procmux$5651_Y[6]
.sym 22500 $techmap$techmap\KEYBOARD.$shl$matrix_kbd.v:51$296.$procmux$66087_Y[11]
.sym 22501 $auto$simplemap.cc:309:simplemap_lut$68704[0]
.sym 22502 $auto$dff2dffe.cc:175:make_patterns_logic$91425
.sym 22503 $techmap$techmap\KEYBOARD.$shl$matrix_kbd.v:51$296.$procmux$66087_Y[14]
.sym 22504 KEYBOARD.ram_adr[1]
.sym 22506 KEYBOARD.ram_adr[2]
.sym 22573 $techmap\KEYBOARD.$procmux$8869_Y[7]
.sym 22574 $false
.sym 22575 $false
.sym 22576 $false
.sym 22578 $techmap\KEYBOARD.$procmux$8869_Y[7]
.sym 22579 $auto$wreduce.cc:310:run$57522[5]
.sym 22580 $false
.sym 22581 $false
.sym 22583 $techmap\KEYBOARD.$procmux$8869_Y[7]
.sym 22584 $auto$wreduce.cc:310:run$57522[6]
.sym 22585 $false
.sym 22586 $false
.sym 22588 $techmap\KEYBOARD.$procmux$8869_Y[7]
.sym 22589 $auto$simplemap.cc:309:simplemap_lut$69160[0]
.sym 22590 $false
.sym 22591 $false
.sym 22593 $techmap\KEYBOARD.$procmux$8869_Y[2]
.sym 22594 $false
.sym 22595 $false
.sym 22596 $false
.sym 22598 $auto$simplemap.cc:309:simplemap_lut$69160[0]
.sym 22599 $false
.sym 22600 $false
.sym 22601 $false
.sym 22603 $techmap\KEYBOARD.$procmux$8869_Y[7]
.sym 22604 $auto$simplemap.cc:309:simplemap_lut$68704[0]
.sym 22605 $false
.sym 22606 $false
.sym 22608 $auto$simplemap.cc:309:simplemap_lut$68704[0]
.sym 22609 $false
.sym 22610 $false
.sym 22611 $false
.sym 22612 RESET$2
.sym 22613 CLK$2$2
.sym 22614 $false
.sym 22616 $logic_not$top.v:66$10_Y
.sym 22617 KEYBOARD.report[4][2]
.sym 22619 KEYBOARD.report[4][1]
.sym 22620 KEYBOARD.report[4][6]
.sym 22622 KEYBOARD.report[4][3]
.sym 22689 $false
.sym 22690 $true$2
.sym 22691 ring_wr[0]
.sym 22692 $false
.sym 22694 I2C.received_byte[0]
.sym 22695 I2C.received_byte[3]
.sym 22696 I2C.received_byte[1]
.sym 22697 I2C.received_byte[2]
.sym 22699 $auto$wreduce.cc:310:run$57529[1]
.sym 22700 $auto$wreduce.cc:310:run$57529[0]
.sym 22701 $auto$wreduce.cc:310:run$57529[2]
.sym 22702 $false
.sym 22709 $abc$92916$n769_1
.sym 22710 $abc$92916$n778
.sym 22711 $false
.sym 22712 $false
.sym 22714 KEYBOARD.row_counter[0]
.sym 22715 KEYBOARD.row_counter[1]
.sym 22716 $false
.sym 22717 $false
.sym 22724 I2C.FLT_SDA.out
.sym 22725 $false
.sym 22726 $false
.sym 22727 $false
.sym 22728 $auto$dff2dffe.cc:175:make_patterns_logic$84919
.sym 22729 CLK$2$2
.sym 22730 $false
.sym 22731 $techmap$techmap\KEYBOARD.$shl$matrix_kbd.v:51$296.$procmux$66087_Y[12]
.sym 22732 $techmap$techmap\KEYBOARD.$shl$matrix_kbd.v:51$296.$procmux$66087_Y[15]
.sym 22733 $auto$wreduce.cc:310:run$57529[0]
.sym 22735 $techmap$techmap\KEYBOARD.$shl$matrix_kbd.v:51$296.$procmux$66087_Y[9]
.sym 22736 $techmap$techmap\KEYBOARD.$shl$matrix_kbd.v:51$296.$procmux$66087_Y[10]
.sym 22737 KEYBOARD.ROWS_EN[9]
.sym 22738 KEYBOARD.ROWS_EN[12]
.sym 22767 $true
.sym 22804 I2C.FLT_SDA.counter[0]$2
.sym 22805 $false
.sym 22806 I2C.FLT_SDA.counter[0]
.sym 22807 $false
.sym 22808 $false
.sym 22809 $auto$alumacc.cc:484:replace_alu$57694[1]$2
.sym 22811 I2C.FLT_SDA.counter[1]
.sym 22812 $true$2
.sym 22818 $auto$alumacc.cc:484:replace_alu$57694[1]$2
.sym 22820 I2C.received_byte[7]
.sym 22821 I2C.received_byte[6]
.sym 22822 $false
.sym 22823 $false
.sym 22825 $abc$92916$n1077_1
.sym 22826 $abc$92916$n1076
.sym 22827 $abc$92916$n728
.sym 22828 I2C.received_byte[0]
.sym 22830 $abc$92916$n833
.sym 22831 $abc$92916$n825
.sym 22832 $auto$simplemap.cc:250:simplemap_eqne$60443[0]
.sym 22833 $false
.sym 22835 $2\ring_wr[3:0][0]
.sym 22836 $false
.sym 22837 $false
.sym 22838 $false
.sym 22840 $2\ring_wr[3:0][2]
.sym 22841 $false
.sym 22842 $false
.sym 22843 $false
.sym 22844 $auto$dff2dffe.cc:175:make_patterns_logic$73370
.sym 22845 CLK$2$2
.sym 22846 $logic_not$top.v:66$10_Y$2
.sym 22849 $auto$alumacc.cc:484:replace_alu$57733[1]
.sym 22850 $auto$alumacc.cc:483:replace_alu$57618[1]
.sym 22851 $auto$dff2dffe.cc:175:make_patterns_logic$84651
.sym 22852 $auto$dff2dffe.cc:175:make_patterns_logic$84584
.sym 22921 I2C.received_byte[3]
.sym 22922 $false
.sym 22923 $false
.sym 22924 $false
.sym 22926 $abc$92916$n1076
.sym 22927 $abc$92916$n728
.sym 22928 I2C.received_byte[3]
.sym 22929 $false
.sym 22931 $false
.sym 22932 $false
.sym 22933 $false
.sym 22934 $auto$alumacc.cc:484:replace_alu$57668[3]
.sym 22936 $auto$alumacc.cc:484:replace_alu$57619[7]
.sym 22937 $abc$92916$n777
.sym 22938 $auto$alumacc.cc:484:replace_alu$57642[7]
.sym 22939 $false
.sym 22941 $false
.sym 22942 $false
.sym 22943 $auto$alumacc.cc:483:replace_alu$57552[2]
.sym 22944 $auto$alumacc.cc:484:replace_alu$57733[1]
.sym 22946 I2C.received_byte[6]
.sym 22947 $false
.sym 22948 $false
.sym 22949 $false
.sym 22951 I2C.received_byte[4]
.sym 22952 $false
.sym 22953 $false
.sym 22954 $false
.sym 22956 I2C.FLT_SDA.out
.sym 22957 $false
.sym 22958 $false
.sym 22959 $false
.sym 22960 $auto$dff2dffe.cc:175:make_patterns_logic$84584
.sym 22961 CLK$2$2
.sym 22962 $false
.sym 22970 $auto$alumacc.cc:484:replace_alu$57642[7]
.sym 22999 $true
.sym 23036 $auto$alumacc.cc:483:replace_alu$57618[1]$2
.sym 23037 $false
.sym 23038 $auto$alumacc.cc:483:replace_alu$57618[1]
.sym 23039 $false
.sym 23040 $false
.sym 23041 $auto$alumacc.cc:484:replace_alu$57619[2]
.sym 23043 $false
.sym 23044 $auto$alumacc.cc:483:replace_alu$57618[2]
.sym 23046 $auto$alumacc.cc:484:replace_alu$57619[3]
.sym 23048 $false
.sym 23049 $auto$alumacc.cc:483:replace_alu$57618[3]
.sym 23051 $auto$alumacc.cc:484:replace_alu$57619[4]
.sym 23053 $false
.sym 23054 $auto$alumacc.cc:483:replace_alu$57618[4]
.sym 23056 $auto$alumacc.cc:484:replace_alu$57619[5]
.sym 23058 $false
.sym 23059 $auto$alumacc.cc:483:replace_alu$57618[5]
.sym 23061 $auto$alumacc.cc:484:replace_alu$57619[6]
.sym 23063 $false
.sym 23064 $auto$alumacc.cc:483:replace_alu$57618[6]
.sym 23066 $auto$alumacc.cc:484:replace_alu$57619[7]$2
.sym 23068 $false
.sym 23069 $auto$alumacc.cc:483:replace_alu$57618[7]
.sym 23075 $auto$alumacc.cc:484:replace_alu$57619[7]$2
.sym 23079 $auto$dff2dffe.cc:175:make_patterns_logic$84718
.sym 23080 LED1$2
.sym 23082 I2C.received_byte[2]
.sym 23115 $true
.sym 23152 wr_cnt[0]$2
.sym 23153 $false
.sym 23154 wr_cnt[0]
.sym 23155 $false
.sym 23156 $false
.sym 23157 $auto$alumacc.cc:484:replace_alu$57650[1]
.sym 23159 $false
.sym 23160 wr_cnt[1]
.sym 23162 $auto$alumacc.cc:484:replace_alu$57650[2]$2
.sym 23163 $false
.sym 23164 $false
.sym 23165 wr_cnt[2]
.sym 23166 $auto$alumacc.cc:484:replace_alu$57650[1]
.sym 23171 $auto$alumacc.cc:484:replace_alu$57650[2]$2
.sym 23178 I2C.received_byte[2]
.sym 23179 $false
.sym 23180 $false
.sym 23181 $false
.sym 23183 $techmap$techmap\KEYBOARD.$shl$matrix_kbd.v:51$296.$procmux$66087_Y[10]
.sym 23184 $false
.sym 23185 $false
.sym 23186 $false
.sym 23188 $techmap$techmap\KEYBOARD.$shl$matrix_kbd.v:51$296.$procmux$66087_Y[8]
.sym 23189 $false
.sym 23190 $false
.sym 23191 $false
.sym 23192 $auto$dff2dffe.cc:175:make_patterns_logic$91425$2
.sym 23193 CLK$2$2
.sym 23194 $auto$wreduce.cc:310:run$57529[3]$2
.sym 23202 $auto$alumacc.cc:484:replace_alu$57680[7]
.sym 23269 $auto$alumacc.cc:483:replace_alu$57684[7]
.sym 23270 $false
.sym 23271 $false
.sym 23272 $false
.sym 23274 $auto$alumacc.cc:483:replace_alu$57684[6]
.sym 23275 $false
.sym 23276 $false
.sym 23277 $false
.sym 23279 $auto$alumacc.cc:483:replace_alu$57684[2]
.sym 23280 $false
.sym 23281 $false
.sym 23282 $false
.sym 23284 $techmap\I2C.$procmux$19804_Y
.sym 23285 I2C.byte_counter[5]
.sym 23286 $false
.sym 23287 $false
.sym 23289 $auto$alumacc.cc:483:replace_alu$57684[5]
.sym 23290 $false
.sym 23291 $false
.sym 23292 $false
.sym 23294 $techmap\I2C.$procmux$19804_Y
.sym 23295 I2C.byte_counter[6]
.sym 23296 $false
.sym 23297 $false
.sym 23299 $abc$92916$n819
.sym 23300 $techmap\I2C.$sub$i2c_slave.v:143$226_Y[2]
.sym 23301 $false
.sym 23302 $false
.sym 23304 I2C.FLT_SDA.out
.sym 23305 $false
.sym 23306 $false
.sym 23307 $false
.sym 23308 $auto$dff2dffe.cc:175:make_patterns_logic$84785
.sym 23309 CLK$2$2
.sym 23310 $false
.sym 23311 $techmap$auto$alumacc.cc:470:replace_alu$57683.$not$/usr/bin/../share/yosys/ice40/arith_map.v:42$58930_Y[3]
.sym 23312 KEYBOARD.ROWS_EN[4]
.sym 23314 KEYBOARD.ROWS_EN[3]
.sym 23315 KEYBOARD.ROWS_EN[6]
.sym 23316 KEYBOARD.ROWS_EN[7]
.sym 23318 KEYBOARD.ROWS_EN[1]
.sym 23385 $abc$92916$n1140
.sym 23386 $abc$92916$n823
.sym 23387 $false
.sym 23388 $false
.sym 23390 $auto$alumacc.cc:483:replace_alu$57684[4]
.sym 23391 $false
.sym 23392 $false
.sym 23393 $false
.sym 23395 $auto$alumacc.cc:483:replace_alu$57684[7]
.sym 23396 $abc$92916$n1141
.sym 23397 $auto$wreduce.cc:310:run$57516[7]
.sym 23398 $abc$92916$n1139
.sym 23400 $auto$alumacc.cc:483:replace_alu$57684[3]
.sym 23401 $abc$92916$n1141
.sym 23402 $auto$wreduce.cc:310:run$57516[3]
.sym 23403 $abc$92916$n1139
.sym 23405 $auto$alumacc.cc:483:replace_alu$57684[6]
.sym 23406 $abc$92916$n1141
.sym 23407 $auto$wreduce.cc:310:run$57516[6]
.sym 23408 $abc$92916$n1139
.sym 23415 $auto$alumacc.cc:483:replace_alu$57684[4]
.sym 23416 $abc$92916$n1141
.sym 23417 $auto$wreduce.cc:310:run$57516[4]
.sym 23418 $abc$92916$n1139
.sym 23420 $auto$alumacc.cc:483:replace_alu$57684[2]
.sym 23421 $abc$92916$n1141
.sym 23422 $auto$wreduce.cc:310:run$57516[2]
.sym 23423 $abc$92916$n1139
.sym 23424 $true
.sym 23425 CLK$2$2
.sym 23426 $false
.sym 23463 $true
.sym 23500 $auto$alumacc.cc:470:replace_alu$57683.C[1]$2
.sym 23501 $false
.sym 23502 $auto$alumacc.cc:470:replace_alu$57683.C[1]
.sym 23503 $false
.sym 23504 $false
.sym 23505 $auto$alumacc.cc:470:replace_alu$57683.C[2]
.sym 23507 $false
.sym 23508 $auto$alumacc.cc:483:replace_alu$57684[1]
.sym 23510 $auto$alumacc.cc:470:replace_alu$57683.C[3]
.sym 23511 $false
.sym 23512 $false
.sym 23513 $auto$alumacc.cc:483:replace_alu$57684[2]
.sym 23514 $auto$alumacc.cc:470:replace_alu$57683.C[2]
.sym 23515 $auto$alumacc.cc:470:replace_alu$57683.C[4]
.sym 23516 $false
.sym 23517 $false
.sym 23518 $auto$alumacc.cc:483:replace_alu$57684[3]
.sym 23519 $auto$alumacc.cc:470:replace_alu$57683.C[3]
.sym 23520 $auto$alumacc.cc:470:replace_alu$57683.C[5]
.sym 23521 $false
.sym 23522 $false
.sym 23523 $auto$alumacc.cc:483:replace_alu$57684[4]
.sym 23524 $auto$alumacc.cc:470:replace_alu$57683.C[4]
.sym 23525 $auto$alumacc.cc:470:replace_alu$57683.C[6]
.sym 23526 $false
.sym 23527 $false
.sym 23528 $auto$alumacc.cc:483:replace_alu$57684[5]
.sym 23529 $auto$alumacc.cc:470:replace_alu$57683.C[5]
.sym 23530 $auto$alumacc.cc:470:replace_alu$57683.C[7]$2
.sym 23531 $false
.sym 23532 $false
.sym 23533 $auto$alumacc.cc:483:replace_alu$57684[6]
.sym 23534 $auto$alumacc.cc:470:replace_alu$57683.C[6]
.sym 23539 $auto$alumacc.cc:470:replace_alu$57683.C[7]$2
.sym 23588 $false
.sym 23590 KEYBOARD.ROWS_EN[4]
.sym 23591 $false
.sym 23593 KEYBOARD.ROWS_EN[5]
.sym 23672 $true
.sym 23709 KEYBOARD.kbd_code_hid[3]$2
.sym 23710 $false
.sym 23711 KEYBOARD.kbd_code_hid[3]
.sym 23712 $false
.sym 23713 $false
.sym 23714 $auto$alumacc.cc:484:replace_alu$57558[4]
.sym 23716 KEYBOARD.kbd_code_hid[4]
.sym 23717 $true$2
.sym 23719 $auto$alumacc.cc:484:replace_alu$57558[5]
.sym 23721 KEYBOARD.kbd_code_hid[5]
.sym 23722 $false
.sym 23724 $auto$alumacc.cc:484:replace_alu$57558[6]
.sym 23726 KEYBOARD.kbd_code_hid[6]
.sym 23727 $false
.sym 23729 $auto$alumacc.cc:484:replace_alu$57558[7]$2
.sym 23731 KEYBOARD.kbd_code_hid[7]
.sym 23732 $false
.sym 23738 $auto$alumacc.cc:484:replace_alu$57558[7]$2
.sym 23905 $auto$wreduce.cc:310:run$57529[3]$2
.sym 23906 $false
.sym 23907 $false
.sym 23908 $false
.sym 24018 $false
.sym 24019 $true$2
.sym 24020 $false
.sym 24021 $false
.sym 24023 $techmap\KEYBOARD.$procmux$5651_Y[5]
.sym 24024 $false
.sym 24025 $false
.sym 24026 $false
.sym 24028 $techmap\KEYBOARD.$procmux$5651_Y[0]
.sym 24029 $false
.sym 24030 $false
.sym 24031 $false
.sym 24038 $techmap\KEYBOARD.$procmux$5651_Y[4]
.sym 24039 $false
.sym 24040 $false
.sym 24041 $false
.sym 24057 $auto$dff2dffe.cc:175:make_patterns_logic$88296
.sym 24058 CLK$2$2
.sym 24059 $logic_not$top.v:66$10_Y$2
.sym 24166 $techmap\KEYBOARD.$procmux$5651_Y[7]
.sym 24167 $false
.sym 24168 $false
.sym 24169 $false
.sym 24171 $techmap\KEYBOARD.$procmux$5651_Y[2]
.sym 24172 $false
.sym 24173 $false
.sym 24174 $false
.sym 24176 $techmap\KEYBOARD.$procmux$5651_Y[4]
.sym 24177 $false
.sym 24178 $false
.sym 24179 $false
.sym 24181 $techmap\KEYBOARD.$procmux$5651_Y[1]
.sym 24182 $false
.sym 24183 $false
.sym 24184 $false
.sym 24186 $techmap\KEYBOARD.$procmux$5651_Y[6]
.sym 24187 $false
.sym 24188 $false
.sym 24189 $false
.sym 24191 $techmap\KEYBOARD.$procmux$5651_Y[0]
.sym 24192 $false
.sym 24193 $false
.sym 24194 $false
.sym 24196 $techmap\KEYBOARD.$procmux$5651_Y[3]
.sym 24197 $false
.sym 24198 $false
.sym 24199 $false
.sym 24201 $techmap\KEYBOARD.$procmux$5651_Y[5]
.sym 24202 $false
.sym 24203 $false
.sym 24204 $false
.sym 24205 $auto$dff2dffe.cc:175:make_patterns_logic$90769
.sym 24206 CLK$2$2
.sym 24207 $logic_not$top.v:66$10_Y$2
.sym 24314 I2C.FLT_SDA.counter[0]
.sym 24315 I2C.FLT_SDA.counter[1]
.sym 24316 I2C.FLT_SDA.counter[2]
.sym 24317 $false
.sym 24319 $abc$92916$n927
.sym 24320 $auto$wreduce.cc:310:run$57521[0]
.sym 24321 $false
.sym 24322 $false
.sym 24324 $techmap\I2C.FLT_SDA.$procmux$1018_Y[1]
.sym 24325 $auto$wreduce.cc:310:run$57521[2]
.sym 24326 I2C.FLT_SDA.out
.sym 24327 I2C.SDAF
.sym 24329 $techmap\I2C.FLT_SDA.$procmux$1018_Y[0]
.sym 24330 $abc$92916$n928
.sym 24331 $false
.sym 24332 $false
.sym 24334 $abc$92916$n927
.sym 24335 I2C.FLT_SDA.out
.sym 24336 I2C.SDAF
.sym 24337 $false
.sym 24339 $abc$92916$n927
.sym 24340 $auto$wreduce.cc:310:run$57521[2]
.sym 24341 $false
.sym 24342 $false
.sym 24344 $techmap\I2C.FLT_SDA.$procmux$1018_Y[1]
.sym 24345 $false
.sym 24346 $false
.sym 24347 $false
.sym 24349 $techmap\I2C.FLT_SDA.$procmux$1018_Y[0]
.sym 24350 $false
.sym 24351 $false
.sym 24352 $false
.sym 24353 $auto$dff2dffe.cc:158:make_patterns_logic$92230
.sym 24354 CLK$2$2
.sym 24355 $logic_not$top.v:66$10_Y$2
.sym 24462 I2C.FLT_SDA.counter[0]
.sym 24463 I2C.FLT_SDA.counter[1]
.sym 24464 $false
.sym 24465 $false
.sym 24467 $false
.sym 24468 I2C.FLT_SDA.counter[2]
.sym 24469 $true$2
.sym 24470 $auto$alumacc.cc:484:replace_alu$57694[1]
.sym 24472 $techmap$techmap\KEYBOARD.$shl$matrix_kbd.v:51$296.$procmux$66087_Y[15]
.sym 24473 $false
.sym 24474 $false
.sym 24475 $false
.sym 24477 $techmap$techmap\KEYBOARD.$shl$matrix_kbd.v:51$296.$procmux$66087_Y[11]
.sym 24478 $false
.sym 24479 $false
.sym 24480 $false
.sym 24492 $techmap$techmap\KEYBOARD.$shl$matrix_kbd.v:51$296.$procmux$66087_Y[10]
.sym 24493 $false
.sym 24494 $false
.sym 24495 $false
.sym 24501 $auto$dff2dffe.cc:175:make_patterns_logic$91425$2
.sym 24502 CLK$2$2
.sym 24503 $auto$rtlil.cc:1692:NotGate$92861
.sym 24506 SCL$2
.sym 24610 $auto$rtlil.cc:1692:NotGate$92753
.sym 24611 KEYBOARD.kbd_code_hid[2]
.sym 24612 $false
.sym 24613 $false
.sym 24615 KEYBOARD.kbd_code_hid[3]
.sym 24616 KEYBOARD.kbd_code_hid[2]
.sym 24617 KEYBOARD.report[4][2]
.sym 24618 KEYBOARD.report[4][3]
.sym 24625 KEYBOARD.kbd_code_hid[1]
.sym 24626 KEYBOARD.kbd_code_hid[0]
.sym 24627 KEYBOARD.report[4][0]
.sym 24628 KEYBOARD.report[4][1]
.sym 24630 $abc$92916$n891
.sym 24631 $abc$92916$n892
.sym 24632 $abc$92916$n893
.sym 24633 $false
.sym 24635 $auto$rtlil.cc:1692:NotGate$92753
.sym 24636 KEYBOARD.kbd_code_hid[7]
.sym 24637 $false
.sym 24638 $false
.sym 24640 KEYBOARD.kbd_code_hid[4]
.sym 24641 KEYBOARD.kbd_code_hid[5]
.sym 24642 KEYBOARD.report[4][4]
.sym 24643 KEYBOARD.report[4][5]
.sym 24645 I2C.FLT_SDA.out
.sym 24646 $false
.sym 24647 $false
.sym 24648 $false
.sym 24649 $auto$dff2dffe.cc:175:make_patterns_logic$84651
.sym 24650 CLK$2$2
.sym 24651 $false
.sym 24652 I2C.SDA_IN
.sym 24758 $auto$rtlil.cc:1692:NotGate$92753
.sym 24759 KEYBOARD.kbd_code_hid[6]
.sym 24760 $false
.sym 24761 $false
.sym 24763 $auto$wreduce.cc:310:run$57529[1]
.sym 24764 $auto$wreduce.cc:310:run$57529[0]
.sym 24765 $auto$wreduce.cc:310:run$57529[2]
.sym 24766 $false
.sym 24768 KEYBOARD.row_counter[0]
.sym 24769 $auto$wreduce.cc:310:run$57529[0]
.sym 24770 $auto$rtlil.cc:1692:NotGate$92893$2
.sym 24771 $false
.sym 24773 $auto$rtlil.cc:1692:NotGate$92893$2
.sym 24774 RESET$2
.sym 24775 $false
.sym 24776 $false
.sym 24778 $auto$wreduce.cc:310:run$57529[1]
.sym 24779 $auto$wreduce.cc:310:run$57529[0]
.sym 24780 $auto$wreduce.cc:310:run$57529[2]
.sym 24781 $false
.sym 24783 $auto$wreduce.cc:310:run$57529[1]
.sym 24784 $false
.sym 24785 $false
.sym 24786 $false
.sym 24793 $auto$wreduce.cc:310:run$57529[2]
.sym 24794 $false
.sym 24795 $false
.sym 24796 $false
.sym 24797 $auto$dff2dffe.cc:175:make_patterns_logic$91425$2
.sym 24798 CLK$2$2
.sym 24799 $false
.sym 24911 RESET$2
.sym 24912 $false
.sym 24913 $false
.sym 24914 $false
.sym 24916 $techmap\KEYBOARD.$procmux$5651_Y[2]
.sym 24917 $false
.sym 24918 $false
.sym 24919 $false
.sym 24926 $techmap\KEYBOARD.$procmux$5651_Y[1]
.sym 24927 $false
.sym 24928 $false
.sym 24929 $false
.sym 24931 $techmap\KEYBOARD.$procmux$5651_Y[6]
.sym 24932 $false
.sym 24933 $false
.sym 24934 $false
.sym 24941 $techmap\KEYBOARD.$procmux$5651_Y[3]
.sym 24942 $false
.sym 24943 $false
.sym 24944 $false
.sym 24945 $auto$dff2dffe.cc:175:make_patterns_logic$88296
.sym 24946 CLK$2$2
.sym 24947 $logic_not$top.v:66$10_Y$2
.sym 25054 $auto$wreduce.cc:310:run$57529[1]
.sym 25055 $auto$wreduce.cc:310:run$57529[0]
.sym 25056 $auto$wreduce.cc:310:run$57529[2]
.sym 25057 $false
.sym 25059 $auto$wreduce.cc:310:run$57529[1]
.sym 25060 $auto$wreduce.cc:310:run$57529[0]
.sym 25061 $auto$wreduce.cc:310:run$57529[2]
.sym 25062 $false
.sym 25064 $false
.sym 25065 $true$2
.sym 25066 KEYBOARD.row_counter[0]
.sym 25067 $false
.sym 25074 $auto$wreduce.cc:310:run$57529[1]
.sym 25075 $auto$wreduce.cc:310:run$57529[0]
.sym 25076 $auto$wreduce.cc:310:run$57529[2]
.sym 25077 $false
.sym 25079 $auto$wreduce.cc:310:run$57529[1]
.sym 25080 $auto$wreduce.cc:310:run$57529[0]
.sym 25081 $auto$wreduce.cc:310:run$57529[2]
.sym 25082 $false
.sym 25084 $techmap$techmap\KEYBOARD.$shl$matrix_kbd.v:51$296.$procmux$66087_Y[9]
.sym 25085 $false
.sym 25086 $false
.sym 25087 $false
.sym 25089 $techmap$techmap\KEYBOARD.$shl$matrix_kbd.v:51$296.$procmux$66087_Y[12]
.sym 25090 $false
.sym 25091 $false
.sym 25092 $false
.sym 25093 $auto$dff2dffe.cc:175:make_patterns_logic$91425$2
.sym 25094 CLK$2$2
.sym 25095 $auto$rtlil.cc:1692:NotGate$92861
.sym 25164 $true
.sym 25201 $auto$alumacc.cc:483:replace_alu$57552[0]$3
.sym 25202 $false
.sym 25203 $auto$alumacc.cc:483:replace_alu$57552[0]
.sym 25204 $false
.sym 25205 $false
.sym 25206 $auto$alumacc.cc:484:replace_alu$57733[1]$2
.sym 25208 $false
.sym 25209 $auto$alumacc.cc:483:replace_alu$57552[1]
.sym 25215 $auto$alumacc.cc:484:replace_alu$57733[1]$2
.sym 25217 I2C.received_byte[1]
.sym 25218 $false
.sym 25219 $false
.sym 25220 $false
.sym 25222 $abc$92916$n818
.sym 25223 $abc$92916$n825
.sym 25224 $auto$simplemap.cc:250:simplemap_eqne$60443[0]
.sym 25225 $false
.sym 25227 $abc$92916$n818
.sym 25228 $abc$92916$n825
.sym 25229 $auto$simplemap.cc:250:simplemap_eqne$60443[0]
.sym 25230 $false
.sym 25312 $true
.sym 25349 $auto$alumacc.cc:483:replace_alu$57618[1]$3
.sym 25350 $false
.sym 25351 $auto$alumacc.cc:483:replace_alu$57618[1]
.sym 25352 $false
.sym 25353 $false
.sym 25354 $auto$alumacc.cc:484:replace_alu$57642[2]
.sym 25356 $true$2
.sym 25357 $auto$alumacc.cc:483:replace_alu$57618[2]
.sym 25359 $auto$alumacc.cc:484:replace_alu$57642[3]
.sym 25361 $false
.sym 25362 $auto$alumacc.cc:483:replace_alu$57618[3]
.sym 25364 $auto$alumacc.cc:484:replace_alu$57642[4]
.sym 25366 $false
.sym 25367 $auto$alumacc.cc:483:replace_alu$57618[4]
.sym 25369 $auto$alumacc.cc:484:replace_alu$57642[5]
.sym 25371 $false
.sym 25372 $auto$alumacc.cc:483:replace_alu$57618[5]
.sym 25374 $auto$alumacc.cc:484:replace_alu$57642[6]
.sym 25376 $false
.sym 25377 $auto$alumacc.cc:483:replace_alu$57618[6]
.sym 25379 $auto$alumacc.cc:484:replace_alu$57642[7]$2
.sym 25381 $false
.sym 25382 $auto$alumacc.cc:483:replace_alu$57618[7]
.sym 25388 $auto$alumacc.cc:484:replace_alu$57642[7]$2
.sym 25498 $abc$92916$n818
.sym 25499 $abc$92916$n825
.sym 25500 $auto$simplemap.cc:250:simplemap_eqne$60443[0]
.sym 25501 $false
.sym 25503 INT
.sym 25504 $false
.sym 25505 $false
.sym 25506 $false
.sym 25513 I2C.FLT_SDA.out
.sym 25514 $false
.sym 25515 $false
.sym 25516 $false
.sym 25537 $auto$dff2dffe.cc:175:make_patterns_logic$84718
.sym 25538 CLK$2$2
.sym 25539 $false
.sym 25608 $true
.sym 25645 $techmap$auto$alumacc.cc:470:replace_alu$57683.$not$/usr/bin/../share/yosys/ice40/arith_map.v:42$58930_Y[1]$2
.sym 25646 $false
.sym 25647 $techmap$auto$alumacc.cc:470:replace_alu$57683.$not$/usr/bin/../share/yosys/ice40/arith_map.v:42$58930_Y[1]
.sym 25648 $false
.sym 25649 $false
.sym 25650 $auto$alumacc.cc:484:replace_alu$57680[2]
.sym 25652 $false
.sym 25653 $techmap$auto$alumacc.cc:470:replace_alu$57683.$not$/usr/bin/../share/yosys/ice40/arith_map.v:42$58930_Y[2]
.sym 25655 $auto$alumacc.cc:484:replace_alu$57680[3]
.sym 25657 $false
.sym 25658 $techmap$auto$alumacc.cc:470:replace_alu$57683.$not$/usr/bin/../share/yosys/ice40/arith_map.v:42$58930_Y[3]
.sym 25660 $auto$alumacc.cc:484:replace_alu$57680[4]
.sym 25662 $false
.sym 25663 $techmap$auto$alumacc.cc:470:replace_alu$57683.$not$/usr/bin/../share/yosys/ice40/arith_map.v:42$58930_Y[4]
.sym 25665 $auto$alumacc.cc:484:replace_alu$57680[5]
.sym 25667 $false
.sym 25668 $techmap$auto$alumacc.cc:470:replace_alu$57683.$not$/usr/bin/../share/yosys/ice40/arith_map.v:42$58930_Y[5]
.sym 25670 $auto$alumacc.cc:484:replace_alu$57680[6]
.sym 25672 $false
.sym 25673 $techmap$auto$alumacc.cc:470:replace_alu$57683.$not$/usr/bin/../share/yosys/ice40/arith_map.v:42$58930_Y[6]
.sym 25675 $auto$alumacc.cc:484:replace_alu$57680[7]$2
.sym 25677 $false
.sym 25678 $techmap$auto$alumacc.cc:470:replace_alu$57683.$not$/usr/bin/../share/yosys/ice40/arith_map.v:42$58930_Y[7]
.sym 25684 $auto$alumacc.cc:484:replace_alu$57680[7]$2
.sym 25794 $auto$alumacc.cc:483:replace_alu$57684[3]
.sym 25795 $false
.sym 25796 $false
.sym 25797 $false
.sym 25799 $techmap$techmap\KEYBOARD.$shl$matrix_kbd.v:51$296.$procmux$66087_Y[12]
.sym 25800 $false
.sym 25801 $false
.sym 25802 $false
.sym 25809 $techmap$techmap\KEYBOARD.$shl$matrix_kbd.v:51$296.$procmux$66087_Y[11]
.sym 25810 $false
.sym 25811 $false
.sym 25812 $false
.sym 25814 $techmap$techmap\KEYBOARD.$shl$matrix_kbd.v:51$296.$procmux$66087_Y[14]
.sym 25815 $false
.sym 25816 $false
.sym 25817 $false
.sym 25819 $techmap$techmap\KEYBOARD.$shl$matrix_kbd.v:51$296.$procmux$66087_Y[15]
.sym 25820 $false
.sym 25821 $false
.sym 25822 $false
.sym 25829 $techmap$techmap\KEYBOARD.$shl$matrix_kbd.v:51$296.$procmux$66087_Y[9]
.sym 25830 $false
.sym 25831 $false
.sym 25832 $false
.sym 25833 $auto$dff2dffe.cc:175:make_patterns_logic$91425$2
.sym 25834 CLK$2$2
.sym 25835 $auto$wreduce.cc:310:run$57529[3]$2
.sym 26069 $false
.sym 26071 KEYBOARD.ROWS_EN[6]
.sym 26072 $false
.sym 26074 KEYBOARD.ROWS_EN[7]
.sym 26163 $false
.sym 26165 KEYBOARD.ROWS_EN[8]
.sym 26190 $false
.sym 26192 KEYBOARD.ROWS_EN[9]
.sym 26193 $false
.sym 26195 KEYBOARD.ROWS_EN[10]
.sym 26250 $false
.sym 26252 KEYBOARD.ROWS_EN[11]
.sym 26253 $false
.sym 26255 KEYBOARD.ROWS_EN[12]
.sym 26280 INT
.sym 26309 $auto$dff2dffe.cc:175:make_patterns_logic$91425
.sym 26310 $false
.sym 26312 I2C.SDA_DIR
.sym 26339 $logic_not$top.v:66$10_Y
.sym 26343 I2C_TRANS
.sym 26399 LED4$2
.sym 26402 LED3$2
.sym 26429 LED2$2
.sym 26432 LED1$2