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1742 lines
104 KiB
1742 lines
104 KiB
# Generated by Yosys 0.8+147 (git sha1 266511b2, clang 6.0.0-1ubuntu2 -fPIC -Os)
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.model top
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.inputs CLK I2C_SCL I2C_SDA INTERRUPT KBD_RC[0] KBD_RC[1] KBD_RC[2] KBD_RC[3] KBD_RC[4] KBD_RC[5] KBD_RC[6] KBD_RC[7] KBD_RC[8] KBD_RC[9] KBD_RC[10] KBD_RC[11] KBD_RC[12] KBD_RC[13] KBD_RC[14] KBD_RC[15] KBD_RC[16] KBD_RC[17] KBD_RC[18] KBD_RC[19] KBD_RC[20] KBD_RC[21] KBD_RC[22] KBD_RC[23] KBD_RC[24] KBD_RC[25] KBD_RC[26] KBD_RC[27] KBD_RC[28] KBD_RC[29] KBD_RC[30] KBD_RC[31] KBD_RC[32] KBD_RC[33]
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.outputs DBG_LED[0] DBG_LED[1] DBG_LED[2] DBG_TX I2C_SDA INTERRUPT KBD_RC[0] KBD_RC[1] KBD_RC[2] KBD_RC[3] KBD_RC[4] KBD_RC[5] KBD_RC[6] KBD_RC[7] KBD_RC[8] KBD_RC[9] KBD_RC[10] KBD_RC[11] KBD_RC[12] KBD_RC[13] KBD_RC[14] KBD_RC[15] KBD_RC[16] KBD_RC[17] KBD_RC[18] KBD_RC[19] KBD_RC[20] KBD_RC[21] KBD_RC[22] KBD_RC[23] KBD_RC[24] KBD_RC[25] KBD_RC[26] KBD_RC[27] KBD_RC[28] KBD_RC[29] KBD_RC[30] KBD_RC[31] KBD_RC[32] KBD_RC[33]
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.names $false
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.names $true
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1
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.names $undef
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.gate SB_LUT4 I0=$abc$4874$n300 I1=$abc$4874$n308_1 I2=$abc$4874$n310 I3=$false O=$abc$4874$n1
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:48"
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.param LUT_INIT 10111111
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.gate SB_LUT4 I0=$abc$4874$n290 I1=$abc$4874$n305_1 I2=$abc$4874$n307_1 I3=$abc$4874$n453 O=$abc$4874$n300
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
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.param LUT_INIT 1000000011111111
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.gate SB_LUT4 I0=ms_counter[5] I1=$abc$4874$n288 I2=$2\ms_counter[5:0][4] I3=$abc$4874$n291 O=$abc$4874$n290
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
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.param LUT_INIT 0000110000001010
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.gate SB_LUT4 I0=$abc$4874$n292 I1=$abc$4874$n300_1 I2=$false I3=$false O=$abc$4874$n291
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
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.param LUT_INIT 1000
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.gate SB_LUT4 I0=$abc$4874$n293 I1=tact_counter_2ms[1] I2=tact_counter_2ms[0] I3=$false O=$abc$4874$n292
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:48"
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.param LUT_INIT 10000000
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.gate SB_LUT4 I0=tact_counter_2ms[8] I1=tact_counter_2ms[9] I2=tact_counter_2ms[10] I3=tact_counter_2ms[12] O=$abc$4874$n293
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
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.param LUT_INIT 0000000000000001
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.gate SB_LUT4 I0=$abc$4874$n287 I1=ms_counter[4] I2=$abc$4874$n292 I3=$abc$4874$n300_1 O=$2\ms_counter[5:0][4]
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
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.param LUT_INIT 1010110011001100
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.gate SB_LUT4 I0=$abc$4874$n301 I1=$abc$4874$n302 I2=$abc$4874$n303_1 I3=$abc$4874$n304 O=$abc$4874$n300_1
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
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.param LUT_INIT 1000000000000000
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.gate SB_LUT4 I0=tact_counter_2ms[2] I1=tact_counter_2ms[3] I2=tact_counter_2ms[4] I3=tact_counter_2ms[5] O=$abc$4874$n301
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
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.param LUT_INIT 1000000000000000
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.gate SB_LUT4 I0=tact_counter_2ms[13] I1=tact_counter_2ms[14] I2=tact_counter_2ms[15] I3=tact_counter_2ms[17] O=$abc$4874$n302
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
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.param LUT_INIT 0000000000000001
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.gate SB_LUT4 I0=tact_counter_2ms[18] I1=tact_counter_2ms[19] I2=tact_counter_2ms[20] I3=tact_counter_2ms[21] O=$abc$4874$n303_1
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
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.param LUT_INIT 1000000000000000
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.gate SB_LUT4 I0=tact_counter_2ms[6] I1=tact_counter_2ms[7] I2=tact_counter_2ms[11] I3=tact_counter_2ms[16] O=$abc$4874$n304
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
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.param LUT_INIT 1000000000000000
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.gate SB_LUT4 I0=ms_counter[2] I1=$abc$4874$n284 I2=$abc$4874$n291 I3=$abc$4874$n15 O=$abc$4874$n305_1
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
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.param LUT_INIT 0011010100000000
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.gate SB_LUT4 I0=$abc$4874$n285 I1=ms_counter[3] I2=$abc$4874$n292 I3=$abc$4874$n300_1 O=$abc$4874$n15
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
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.param LUT_INIT 0101001100110011
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.gate SB_LUT4 I0=$abc$4874$n281 I1=ms_counter[1] I2=ms_counter[0] I3=$abc$4874$n291 O=$abc$4874$n307_1
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
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.param LUT_INIT 1000001000110000
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.gate SB_LUT4 I0=$2\ms_counter[5:0][4] I1=$abc$4874$n459 I2=$false I3=$false O=$abc$4874$n308_1
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
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.param LUT_INIT 0100
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.gate SB_LUT4 I0=ms_counter[5] I1=$abc$4874$n288 I2=$abc$4874$n291 I3=$false O=$abc$4874$n459
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:48"
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.param LUT_INIT 00110101
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.gate SB_LUT4 I0=$2\ms_counter[5:0][0] I1=$abc$4874$n18 I2=$abc$4874$n305_1 I3=$false O=$abc$4874$n310
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:48"
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.param LUT_INIT 01000000
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.gate SB_LUT4 I0=$abc$4874$n291 I1=ms_counter[0] I2=ms_counter[1] I3=$false O=$abc$4874$n18
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:48"
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.param LUT_INIT 10000111
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.gate SB_LUT4 I0=ms_counter[0] I1=$abc$4874$n281 I2=$abc$4874$n291 I3=$false O=$2\ms_counter[5:0][0]
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:48"
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.param LUT_INIT 11001010
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.gate SB_LUT4 I0=$abc$4874$n314 I1=$abc$4874$n318_1 I2=$abc$4874$n320_1 I3=UART.tx_activity O=$abc$4874$n3
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
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.param LUT_INIT 0000000111111111
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.gate SB_LUT4 I0=$abc$4874$n317 I1=UART_TX_DATA[2] I2=$abc$4874$n427 I3=$abc$4874$n315_1 O=$abc$4874$n314
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
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.param LUT_INIT 0000110000001010
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.gate SB_LUT4 I0=$abc$4874$n446 I1=$abc$4874$n431 I2=$false I3=$false O=$abc$4874$n315_1
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
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.param LUT_INIT 1001
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.gate SB_LUT4 I0=UART.tx_bit_counter[0] I1=UART.tx_bit_counter[1] I2=$false I3=$false O=$abc$4874$n446
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
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.param LUT_INIT 0110
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.gate SB_LUT4 I0=UART_TX_DATA[4] I1=UART_TX_DATA[0] I2=$abc$4874$n420 I3=$false O=$abc$4874$n317
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:48"
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.param LUT_INIT 10101100
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.gate SB_LUT4 I0=$abc$4874$n319 I1=UART_TX_DATA[3] I2=$abc$4874$n315_1 I3=$abc$4874$n427 O=$abc$4874$n318_1
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
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.param LUT_INIT 1100010100000000
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.gate SB_LUT4 I0=UART_TX_DATA[1] I1=UART_TX_DATA[5] I2=$abc$4874$n420 I3=$false O=$abc$4874$n319
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:48"
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.param LUT_INIT 00110101
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.gate SB_LUT4 I0=$abc$4874$n431 I1=$abc$4874$n434 I2=$abc$4874$n436 I3=$abc$4874$n446 O=$abc$4874$n320_1
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
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.param LUT_INIT 0000000100000000
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.gate SB_LUT4 I0=rststate[3] I1=rststate[2] I2=rststate[1] I3=rststate[0] O=RESET
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
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.param LUT_INIT 1000000000000000
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.gate SB_LUT4 I0=ms_counter[2] I1=$abc$4874$n284 I2=$abc$4874$n291 I3=$false O=$abc$4874$n16
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:48"
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.param LUT_INIT 00110101
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.gate SB_LUT4 I0=$abc$4874$n324 I1=$abc$4874$n509_1 I2=$abc$4874$n336 I3=$false O=$abc$4874$n35
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:48"
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.param LUT_INIT 10000000
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.gate SB_LUT4 I0=$abc$4874$n325_1 I1=$abc$4874$n290 I2=RESET I3=$false O=$abc$4874$n324
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:48"
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.param LUT_INIT 10000000
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.gate SB_LUT4 I0=$abc$4874$n18 I1=$2\ms_counter[5:0][0] I2=$abc$4874$n305_1 I3=$false O=$abc$4874$n325_1
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:48"
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.param LUT_INIT 00010000
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.gate SB_LUT4 I0=$abc$4874$n291 I1=$abc$4874$n359 I2=$false I3=$false O=$2\tact_counter_2ms[21:0][6]
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
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.param LUT_INIT 0100
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.gate SB_LUT4 I0=$abc$4874$n291 I1=$abc$4874$n360 I2=$false I3=$false O=$2\tact_counter_2ms[21:0][7]
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
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.param LUT_INIT 0100
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.gate SB_LUT4 I0=$abc$4874$n291 I1=$abc$4874$n355 I2=$false I3=$false O=$2\tact_counter_2ms[21:0][2]
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
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.param LUT_INIT 0100
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.gate SB_LUT4 I0=$abc$4874$n291 I1=$abc$4874$n353 I2=$false I3=$false O=$2\tact_counter_2ms[21:0][0]
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
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.param LUT_INIT 0100
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.gate SB_LUT4 I0=$abc$4874$n291 I1=$abc$4874$n356 I2=$false I3=$false O=$2\tact_counter_2ms[21:0][3]
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
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.param LUT_INIT 0100
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.gate SB_LUT4 I0=tact_counter_2ms[1] I1=tact_counter_2ms[0] I2=$false I3=$false O=$2\tact_counter_2ms[21:0][1]
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
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.param LUT_INIT 0110
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.gate SB_LUT4 I0=$2\tact_counter_2ms[21:0][8] I1=$2\tact_counter_2ms[21:0][9] I2=$2\tact_counter_2ms[21:0][10] I3=$false O=$abc$4874$n336
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:48"
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.param LUT_INIT 00010000
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.gate SB_LUT4 I0=$abc$4874$n291 I1=$abc$4874$n363 I2=$false I3=$false O=$2\tact_counter_2ms[21:0][10]
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
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.param LUT_INIT 0100
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.gate SB_LUT4 I0=$abc$4874$n291 I1=$abc$4874$n361 I2=$false I3=$false O=$2\tact_counter_2ms[21:0][8]
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.attr module_not_derived 00000000000000000000000000000001
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.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
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.param LUT_INIT 0100
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.gate SB_LUT4 I0=$abc$4874$n291 I1=$abc$4874$n362 I2=$false I3=$false O=$2\tact_counter_2ms[21:0][9]
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.attr module_not_derived 00000000000000000000000000000001
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|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
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.param LUT_INIT 0100
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.gate SB_LUT4 I0=com_len[2] I1=com_len[0] I2=$abc$4874$n456 I3=$abc$4874$n379_1 O=$abc$4874$n37
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.attr module_not_derived 00000000000000000000000000000001
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|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
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.param LUT_INIT 1011111100000000
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|
.gate SB_LUT4 I0=$abc$4874$n342_1 I1=com_len[1] I2=$false I3=$false O=$abc$4874$n456
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|
.attr module_not_derived 00000000000000000000000000000001
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|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 0001
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|
.gate SB_LUT4 I0=$abc$4874$n300 I1=$abc$4874$n343_1 I2=$false I3=$false O=$abc$4874$n342_1
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|
.attr module_not_derived 00000000000000000000000000000001
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|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 0100
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|
.gate SB_LUT4 I0=$abc$4874$n353_1 I1=$abc$4874$n345_1 I2=$abc$4874$n352_1 I3=$abc$4874$n344_1 O=$abc$4874$n343_1
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|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 0100000000000000
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|
.gate SB_LUT4 I0=$abc$4874$n363 I1=$abc$4874$n361 I2=$abc$4874$n362 I3=$abc$4874$n291 O=$abc$4874$n344_1
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|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 1111111100000001
|
|
.gate SB_LUT4 I0=$abc$4874$n346_1 I1=$abc$4874$n355 I2=$abc$4874$n379 I3=$false O=$abc$4874$n345_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:48"
|
|
.param LUT_INIT 10000000
|
|
.gate SB_LUT4 I0=$abc$4874$n347_1 I1=$abc$4874$n349_1 I2=$abc$4874$n350_1 I3=$abc$4874$n351_1 O=$abc$4874$n346_1
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|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
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.param LUT_INIT 1000000000000000
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|
.gate SB_LUT4 I0=com_len[2] I1=com_len[0] I2=$abc$4874$n348_1 I3=$false O=$abc$4874$n347_1
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|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:48"
|
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.param LUT_INIT 01000000
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|
.gate SB_LUT4 I0=com_len[1] I1=$abc$4874$n353 I2=$abc$4874$n356 I3=$abc$4874$n357 O=$abc$4874$n348_1
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.attr module_not_derived 00000000000000000000000000000001
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|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
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.param LUT_INIT 0100000000000000
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.gate SB_LUT4 I0=$2\tact_counter_2ms[21:0][1] I1=$abc$4874$n373 I2=$abc$4874$n375 I3=$abc$4874$n377 O=$abc$4874$n349_1
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|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
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|
.param LUT_INIT 1000000000000000
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|
.gate SB_LUT4 I0=$abc$4874$n368 I1=$abc$4874$n369 I2=$abc$4874$n372 I3=$abc$4874$n370 O=$abc$4874$n350_1
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|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
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.param LUT_INIT 0000000100000000
|
|
.gate SB_LUT4 I0=$abc$4874$n367 I1=$abc$4874$n359 I2=$abc$4874$n360 I3=$abc$4874$n358 O=$abc$4874$n351_1
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|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 0100000000000000
|
|
.gate SB_LUT4 I0=$abc$4874$n366 I1=$abc$4874$n364 I2=$false I3=$false O=$abc$4874$n352_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 0100
|
|
.gate SB_LUT4 I0=$abc$4874$n354 I1=$abc$4874$n363_1 I2=$false I3=$false O=$abc$4874$n353_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 1000
|
|
.gate SB_LUT4 I0=$abc$4874$n355_1 I1=$abc$4874$n358_1 I2=$abc$4874$n361_1 I3=$abc$4874$n362_1 O=$abc$4874$n354
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 1000000000000000
|
|
.gate SB_LUT4 I0=$abc$4874$n356_1 I1=$abc$4874$n357_1 I2=$false I3=$false O=$abc$4874$n355_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 1000
|
|
.gate SB_LUT4 I0=KBD_RC_IN[17] I1=KBD_RC_EN[17] I2=KBD_RC_IN[16] I3=KBD_RC_EN[16] O=$abc$4874$n356_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 1110111011100000
|
|
.gate SB_LUT4 I0=KBD_RC_IN[15] I1=KBD_RC_EN[15] I2=KBD_RC_IN[13] I3=KBD_RC_EN[13] O=$abc$4874$n357_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 1110111011100000
|
|
.gate SB_LUT4 I0=$abc$4874$n359_1 I1=$abc$4874$n360_1 I2=$false I3=$false O=$abc$4874$n358_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 1000
|
|
.gate SB_LUT4 I0=KBD_RC_IN[12] I1=KBD_RC_EN[12] I2=KBD_RC_IN[8] I3=KBD_RC_EN[8] O=$abc$4874$n359_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 1110111011100000
|
|
.gate SB_LUT4 I0=KBD_RC_IN[14] I1=KBD_RC_EN[14] I2=KBD_RC_IN[5] I3=KBD_RC_EN[5] O=$abc$4874$n360_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 1110111011100000
|
|
.gate SB_LUT4 I0=KBD_RC_IN[6] I1=KBD_RC_EN[6] I2=KBD_RC_IN[1] I3=KBD_RC_EN[1] O=$abc$4874$n361_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 1110111011100000
|
|
.gate SB_LUT4 I0=KBD_RC_IN[9] I1=KBD_RC_EN[9] I2=KBD_RC_IN[3] I3=KBD_RC_EN[3] O=$abc$4874$n362_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 1110111011100000
|
|
.gate SB_LUT4 I0=$abc$4874$n364_1 I1=$abc$4874$n368_1 I2=$abc$4874$n373_1 I3=$abc$4874$n376_1 O=$abc$4874$n363_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 1000000000000000
|
|
.gate SB_LUT4 I0=$abc$4874$n365_1 I1=$abc$4874$n366_1 I2=$abc$4874$n367_1 I3=$false O=$abc$4874$n364_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:48"
|
|
.param LUT_INIT 10000000
|
|
.gate SB_LUT4 I0=KBD_RC_IN[32] I1=KBD_RC_EN[32] I2=KBD_RC_IN[33] I3=KBD_RC_EN[33] O=$abc$4874$n365_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 0000000000000001
|
|
.gate SB_LUT4 I0=KBD_RC_IN[30] I1=KBD_RC_EN[30] I2=KBD_RC_IN[31] I3=KBD_RC_EN[31] O=$abc$4874$n366_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 0000000000000001
|
|
.gate SB_LUT4 I0=KBD_RC_IN[28] I1=KBD_RC_EN[28] I2=KBD_RC_IN[29] I3=KBD_RC_EN[29] O=$abc$4874$n367_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 0000000000000001
|
|
.gate SB_LUT4 I0=$abc$4874$n369_1 I1=$abc$4874$n370_1 I2=$abc$4874$n371_1 I3=$abc$4874$n372_1 O=$abc$4874$n368_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 1000000000000000
|
|
.gate SB_LUT4 I0=KBD_RC_IN[22] I1=KBD_RC_EN[22] I2=KBD_RC_IN[23] I3=KBD_RC_EN[23] O=$abc$4874$n369_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 0000000000000001
|
|
.gate SB_LUT4 I0=KBD_RC_IN[20] I1=KBD_RC_EN[20] I2=KBD_RC_IN[21] I3=KBD_RC_EN[21] O=$abc$4874$n370_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 0000000000000001
|
|
.gate SB_LUT4 I0=KBD_RC_IN[26] I1=KBD_RC_EN[26] I2=KBD_RC_IN[27] I3=KBD_RC_EN[27] O=$abc$4874$n371_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 0000000000000001
|
|
.gate SB_LUT4 I0=KBD_RC_IN[24] I1=KBD_RC_EN[24] I2=KBD_RC_IN[25] I3=KBD_RC_EN[25] O=$abc$4874$n372_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 0000000000000001
|
|
.gate SB_LUT4 I0=$abc$4874$n374_1 I1=$abc$4874$n375_1 I2=$false I3=$false O=$abc$4874$n373_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 1000
|
|
.gate SB_LUT4 I0=KBD_RC_IN[11] I1=KBD_RC_EN[11] I2=KBD_RC_IN[7] I3=KBD_RC_EN[7] O=$abc$4874$n374_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 1110111011100000
|
|
.gate SB_LUT4 I0=KBD_RC_IN[10] I1=KBD_RC_EN[10] I2=KBD_RC_IN[4] I3=KBD_RC_EN[4] O=$abc$4874$n375_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 1110111011100000
|
|
.gate SB_LUT4 I0=$abc$4874$n377_1 I1=$abc$4874$n378_1 I2=$false I3=$false O=$abc$4874$n376_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 1000
|
|
.gate SB_LUT4 I0=KBD_RC_IN[18] I1=KBD_RC_EN[18] I2=KBD_RC_IN[19] I3=KBD_RC_EN[19] O=$abc$4874$n377_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 0000000000000001
|
|
.gate SB_LUT4 I0=KBD_RC_IN[2] I1=KBD_RC_EN[2] I2=KBD_RC_IN[0] I3=$abc$4874$n4 O=$abc$4874$n378_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 1110000011101110
|
|
.gate SB_LUT4 I0=$abc$4874$n462 I1=$abc$4874$n509_1 I2=$abc$4874$n344_1 I3=$abc$4874$n324 O=$abc$4874$n379_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 0100000000000000
|
|
.gate SB_LUT4 I0=$abc$4874$n287 I1=$abc$4874$n291 I2=$abc$4874$n381_1 I3=RESET O=$abc$4874$n58
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 0100000011111111
|
|
.gate SB_LUT4 I0=ms_counter[0] I1=ms_counter[1] I2=$abc$4874$n382 I3=$false O=$abc$4874$n381_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:48"
|
|
.param LUT_INIT 10010000
|
|
.gate SB_LUT4 I0=$abc$4874$n281 I1=$abc$4874$n284 I2=$abc$4874$n285 I3=$abc$4874$n288 O=$abc$4874$n382
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 0000000000000001
|
|
.gate SB_LUT4 I0=$abc$4874$n384_1 I1=RESET I2=$false I3=$false O=$abc$4874$n61
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 0100
|
|
.gate SB_LUT4 I0=UART.TX_sig_last I1=UART_WR I2=UART.tx_activity I3=$false O=$abc$4874$n384_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:48"
|
|
.param LUT_INIT 00001011
|
|
.gate SB_LUT4 I0=UART.tx_activity I1=$abc$4874$n386_1 I2=$abc$4874$n389_1 I3=$abc$4874$n61 O=$abc$4874$n64
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 0000110100000000
|
|
.gate SB_LUT4 I0=$abc$4874$n384 I1=$abc$4874$n269 I2=$abc$4874$n272 I3=$abc$4874$n388_1 O=$abc$4874$n386_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 0000000100000000
|
|
.gate SB_LUT4 I0=UART.tx_clk_counter[1] I1=UART.tx_clk_counter[0] I2=$false I3=$false O=$abc$4874$n384
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 1001
|
|
.gate SB_LUT4 I0=$abc$4874$n273 I1=$abc$4874$n275 I2=$abc$4874$n276 I3=$abc$4874$n279 O=$abc$4874$n388_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 0000000000000001
|
|
.gate SB_LUT4 I0=UART.tx_bit_counter[3] I1=$abc$4874$n390 I2=$false I3=$false O=$abc$4874$n389_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 0100
|
|
.gate SB_LUT4 I0=UART.tx_bit_counter[0] I1=UART.tx_bit_counter[1] I2=UART.tx_bit_counter[2] I3=UART.tx_activity O=$abc$4874$n390
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 0000000100000000
|
|
.gate SB_LUT4 I0=$abc$4874$n291 I1=$abc$4874$n366 I2=$false I3=$false O=$2\tact_counter_2ms[21:0][12]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 0100
|
|
.gate SB_LUT4 I0=$abc$4874$n291 I1=$abc$4874$n367 I2=$false I3=$false O=$2\tact_counter_2ms[21:0][13]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 0100
|
|
.gate SB_LUT4 I0=$abc$4874$n291 I1=$abc$4874$n368 I2=$false I3=$false O=$2\tact_counter_2ms[21:0][14]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 0100
|
|
.gate SB_LUT4 I0=$abc$4874$n291 I1=$abc$4874$n369 I2=$false I3=$false O=$2\tact_counter_2ms[21:0][15]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 0100
|
|
.gate SB_LUT4 I0=$abc$4874$n291 I1=$abc$4874$n372 I2=$false I3=$false O=$2\tact_counter_2ms[21:0][17]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 0100
|
|
.gate SB_LUT4 I0=$abc$4874$n291 I1=$abc$4874$n357 I2=$false I3=$false O=$2\tact_counter_2ms[21:0][4]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 0100
|
|
.gate SB_LUT4 I0=$abc$4874$n291 I1=$abc$4874$n358 I2=$false I3=$false O=$2\tact_counter_2ms[21:0][5]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 0100
|
|
.gate SB_LUT4 I0=$abc$4874$n400 I1=$abc$4874$n451 I2=$false I3=$false O=$5\com_len[2:0][0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 1011
|
|
.gate SB_LUT4 I0=com_len[0] I1=$abc$4874$n309 I2=$abc$4874$n342_1 I3=$false O=$abc$4874$n451
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:48"
|
|
.param LUT_INIT 00110101
|
|
.gate SB_LUT4 I0=$abc$4874$n401 I1=$abc$4874$n290 I2=$false I3=$false O=$abc$4874$n400
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 1000
|
|
.gate SB_LUT4 I0=$abc$4874$n18 I1=$abc$4874$n305_1 I2=$2\ms_counter[5:0][0] I3=$false O=$abc$4874$n401
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:48"
|
|
.param LUT_INIT 01000000
|
|
.gate SB_LUT4 I0=$abc$4874$n456 I1=$abc$4874$n400 I2=$false I3=$false O=$5\com_len[2:0][1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 0001
|
|
.gate SB_LUT4 I0=$abc$4874$n457 I1=$abc$4874$n400 I2=$false I3=$false O=$5\com_len[2:0][2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 0001
|
|
.gate SB_LUT4 I0=$abc$4874$n316 I1=$abc$4874$n342_1 I2=com_len[2] I3=$false O=$abc$4874$n457
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:48"
|
|
.param LUT_INIT 00000111
|
|
.gate SB_LUT4 I0=com_msg[6] I1=$2\ms_counter[5:0][0] I2=$abc$4874$n342_1 I3=$false O=$0\com_msg[11:0][6]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:48"
|
|
.param LUT_INIT 11001010
|
|
.gate SB_LUT4 I0=com_msg[7] I1=$abc$4874$n18 I2=$abc$4874$n342_1 I3=$false O=$0\com_msg[11:0][7]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:48"
|
|
.param LUT_INIT 00111010
|
|
.gate SB_LUT4 I0=$abc$4874$n16 I1=com_msg[8] I2=$abc$4874$n300 I3=$abc$4874$n343_1 O=$0\com_msg[11:0][8]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 1100010111001100
|
|
.gate SB_LUT4 I0=$abc$4874$n15 I1=com_msg[9] I2=$abc$4874$n300 I3=$abc$4874$n343_1 O=$0\com_msg[11:0][9]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 1100010111001100
|
|
.gate SB_LUT4 I0=$2\ms_counter[5:0][4] I1=com_msg[10] I2=$abc$4874$n300 I3=$abc$4874$n343_1 O=$0\com_msg[11:0][10]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 1100101011001100
|
|
.gate SB_LUT4 I0=$abc$4874$n459 I1=com_msg[11] I2=$abc$4874$n300 I3=$abc$4874$n343_1 O=$0\com_msg[11:0][11]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 1100010111001100
|
|
.gate SB_LUT4 I0=$abc$4874$n291 I1=$abc$4874$n364 I2=$false I3=$false O=$2\tact_counter_2ms[21:0][11]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 0100
|
|
.gate SB_LUT4 I0=$abc$4874$n291 I1=$abc$4874$n370 I2=$false I3=$false O=$2\tact_counter_2ms[21:0][16]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 0100
|
|
.gate SB_LUT4 I0=$abc$4874$n291 I1=$abc$4874$n373 I2=$false I3=$false O=$2\tact_counter_2ms[21:0][18]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 0100
|
|
.gate SB_LUT4 I0=$abc$4874$n291 I1=$abc$4874$n375 I2=$false I3=$false O=$2\tact_counter_2ms[21:0][19]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 0100
|
|
.gate SB_LUT4 I0=$abc$4874$n291 I1=$abc$4874$n377 I2=$false I3=$false O=$2\tact_counter_2ms[21:0][20]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 0100
|
|
.gate SB_LUT4 I0=$abc$4874$n291 I1=$abc$4874$n379 I2=$false I3=$false O=$2\tact_counter_2ms[21:0][21]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 0100
|
|
.gate SB_LUT4 I0=$abc$4874$n389_1 I1=$abc$4874$n386_1 I2=$abc$4874$n384_1 I3=$false O=$abc$4874$n381
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:48"
|
|
.param LUT_INIT 00000111
|
|
.gate SB_LUT4 I0=$abc$4874$n386_1 I1=$abc$4874$n273 I2=$false I3=$false O=$abc$4874$n386
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 1110
|
|
.gate SB_LUT4 I0=$abc$4874$n386_1 I1=$abc$4874$n276 I2=$false I3=$false O=$abc$4874$n388
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 1110
|
|
.gate SB_LUT4 I0=$abc$4874$n386_1 I1=$abc$4874$n279 I2=$false I3=$false O=$abc$4874$n389
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 1110
|
|
.gate SB_LUT4 I0=$abc$4874$n427_1 I1=$abc$4874$n428_1 I2=$abc$4874$n422_1 I3=$2\tact_counter_2ms[21:0][11] O=$0\UART_TX_DATA[5:0][0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 1110111000001111
|
|
.gate SB_LUT4 I0=$0\com_msg[11:0][8] I1=$abc$4874$n425 I2=$abc$4874$n423_1 I3=$abc$4874$n426 O=$abc$4874$n422_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 0000000001001111
|
|
.gate SB_LUT4 I0=com_msg[0] I1=$abc$4874$n425 I2=$abc$4874$n424 I3=$false O=$abc$4874$n423_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:48"
|
|
.param LUT_INIT 11100000
|
|
.gate SB_LUT4 I0=$abc$4874$n291 I1=$abc$4874$n364 I2=$abc$4874$n366 I3=$false O=$abc$4874$n424
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:48"
|
|
.param LUT_INIT 11101011
|
|
.gate SB_LUT4 I0=$abc$4874$n364 I1=$abc$4874$n366 I2=$abc$4874$n291 I3=$abc$4874$n367 O=$abc$4874$n425
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 0000101100000100
|
|
.gate SB_LUT4 I0=$2\tact_counter_2ms[21:0][12] I1=com_msg[4] I2=$false I3=$false O=$abc$4874$n426
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 1000
|
|
.gate SB_LUT4 I0=com_msg[2] I1=$0\com_msg[11:0][10] I2=$abc$4874$n425 I3=$abc$4874$n424 O=$abc$4874$n427_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 1100101000000000
|
|
.gate SB_LUT4 I0=com_msg[6] I1=$2\ms_counter[5:0][0] I2=$abc$4874$n424 I3=$abc$4874$n342_1 O=$abc$4874$n428_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 0000110000001010
|
|
.gate SB_LUT4 I0=$abc$4874$n433 I1=$abc$4874$n434_1 I2=$abc$4874$n430_1 I3=$2\tact_counter_2ms[21:0][11] O=$0\UART_TX_DATA[5:0][1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 1110111000001111
|
|
.gate SB_LUT4 I0=$0\com_msg[11:0][9] I1=$abc$4874$n425 I2=$abc$4874$n431_1 I3=$abc$4874$n432_1 O=$abc$4874$n430_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 0000000001001111
|
|
.gate SB_LUT4 I0=com_msg[1] I1=$abc$4874$n425 I2=$abc$4874$n424 I3=$false O=$abc$4874$n431_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:48"
|
|
.param LUT_INIT 11100000
|
|
.gate SB_LUT4 I0=$2\tact_counter_2ms[21:0][12] I1=com_msg[5] I2=$false I3=$false O=$abc$4874$n432_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 1000
|
|
.gate SB_LUT4 I0=com_msg[3] I1=$0\com_msg[11:0][11] I2=$abc$4874$n425 I3=$abc$4874$n424 O=$abc$4874$n433
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 1100101000000000
|
|
.gate SB_LUT4 I0=com_msg[7] I1=$abc$4874$n18 I2=$abc$4874$n424 I3=$abc$4874$n342_1 O=$abc$4874$n434_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 0000001100001010
|
|
.gate SB_LUT4 I0=$abc$4874$n428_1 I1=$abc$4874$n427_1 I2=$abc$4874$n436_1 I3=$2\tact_counter_2ms[21:0][11] O=$0\UART_TX_DATA[5:0][2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 1111000011101110
|
|
.gate SB_LUT4 I0=com_msg[4] I1=$0\com_msg[11:0][8] I2=$abc$4874$n424 I3=$false O=$abc$4874$n436_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:48"
|
|
.param LUT_INIT 10101100
|
|
.gate SB_LUT4 I0=$abc$4874$n434_1 I1=$abc$4874$n433 I2=$abc$4874$n438_1 I3=$2\tact_counter_2ms[21:0][11] O=$0\UART_TX_DATA[5:0][3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 1111000011101110
|
|
.gate SB_LUT4 I0=com_msg[5] I1=$0\com_msg[11:0][9] I2=$abc$4874$n424 I3=$false O=$abc$4874$n438_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:48"
|
|
.param LUT_INIT 10101100
|
|
.gate SB_LUT4 I0=$abc$4874$n446_1 I1=$abc$4874$n308_1 I2=$false I3=$false O=$abc$4874$n566
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 1000
|
|
.gate SB_LUT4 I0=$abc$4874$n305_1 I1=$abc$4874$n307_1 I2=$false I3=$false O=$abc$4874$n446_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 1000
|
|
.gate SB_LUT4 I0=$abc$4874$n308_1 I1=$abc$4874$n325_1 I2=$false I3=$false O=$abc$4874$n568
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 1000
|
|
.gate SB_LUT4 I0=$abc$4874$n308_1 I1=$abc$4874$n401 I2=$false I3=$false O=$abc$4874$n570
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 1000
|
|
.gate SB_LUT4 I0=$abc$4874$n308_1 I1=$abc$4874$n450 I2=$false I3=$false O=$abc$4874$n572
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 1000
|
|
.gate SB_LUT4 I0=$abc$4874$n16 I1=$2\ms_counter[5:0][0] I2=$abc$4874$n18 I3=$abc$4874$n15 O=$abc$4874$n450
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 0001000000000000
|
|
.gate SB_LUT4 I0=$abc$4874$n308_1 I1=$abc$4874$n452 I2=$false I3=$false O=$abc$4874$n574
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 1000
|
|
.gate SB_LUT4 I0=$abc$4874$n16 I1=$abc$4874$n307_1 I2=$abc$4874$n15 I3=$false O=$abc$4874$n452
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:48"
|
|
.param LUT_INIT 01000000
|
|
.gate SB_LUT4 I0=$abc$4874$n308_1 I1=$abc$4874$n454 I2=$false I3=$false O=$abc$4874$n576
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 1000
|
|
.gate SB_LUT4 I0=$abc$4874$n16 I1=$abc$4874$n18 I2=$2\ms_counter[5:0][0] I3=$abc$4874$n15 O=$abc$4874$n454
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 0000000100000000
|
|
.gate SB_LUT4 I0=$abc$4874$n308_1 I1=$abc$4874$n456_1 I2=$false I3=$false O=$abc$4874$n578
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 1000
|
|
.gate SB_LUT4 I0=$abc$4874$n16 I1=$abc$4874$n18 I2=$2\ms_counter[5:0][0] I3=$abc$4874$n15 O=$abc$4874$n456_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 0001000000000000
|
|
.gate SB_LUT4 I0=$2\ms_counter[5:0][0] I1=$abc$4874$n458 I2=$abc$4874$n18 I3=$abc$4874$n308_1 O=$abc$4874$n580
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 0100000000000000
|
|
.gate SB_LUT4 I0=$abc$4874$n15 I1=$abc$4874$n16 I2=$false I3=$false O=$abc$4874$n458
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 0100
|
|
.gate SB_LUT4 I0=$abc$4874$n308_1 I1=$abc$4874$n458 I2=$abc$4874$n307_1 I3=$false O=$abc$4874$n582
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:48"
|
|
.param LUT_INIT 10000000
|
|
.gate SB_LUT4 I0=$abc$4874$n18 I1=$2\ms_counter[5:0][0] I2=$abc$4874$n308_1 I3=$abc$4874$n458 O=$abc$4874$n584
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 0001000000000000
|
|
.gate SB_LUT4 I0=$abc$4874$n18 I1=$abc$4874$n458 I2=$abc$4874$n308_1 I3=$2\ms_counter[5:0][0] O=$abc$4874$n586
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 0100000000000000
|
|
.gate SB_LUT4 I0=$abc$4874$n308_1 I1=$abc$4874$n463_1 I2=$false I3=$false O=$abc$4874$n588
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 1000
|
|
.gate SB_LUT4 I0=$abc$4874$n16 I1=$2\ms_counter[5:0][0] I2=$abc$4874$n15 I3=$abc$4874$n18 O=$abc$4874$n463_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 0000000100000000
|
|
.gate SB_LUT4 I0=$abc$4874$n308_1 I1=$abc$4874$n465_1 I2=$false I3=$false O=$abc$4874$n590
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 1000
|
|
.gate SB_LUT4 I0=$abc$4874$n16 I1=$abc$4874$n15 I2=$abc$4874$n307_1 I3=$false O=$abc$4874$n465_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:48"
|
|
.param LUT_INIT 00010000
|
|
.gate SB_LUT4 I0=$abc$4874$n308_1 I1=$abc$4874$n467_1 I2=$false I3=$false O=$abc$4874$n592
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 1000
|
|
.gate SB_LUT4 I0=$abc$4874$n16 I1=$abc$4874$n18 I2=$2\ms_counter[5:0][0] I3=$abc$4874$n15 O=$abc$4874$n467_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 0000000000000001
|
|
.gate SB_LUT4 I0=$abc$4874$n308_1 I1=$abc$4874$n469_1 I2=$false I3=$false O=$abc$4874$n594
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 1000
|
|
.gate SB_LUT4 I0=$abc$4874$n16 I1=$abc$4874$n18 I2=$abc$4874$n15 I3=$2\ms_counter[5:0][0] O=$abc$4874$n469_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 0000000100000000
|
|
.gate SB_LUT4 I0=$abc$4874$n310 I1=$abc$4874$n471_1 I2=$false I3=$false O=$abc$4874$n596
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 1000
|
|
.gate SB_LUT4 I0=$abc$4874$n459 I1=$2\ms_counter[5:0][4] I2=$false I3=$false O=$abc$4874$n471_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 1000
|
|
.gate SB_LUT4 I0=$abc$4874$n446_1 I1=$abc$4874$n471_1 I2=$false I3=$false O=$abc$4874$n598
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 1000
|
|
.gate SB_LUT4 I0=$abc$4874$n325_1 I1=$abc$4874$n471_1 I2=$false I3=$false O=$abc$4874$n600
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 1000
|
|
.gate SB_LUT4 I0=$abc$4874$n401 I1=$abc$4874$n471_1 I2=$false I3=$false O=$abc$4874$n602
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 1000
|
|
.gate SB_LUT4 I0=$abc$4874$n450 I1=$abc$4874$n471_1 I2=$false I3=$false O=$abc$4874$n604
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 1000
|
|
.gate SB_LUT4 I0=$abc$4874$n452 I1=$abc$4874$n471_1 I2=$false I3=$false O=$abc$4874$n606
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 1000
|
|
.gate SB_LUT4 I0=$abc$4874$n454 I1=$abc$4874$n471_1 I2=$false I3=$false O=$abc$4874$n608
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 1000
|
|
.gate SB_LUT4 I0=$abc$4874$n456_1 I1=$abc$4874$n471_1 I2=$false I3=$false O=$abc$4874$n610
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 1000
|
|
.gate SB_LUT4 I0=$2\ms_counter[5:0][0] I1=$abc$4874$n471_1 I2=$abc$4874$n18 I3=$abc$4874$n458 O=$abc$4874$n612
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 0100000000000000
|
|
.gate SB_LUT4 I0=$abc$4874$n458 I1=$abc$4874$n471_1 I2=$abc$4874$n307_1 I3=$false O=$abc$4874$n614
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:48"
|
|
.param LUT_INIT 10000000
|
|
.gate SB_LUT4 I0=$abc$4874$n18 I1=$2\ms_counter[5:0][0] I2=$abc$4874$n458 I3=$abc$4874$n471_1 O=$abc$4874$n616
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 0001000000000000
|
|
.gate SB_LUT4 I0=$abc$4874$n18 I1=$abc$4874$n471_1 I2=$abc$4874$n458 I3=$2\ms_counter[5:0][0] O=$abc$4874$n618
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 0100000000000000
|
|
.gate SB_LUT4 I0=$abc$4874$n463_1 I1=$abc$4874$n471_1 I2=$false I3=$false O=$abc$4874$n620
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 1000
|
|
.gate SB_LUT4 I0=$abc$4874$n465_1 I1=$abc$4874$n471_1 I2=$false I3=$false O=$abc$4874$n622
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 1000
|
|
.gate SB_LUT4 I0=$abc$4874$n467_1 I1=$abc$4874$n471_1 I2=$false I3=$false O=$abc$4874$n624
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 1000
|
|
.gate SB_LUT4 I0=$abc$4874$n469_1 I1=$abc$4874$n471_1 I2=$false I3=$false O=$abc$4874$n626
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 1000
|
|
.gate SB_LUT4 I0=$abc$4874$n310 I1=$abc$4874$n290 I2=$false I3=$false O=$abc$4874$n627
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 1000
|
|
.gate SB_LUT4 I0=$abc$4874$n446_1 I1=$abc$4874$n290 I2=$false I3=$false O=$abc$4874$n628
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:44"
|
|
.param LUT_INIT 1000
|
|
.gate SB_LUT4 I0=$abc$4874$n4 I1=$false I2=$false I3=$false O=KBD_RC_EN[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:40"
|
|
.param LUT_INIT 01
|
|
.gate SB_LUT4 I0=$abc$4874$n6 I1=$false I2=$false I3=$false O=DBG_TX
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:40"
|
|
.param LUT_INIT 01
|
|
.gate SB_LUT4 I0=RESET I1=$false I2=$false I3=$false O=$abc$4874$n9
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:40"
|
|
.param LUT_INIT 01
|
|
.gate SB_LUT4 I0=UART.tx_activity I1=$false I2=$false I3=$false O=$abc$4874$n11
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:40"
|
|
.param LUT_INIT 01
|
|
.gate SB_LUT4 I0=$2\ms_counter[5:0][4] I1=$false I2=$false I3=$false O=$abc$4874$n13
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:40"
|
|
.param LUT_INIT 01
|
|
.gate SB_LUT4 I0=$abc$4874$n16 I1=$false I2=$false I3=$false O=$2\ms_counter[5:0][2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:40"
|
|
.param LUT_INIT 01
|
|
.gate SB_LUT4 I0=$abc$4874$n15 I1=$false I2=$false I3=$false O=$2\ms_counter[5:0][3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:40"
|
|
.param LUT_INIT 01
|
|
.gate SB_LUT4 I0=$abc$4874$n18 I1=$false I2=$false I3=$false O=$2\ms_counter[5:0][1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:40"
|
|
.param LUT_INIT 01
|
|
.gate SB_LUT4 I0=$abc$4874$n459 I1=$false I2=$false I3=$false O=$2\ms_counter[5:0][5]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:40"
|
|
.param LUT_INIT 01
|
|
.gate SB_LUT4 I0=$abc$4874$n446 I1=$false I2=$false I3=$false O=$abc$4874$n432
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:40"
|
|
.param LUT_INIT 01
|
|
.gate SB_LUT4 I0=$abc$4874$n431 I1=$false I2=$false I3=$false O=$abc$4874$n460
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:40"
|
|
.param LUT_INIT 01
|
|
.gate SB_LUT4 I0=$abc$4874$n434 I1=$false I2=$false I3=$false O=$abc$4874$n461
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:40"
|
|
.param LUT_INIT 01
|
|
.gate SB_LUT4 I0=dbg_led[0] I1=$false I2=$false I3=$false O=$2\dbg_led[2:0][0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:40"
|
|
.param LUT_INIT 01
|
|
.gate SB_LUT4 I0=dbg_led[1] I1=$false I2=$false I3=$false O=$2\dbg_led[2:0][1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:40"
|
|
.param LUT_INIT 01
|
|
.gate SB_LUT4 I0=RESET I1=$false I2=$false I3=$false O=$abc$4874$n23
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:40"
|
|
.param LUT_INIT 01
|
|
.gate SB_LUT4 I0=$abc$4874$n357 I1=$abc$4874$n358 I2=$abc$4874$n355 I3=$abc$4874$n291 O=$abc$4874$n507
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 1111111100000001
|
|
.gate SB_LUT4 I0=$2\tact_counter_2ms[21:0][7] I1=$2\tact_counter_2ms[21:0][0] I2=$2\tact_counter_2ms[21:0][3] I3=$2\tact_counter_2ms[21:0][1] O=$abc$4874$n508_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 0000000000000001
|
|
.gate SB_LUT4 I0=$2\tact_counter_2ms[21:0][6] I1=$abc$4874$n507 I2=$abc$4874$n508_1 I3=$false O=$abc$4874$n509_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:48"
|
|
.param LUT_INIT 01000000
|
|
.gate SB_LUT4 I0=$0\com_msg[11:0][10] I1=com_msg[6] I2=$abc$4874$n366 I3=$false O=$abc$4874$n510
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:48"
|
|
.param LUT_INIT 11001010
|
|
.gate SB_LUT4 I0=$abc$4874$n510 I1=$abc$4874$n436_1 I2=$abc$4874$n291 I3=$abc$4874$n364 O=$0\UART_TX_DATA[5:0][4]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 1100101011001100
|
|
.gate SB_LUT4 I0=$0\com_msg[11:0][11] I1=com_msg[7] I2=$abc$4874$n366 I3=$false O=$abc$4874$n512_1
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:48"
|
|
.param LUT_INIT 11001010
|
|
.gate SB_LUT4 I0=$abc$4874$n512_1 I1=$abc$4874$n438_1 I2=$abc$4874$n291 I3=$abc$4874$n364 O=$0\UART_TX_DATA[5:0][5]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:52"
|
|
.param LUT_INIT 1100101011001100
|
|
.gate SB_CARRY CI=$true CO=$auto$alumacc.cc:474:replace_alu$432.C[1] I0=$2\tact_counter_2ms[21:0][11] I1=$abc$4874$n451
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:79|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
|
|
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$432.C[1] CO=$auto$alumacc.cc:474:replace_alu$432.C[2] I0=$2\tact_counter_2ms[21:0][12] I1=$abc$4874$n456
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:79|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
|
|
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$432.C[2] CO=$abc$4874$n462 I0=$2\tact_counter_2ms[21:0][13] I1=$abc$4874$n457
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:79|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
|
|
.gate SB_CARRY CI=$abc$4874$n18 CO=$auto$alumacc.cc:474:replace_alu$437.C[3] I0=$false I1=$abc$4874$n16
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:102|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
|
|
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$437.C[3] CO=$auto$alumacc.cc:474:replace_alu$437.C[4] I0=$false I1=$abc$4874$n15
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:102|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
|
|
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$437.C[4] CO=$auto$alumacc.cc:474:replace_alu$437.C[5] I0=$false I1=$abc$4874$n13
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:102|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
|
|
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$437.C[5] CO=$abc$4874$n453 I0=$true I1=$abc$4874$n459
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:102|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
|
|
.gate SB_LUT4 I0=$false I1=$abc$4874$n9 I2=rststate[0] I3=$false O=$0\rststate[3:0][0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:35|/usr/local/bin/../share/yosys/ice40/arith_map.v:53"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_CARRY CI=$false CO=$auto$alumacc.cc:474:replace_alu$448.C[1] I0=$abc$4874$n9 I1=rststate[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:35|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=rststate[1] I3=$auto$alumacc.cc:474:replace_alu$448.C[1] O=$0\rststate[3:0][1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:35|/usr/local/bin/../share/yosys/ice40/arith_map.v:53"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$448.C[1] CO=$auto$alumacc.cc:474:replace_alu$448.C[2] I0=$false I1=rststate[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:35|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=rststate[2] I3=$auto$alumacc.cc:474:replace_alu$448.C[2] O=$0\rststate[3:0][2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:35|/usr/local/bin/../share/yosys/ice40/arith_map.v:53"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$448.C[2] CO=$auto$alumacc.cc:474:replace_alu$448.C[3] I0=$false I1=rststate[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:35|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=rststate[3] I3=$auto$alumacc.cc:474:replace_alu$448.C[3] O=$0\rststate[3:0][3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:35|/usr/local/bin/../share/yosys/ice40/arith_map.v:53"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_LUT4 I0=$false I1=$true I2=ms_counter[0] I3=$false O=$abc$4874$n281
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:50|/usr/local/bin/../share/yosys/ice40/arith_map.v:53"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_CARRY CI=ms_counter[0] CO=$auto$alumacc.cc:474:replace_alu$451.C[2] I0=$false I1=ms_counter[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:50|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=ms_counter[2] I3=$auto$alumacc.cc:474:replace_alu$451.C[2] O=$abc$4874$n284
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:50|/usr/local/bin/../share/yosys/ice40/arith_map.v:53"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$451.C[2] CO=$auto$alumacc.cc:474:replace_alu$451.C[3] I0=$false I1=ms_counter[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:50|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=ms_counter[3] I3=$auto$alumacc.cc:474:replace_alu$451.C[3] O=$abc$4874$n285
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:50|/usr/local/bin/../share/yosys/ice40/arith_map.v:53"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$451.C[3] CO=$auto$alumacc.cc:474:replace_alu$451.C[4] I0=$false I1=ms_counter[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:50|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=ms_counter[4] I3=$auto$alumacc.cc:474:replace_alu$451.C[4] O=$abc$4874$n287
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:50|/usr/local/bin/../share/yosys/ice40/arith_map.v:53"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$451.C[4] CO=$auto$alumacc.cc:474:replace_alu$451.C[5] I0=$false I1=ms_counter[4]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:50|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=ms_counter[5] I3=$auto$alumacc.cc:474:replace_alu$451.C[5] O=$abc$4874$n288
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:50|/usr/local/bin/../share/yosys/ice40/arith_map.v:53"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_LUT4 I0=$false I1=$true I2=tact_counter_2ms[0] I3=$false O=$abc$4874$n353
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:55|/usr/local/bin/../share/yosys/ice40/arith_map.v:53"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tact_counter_2ms[10] I3=$auto$alumacc.cc:474:replace_alu$454.C[10] O=$abc$4874$n363
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:55|/usr/local/bin/../share/yosys/ice40/arith_map.v:53"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$454.C[10] CO=$auto$alumacc.cc:474:replace_alu$454.C[11] I0=$false I1=tact_counter_2ms[10]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:55|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tact_counter_2ms[11] I3=$auto$alumacc.cc:474:replace_alu$454.C[11] O=$abc$4874$n364
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:55|/usr/local/bin/../share/yosys/ice40/arith_map.v:53"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$454.C[11] CO=$auto$alumacc.cc:474:replace_alu$454.C[12] I0=$false I1=tact_counter_2ms[11]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:55|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tact_counter_2ms[12] I3=$auto$alumacc.cc:474:replace_alu$454.C[12] O=$abc$4874$n366
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:55|/usr/local/bin/../share/yosys/ice40/arith_map.v:53"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$454.C[12] CO=$auto$alumacc.cc:474:replace_alu$454.C[13] I0=$false I1=tact_counter_2ms[12]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:55|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tact_counter_2ms[13] I3=$auto$alumacc.cc:474:replace_alu$454.C[13] O=$abc$4874$n367
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:55|/usr/local/bin/../share/yosys/ice40/arith_map.v:53"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$454.C[13] CO=$auto$alumacc.cc:474:replace_alu$454.C[14] I0=$false I1=tact_counter_2ms[13]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:55|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tact_counter_2ms[14] I3=$auto$alumacc.cc:474:replace_alu$454.C[14] O=$abc$4874$n368
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:55|/usr/local/bin/../share/yosys/ice40/arith_map.v:53"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$454.C[14] CO=$auto$alumacc.cc:474:replace_alu$454.C[15] I0=$false I1=tact_counter_2ms[14]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:55|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tact_counter_2ms[15] I3=$auto$alumacc.cc:474:replace_alu$454.C[15] O=$abc$4874$n369
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:55|/usr/local/bin/../share/yosys/ice40/arith_map.v:53"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$454.C[15] CO=$auto$alumacc.cc:474:replace_alu$454.C[16] I0=$false I1=tact_counter_2ms[15]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:55|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tact_counter_2ms[16] I3=$auto$alumacc.cc:474:replace_alu$454.C[16] O=$abc$4874$n370
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:55|/usr/local/bin/../share/yosys/ice40/arith_map.v:53"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$454.C[16] CO=$auto$alumacc.cc:474:replace_alu$454.C[17] I0=$false I1=tact_counter_2ms[16]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:55|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tact_counter_2ms[17] I3=$auto$alumacc.cc:474:replace_alu$454.C[17] O=$abc$4874$n372
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:55|/usr/local/bin/../share/yosys/ice40/arith_map.v:53"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$454.C[17] CO=$auto$alumacc.cc:474:replace_alu$454.C[18] I0=$false I1=tact_counter_2ms[17]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:55|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tact_counter_2ms[18] I3=$auto$alumacc.cc:474:replace_alu$454.C[18] O=$abc$4874$n373
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:55|/usr/local/bin/../share/yosys/ice40/arith_map.v:53"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$454.C[18] CO=$auto$alumacc.cc:474:replace_alu$454.C[19] I0=$false I1=tact_counter_2ms[18]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:55|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tact_counter_2ms[19] I3=$auto$alumacc.cc:474:replace_alu$454.C[19] O=$abc$4874$n375
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:55|/usr/local/bin/../share/yosys/ice40/arith_map.v:53"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$454.C[19] CO=$auto$alumacc.cc:474:replace_alu$454.C[20] I0=$false I1=tact_counter_2ms[19]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:55|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
|
|
.gate SB_CARRY CI=tact_counter_2ms[0] CO=$auto$alumacc.cc:474:replace_alu$454.C[2] I0=$false I1=tact_counter_2ms[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:55|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tact_counter_2ms[20] I3=$auto$alumacc.cc:474:replace_alu$454.C[20] O=$abc$4874$n377
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:55|/usr/local/bin/../share/yosys/ice40/arith_map.v:53"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$454.C[20] CO=$auto$alumacc.cc:474:replace_alu$454.C[21] I0=$false I1=tact_counter_2ms[20]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:55|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tact_counter_2ms[21] I3=$auto$alumacc.cc:474:replace_alu$454.C[21] O=$abc$4874$n379
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:55|/usr/local/bin/../share/yosys/ice40/arith_map.v:53"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tact_counter_2ms[2] I3=$auto$alumacc.cc:474:replace_alu$454.C[2] O=$abc$4874$n355
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:55|/usr/local/bin/../share/yosys/ice40/arith_map.v:53"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$454.C[2] CO=$auto$alumacc.cc:474:replace_alu$454.C[3] I0=$false I1=tact_counter_2ms[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:55|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tact_counter_2ms[3] I3=$auto$alumacc.cc:474:replace_alu$454.C[3] O=$abc$4874$n356
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:55|/usr/local/bin/../share/yosys/ice40/arith_map.v:53"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$454.C[3] CO=$auto$alumacc.cc:474:replace_alu$454.C[4] I0=$false I1=tact_counter_2ms[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:55|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tact_counter_2ms[4] I3=$auto$alumacc.cc:474:replace_alu$454.C[4] O=$abc$4874$n357
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:55|/usr/local/bin/../share/yosys/ice40/arith_map.v:53"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$454.C[4] CO=$auto$alumacc.cc:474:replace_alu$454.C[5] I0=$false I1=tact_counter_2ms[4]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:55|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tact_counter_2ms[5] I3=$auto$alumacc.cc:474:replace_alu$454.C[5] O=$abc$4874$n358
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:55|/usr/local/bin/../share/yosys/ice40/arith_map.v:53"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$454.C[5] CO=$auto$alumacc.cc:474:replace_alu$454.C[6] I0=$false I1=tact_counter_2ms[5]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:55|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tact_counter_2ms[6] I3=$auto$alumacc.cc:474:replace_alu$454.C[6] O=$abc$4874$n359
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:55|/usr/local/bin/../share/yosys/ice40/arith_map.v:53"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$454.C[6] CO=$auto$alumacc.cc:474:replace_alu$454.C[7] I0=$false I1=tact_counter_2ms[6]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:55|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tact_counter_2ms[7] I3=$auto$alumacc.cc:474:replace_alu$454.C[7] O=$abc$4874$n360
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:55|/usr/local/bin/../share/yosys/ice40/arith_map.v:53"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$454.C[7] CO=$auto$alumacc.cc:474:replace_alu$454.C[8] I0=$false I1=tact_counter_2ms[7]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:55|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tact_counter_2ms[8] I3=$auto$alumacc.cc:474:replace_alu$454.C[8] O=$abc$4874$n361
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:55|/usr/local/bin/../share/yosys/ice40/arith_map.v:53"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$454.C[8] CO=$auto$alumacc.cc:474:replace_alu$454.C[9] I0=$false I1=tact_counter_2ms[8]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:55|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=tact_counter_2ms[9] I3=$auto$alumacc.cc:474:replace_alu$454.C[9] O=$abc$4874$n362
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:55|/usr/local/bin/../share/yosys/ice40/arith_map.v:53"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$454.C[9] CO=$auto$alumacc.cc:474:replace_alu$454.C[10] I0=$false I1=tact_counter_2ms[9]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:55|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
|
|
.gate SB_LUT4 I0=$false I1=$true I2=com_len[0] I3=$false O=$abc$4874$n309
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:61|/usr/local/bin/../share/yosys/ice40/arith_map.v:53"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_CARRY CI=com_len[0] CO=$auto$alumacc.cc:474:replace_alu$457.C[2] I0=$false I1=com_len[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:61|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=com_len[2] I3=$auto$alumacc.cc:474:replace_alu$457.C[2] O=$abc$4874$n316
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:61|/usr/local/bin/../share/yosys/ice40/arith_map.v:53"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_LUT4 I0=$false I1=UART.tx_clk_counter[0] I2=$false I3=$true O=$abc$4874$n269
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:28|uart.v:33|/usr/local/bin/../share/yosys/ice40/arith_map.v:53"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_CARRY CI=UART.tx_clk_counter[0] CO=$auto$alumacc.cc:474:replace_alu$460.C[2] I0=UART.tx_clk_counter[1] I1=$true
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:28|uart.v:33|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
|
|
.gate SB_LUT4 I0=$false I1=UART.tx_clk_counter[2] I2=$true I3=$auto$alumacc.cc:474:replace_alu$460.C[2] O=$abc$4874$n272
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:28|uart.v:33|/usr/local/bin/../share/yosys/ice40/arith_map.v:53"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$460.C[2] CO=$auto$alumacc.cc:474:replace_alu$460.C[3] I0=UART.tx_clk_counter[2] I1=$true
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:28|uart.v:33|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
|
|
.gate SB_LUT4 I0=$false I1=UART.tx_clk_counter[3] I2=$true I3=$auto$alumacc.cc:474:replace_alu$460.C[3] O=$abc$4874$n273
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:28|uart.v:33|/usr/local/bin/../share/yosys/ice40/arith_map.v:53"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$460.C[3] CO=$auto$alumacc.cc:474:replace_alu$460.C[4] I0=UART.tx_clk_counter[3] I1=$true
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:28|uart.v:33|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
|
|
.gate SB_LUT4 I0=$false I1=UART.tx_clk_counter[4] I2=$true I3=$auto$alumacc.cc:474:replace_alu$460.C[4] O=$abc$4874$n275
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:28|uart.v:33|/usr/local/bin/../share/yosys/ice40/arith_map.v:53"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$460.C[4] CO=$auto$alumacc.cc:474:replace_alu$460.C[5] I0=UART.tx_clk_counter[4] I1=$true
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:28|uart.v:33|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
|
|
.gate SB_LUT4 I0=$false I1=UART.tx_clk_counter[5] I2=$true I3=$auto$alumacc.cc:474:replace_alu$460.C[5] O=$abc$4874$n276
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:28|uart.v:33|/usr/local/bin/../share/yosys/ice40/arith_map.v:53"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$460.C[5] CO=$auto$alumacc.cc:474:replace_alu$460.C[6] I0=UART.tx_clk_counter[5] I1=$true
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:28|uart.v:33|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
|
|
.gate SB_LUT4 I0=$false I1=UART.tx_clk_counter[6] I2=$true I3=$auto$alumacc.cc:474:replace_alu$460.C[6] O=$abc$4874$n279
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:28|uart.v:33|/usr/local/bin/../share/yosys/ice40/arith_map.v:53"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_LUT4 I0=$false I1=UART.tx_bit_counter[0] I2=$false I3=$true O=$abc$4874$n431
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:28|uart.v:39|/usr/local/bin/../share/yosys/ice40/arith_map.v:53"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_CARRY CI=UART.tx_bit_counter[0] CO=$auto$alumacc.cc:474:replace_alu$463.C[2] I0=UART.tx_bit_counter[1] I1=$true
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:28|uart.v:39|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
|
|
.gate SB_LUT4 I0=$false I1=UART.tx_bit_counter[2] I2=$true I3=$auto$alumacc.cc:474:replace_alu$463.C[2] O=$abc$4874$n434
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:28|uart.v:39|/usr/local/bin/../share/yosys/ice40/arith_map.v:53"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_CARRY CI=$auto$alumacc.cc:474:replace_alu$463.C[2] CO=$auto$alumacc.cc:474:replace_alu$463.C[3] I0=UART.tx_bit_counter[2] I1=$true
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:28|uart.v:39|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
|
|
.gate SB_LUT4 I0=$false I1=UART.tx_bit_counter[3] I2=$true I3=$auto$alumacc.cc:474:replace_alu$463.C[3] O=$abc$4874$n436
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:28|uart.v:39|/usr/local/bin/../share/yosys/ice40/arith_map.v:53"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_LUT4 I0=$false I1=$false I2=$abc$4874$n460 I3=$true O=$abc$4874$n427
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:28|uart.v:41|/usr/local/bin/../share/yosys/ice40/arith_map.v:53"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_CARRY CI=$abc$4874$n460 CO=$auto$alumacc.cc:474:replace_alu$466.C[2] I0=$false I1=$abc$4874$n446
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:28|uart.v:41|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
|
|
.gate SB_LUT4 I0=$false I1=$false I2=$abc$4874$n461 I3=$auto$alumacc.cc:474:replace_alu$466.C[2] O=$abc$4874$n420
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:28|uart.v:41|/usr/local/bin/../share/yosys/ice40/arith_map.v:53"
|
|
.param LUT_INIT 0110100110010110
|
|
.gate SB_DFFSR C=CLK D=$2\tact_counter_2ms[21:0][0] Q=tact_counter_2ms[0] R=$abc$4874$n9
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
|
|
.gate SB_DFFSR C=CLK D=$2\tact_counter_2ms[21:0][1] Q=tact_counter_2ms[1] R=$abc$4874$n9
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
|
|
.gate SB_DFFSR C=CLK D=$2\tact_counter_2ms[21:0][2] Q=tact_counter_2ms[2] R=$abc$4874$n9
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
|
|
.gate SB_DFFSR C=CLK D=$2\tact_counter_2ms[21:0][3] Q=tact_counter_2ms[3] R=$abc$4874$n9
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
|
|
.gate SB_DFFSR C=CLK D=$2\tact_counter_2ms[21:0][4] Q=tact_counter_2ms[4] R=$abc$4874$n9
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
|
|
.gate SB_DFFSR C=CLK D=$2\tact_counter_2ms[21:0][5] Q=tact_counter_2ms[5] R=$abc$4874$n9
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
|
|
.gate SB_DFFSR C=CLK D=$2\tact_counter_2ms[21:0][6] Q=tact_counter_2ms[6] R=$abc$4874$n9
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
|
|
.gate SB_DFFSR C=CLK D=$2\tact_counter_2ms[21:0][7] Q=tact_counter_2ms[7] R=$abc$4874$n9
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
|
|
.gate SB_DFFSR C=CLK D=$2\tact_counter_2ms[21:0][8] Q=tact_counter_2ms[8] R=$abc$4874$n9
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
|
|
.gate SB_DFFSR C=CLK D=$2\tact_counter_2ms[21:0][9] Q=tact_counter_2ms[9] R=$abc$4874$n9
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
|
|
.gate SB_DFFSR C=CLK D=$2\tact_counter_2ms[21:0][10] Q=tact_counter_2ms[10] R=$abc$4874$n9
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
|
|
.gate SB_DFFSR C=CLK D=$2\tact_counter_2ms[21:0][11] Q=tact_counter_2ms[11] R=$abc$4874$n9
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
|
|
.gate SB_DFFSR C=CLK D=$2\tact_counter_2ms[21:0][12] Q=tact_counter_2ms[12] R=$abc$4874$n9
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
|
|
.gate SB_DFFSR C=CLK D=$2\tact_counter_2ms[21:0][13] Q=tact_counter_2ms[13] R=$abc$4874$n9
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
|
|
.gate SB_DFFSR C=CLK D=$2\tact_counter_2ms[21:0][14] Q=tact_counter_2ms[14] R=$abc$4874$n9
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
|
|
.gate SB_DFFSR C=CLK D=$2\tact_counter_2ms[21:0][15] Q=tact_counter_2ms[15] R=$abc$4874$n9
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
|
|
.gate SB_DFFSR C=CLK D=$2\tact_counter_2ms[21:0][16] Q=tact_counter_2ms[16] R=$abc$4874$n9
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
|
|
.gate SB_DFFSR C=CLK D=$2\tact_counter_2ms[21:0][17] Q=tact_counter_2ms[17] R=$abc$4874$n9
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
|
|
.gate SB_DFFSR C=CLK D=$2\tact_counter_2ms[21:0][18] Q=tact_counter_2ms[18] R=$abc$4874$n9
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
|
|
.gate SB_DFFSR C=CLK D=$2\tact_counter_2ms[21:0][19] Q=tact_counter_2ms[19] R=$abc$4874$n9
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
|
|
.gate SB_DFFSR C=CLK D=$2\tact_counter_2ms[21:0][20] Q=tact_counter_2ms[20] R=$abc$4874$n9
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
|
|
.gate SB_DFFSR C=CLK D=$2\tact_counter_2ms[21:0][21] Q=tact_counter_2ms[21] R=$abc$4874$n9
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
|
|
.gate SB_DFFSR C=CLK D=$2\ms_counter[5:0][0] Q=ms_counter[0] R=$abc$4874$n9
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
|
|
.gate SB_DFFSR C=CLK D=$2\ms_counter[5:0][1] Q=ms_counter[1] R=$abc$4874$n9
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
|
|
.gate SB_DFFSR C=CLK D=$2\ms_counter[5:0][2] Q=ms_counter[2] R=$abc$4874$n9
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
|
|
.gate SB_DFFSR C=CLK D=$2\ms_counter[5:0][3] Q=ms_counter[3] R=$abc$4874$n9
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
|
|
.gate SB_DFFSR C=CLK D=$2\ms_counter[5:0][4] Q=ms_counter[4] R=$abc$4874$n9
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
|
|
.gate SB_DFFSR C=CLK D=$2\ms_counter[5:0][5] Q=ms_counter[5] R=$abc$4874$n9
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
|
|
.gate SB_DFFE C=CLK D=$abc$4874$n1 E=RESET Q=$abc$4874$n4
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFESR C=CLK D=$abc$4874$n566 E=RESET Q=KBD_RC_EN[1] R=$abc$4874$n300
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFESR C=CLK D=$abc$4874$n568 E=RESET Q=KBD_RC_EN[2] R=$abc$4874$n300
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFESR C=CLK D=$abc$4874$n570 E=RESET Q=KBD_RC_EN[3] R=$abc$4874$n300
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFESR C=CLK D=$abc$4874$n572 E=RESET Q=KBD_RC_EN[4] R=$abc$4874$n300
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFESR C=CLK D=$abc$4874$n574 E=RESET Q=KBD_RC_EN[5] R=$abc$4874$n300
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFESR C=CLK D=$abc$4874$n576 E=RESET Q=KBD_RC_EN[6] R=$abc$4874$n300
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFESR C=CLK D=$abc$4874$n578 E=RESET Q=KBD_RC_EN[7] R=$abc$4874$n300
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFESR C=CLK D=$abc$4874$n580 E=RESET Q=KBD_RC_EN[8] R=$abc$4874$n300
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFESR C=CLK D=$abc$4874$n582 E=RESET Q=KBD_RC_EN[9] R=$abc$4874$n300
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFESR C=CLK D=$abc$4874$n584 E=RESET Q=KBD_RC_EN[10] R=$abc$4874$n300
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFESR C=CLK D=$abc$4874$n586 E=RESET Q=KBD_RC_EN[11] R=$abc$4874$n300
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFESR C=CLK D=$abc$4874$n588 E=RESET Q=KBD_RC_EN[12] R=$abc$4874$n300
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFESR C=CLK D=$abc$4874$n590 E=RESET Q=KBD_RC_EN[13] R=$abc$4874$n300
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFESR C=CLK D=$abc$4874$n592 E=RESET Q=KBD_RC_EN[14] R=$abc$4874$n300
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFESR C=CLK D=$abc$4874$n594 E=RESET Q=KBD_RC_EN[15] R=$abc$4874$n300
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFESR C=CLK D=$abc$4874$n596 E=RESET Q=KBD_RC_EN[16] R=$abc$4874$n300
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFESR C=CLK D=$abc$4874$n598 E=RESET Q=KBD_RC_EN[17] R=$abc$4874$n300
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFESR C=CLK D=$abc$4874$n600 E=RESET Q=KBD_RC_EN[18] R=$abc$4874$n300
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFESR C=CLK D=$abc$4874$n602 E=RESET Q=KBD_RC_EN[19] R=$abc$4874$n300
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFESR C=CLK D=$abc$4874$n604 E=RESET Q=KBD_RC_EN[20] R=$abc$4874$n300
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFESR C=CLK D=$abc$4874$n606 E=RESET Q=KBD_RC_EN[21] R=$abc$4874$n300
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFESR C=CLK D=$abc$4874$n608 E=RESET Q=KBD_RC_EN[22] R=$abc$4874$n300
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFESR C=CLK D=$abc$4874$n610 E=RESET Q=KBD_RC_EN[23] R=$abc$4874$n300
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFESR C=CLK D=$abc$4874$n612 E=RESET Q=KBD_RC_EN[24] R=$abc$4874$n300
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFESR C=CLK D=$abc$4874$n614 E=RESET Q=KBD_RC_EN[25] R=$abc$4874$n300
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFESR C=CLK D=$abc$4874$n616 E=RESET Q=KBD_RC_EN[26] R=$abc$4874$n300
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFESR C=CLK D=$abc$4874$n618 E=RESET Q=KBD_RC_EN[27] R=$abc$4874$n300
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFESR C=CLK D=$abc$4874$n620 E=RESET Q=KBD_RC_EN[28] R=$abc$4874$n300
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFESR C=CLK D=$abc$4874$n622 E=RESET Q=KBD_RC_EN[29] R=$abc$4874$n300
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFESR C=CLK D=$abc$4874$n624 E=RESET Q=KBD_RC_EN[30] R=$abc$4874$n300
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFESR C=CLK D=$abc$4874$n626 E=RESET Q=KBD_RC_EN[31] R=$abc$4874$n300
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFESR C=CLK D=$abc$4874$n627 E=RESET Q=KBD_RC_EN[32] R=$abc$4874$n300
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFESR C=CLK D=$abc$4874$n628 E=RESET Q=KBD_RC_EN[33] R=$abc$4874$n300
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFE C=CLK D=$true E=$abc$4874$n23 Q=com_msg[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFE C=CLK D=$true E=$abc$4874$n23 Q=com_msg[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFE C=CLK D=$true E=$abc$4874$n23 Q=com_msg[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFE C=CLK D=$true E=$abc$4874$n23 Q=com_msg[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFE C=CLK D=$true E=$abc$4874$n23 Q=com_msg[4]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFE C=CLK D=$true E=$abc$4874$n23 Q=com_msg[5]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFE C=CLK D=$0\com_msg[11:0][6] E=RESET Q=com_msg[6]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFE C=CLK D=$0\com_msg[11:0][7] E=RESET Q=com_msg[7]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFE C=CLK D=$0\com_msg[11:0][8] E=RESET Q=com_msg[8]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFE C=CLK D=$0\com_msg[11:0][9] E=RESET Q=com_msg[9]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFE C=CLK D=$0\com_msg[11:0][10] E=RESET Q=com_msg[10]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFE C=CLK D=$0\com_msg[11:0][11] E=RESET Q=com_msg[11]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFSS C=CLK D=$5\com_len[2:0][0] Q=com_len[0] S=$abc$4874$n9
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
|
|
.gate SB_DFFSR C=CLK D=$5\com_len[2:0][1] Q=com_len[1] R=$abc$4874$n9
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
|
|
.gate SB_DFFSR C=CLK D=$5\com_len[2:0][2] Q=com_len[2] R=$abc$4874$n9
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
|
|
.gate SB_DFF C=CLK D=$0\rststate[3:0][0] Q=rststate[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
|
|
.gate SB_DFF C=CLK D=$0\rststate[3:0][1] Q=rststate[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
|
|
.gate SB_DFF C=CLK D=$0\rststate[3:0][2] Q=rststate[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
|
|
.gate SB_DFF C=CLK D=$0\rststate[3:0][3] Q=rststate[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
|
|
.gate SB_DFFE C=CLK D=$false E=$abc$4874$n35 Q=UART_WR
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFE C=CLK D=$0\UART_TX_DATA[5:0][0] E=$abc$4874$n37 Q=UART_TX_DATA[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFE C=CLK D=$0\UART_TX_DATA[5:0][1] E=$abc$4874$n37 Q=UART_TX_DATA[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFE C=CLK D=$0\UART_TX_DATA[5:0][2] E=$abc$4874$n37 Q=UART_TX_DATA[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFE C=CLK D=$0\UART_TX_DATA[5:0][3] E=$abc$4874$n37 Q=UART_TX_DATA[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFE C=CLK D=$0\UART_TX_DATA[5:0][4] E=$abc$4874$n37 Q=UART_TX_DATA[4]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFE C=CLK D=$0\UART_TX_DATA[5:0][5] E=$abc$4874$n37 Q=UART_TX_DATA[5]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFESS C=CLK D=$2\dbg_led[2:0][0] E=$abc$4874$n58 Q=dbg_led[0] S=$abc$4874$n9
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFESR C=CLK D=$2\dbg_led[2:0][1] E=$abc$4874$n58 Q=dbg_led[1] R=$abc$4874$n9
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:32|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
|
|
.gate SB_DFFNSR C=CLK D=$abc$4874$n381 Q=UART.tx_activity R=$abc$4874$n9
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:28|uart.v:25|/usr/local/bin/../share/yosys/ice40/cells_map.v:1"
|
|
.gate SB_DFFNE C=CLK D=$abc$4874$n3 E=$abc$4874$n64 Q=$abc$4874$n6
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:28|uart.v:25|/usr/local/bin/../share/yosys/ice40/cells_map.v:7"
|
|
.gate SB_DFFNESR C=CLK D=$abc$4874$n269 E=$abc$4874$n61 Q=UART.tx_clk_counter[0] R=$abc$4874$n11
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:28|uart.v:25|/usr/local/bin/../share/yosys/ice40/cells_map.v:7"
|
|
.gate SB_DFFNESR C=CLK D=$abc$4874$n384 E=$abc$4874$n61 Q=UART.tx_clk_counter[1] R=$abc$4874$n11
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:28|uart.v:25|/usr/local/bin/../share/yosys/ice40/cells_map.v:7"
|
|
.gate SB_DFFNESR C=CLK D=$abc$4874$n272 E=$abc$4874$n61 Q=UART.tx_clk_counter[2] R=$abc$4874$n11
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:28|uart.v:25|/usr/local/bin/../share/yosys/ice40/cells_map.v:7"
|
|
.gate SB_DFFNESS C=CLK D=$abc$4874$n386 E=$abc$4874$n61 Q=UART.tx_clk_counter[3] S=$abc$4874$n11
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:28|uart.v:25|/usr/local/bin/../share/yosys/ice40/cells_map.v:7"
|
|
.gate SB_DFFNESR C=CLK D=$abc$4874$n275 E=$abc$4874$n61 Q=UART.tx_clk_counter[4] R=$abc$4874$n11
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:28|uart.v:25|/usr/local/bin/../share/yosys/ice40/cells_map.v:7"
|
|
.gate SB_DFFNESS C=CLK D=$abc$4874$n388 E=$abc$4874$n61 Q=UART.tx_clk_counter[5] S=$abc$4874$n11
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:28|uart.v:25|/usr/local/bin/../share/yosys/ice40/cells_map.v:7"
|
|
.gate SB_DFFNESS C=CLK D=$abc$4874$n389 E=$abc$4874$n61 Q=UART.tx_clk_counter[6] S=$abc$4874$n11
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:28|uart.v:25|/usr/local/bin/../share/yosys/ice40/cells_map.v:7"
|
|
.gate SB_DFFNESS C=CLK D=$abc$4874$n431 E=$abc$4874$n64 Q=UART.tx_bit_counter[0] S=$abc$4874$n11
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:28|uart.v:25|/usr/local/bin/../share/yosys/ice40/cells_map.v:7"
|
|
.gate SB_DFFNESR C=CLK D=$abc$4874$n432 E=$abc$4874$n64 Q=UART.tx_bit_counter[1] R=$abc$4874$n11
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:28|uart.v:25|/usr/local/bin/../share/yosys/ice40/cells_map.v:7"
|
|
.gate SB_DFFNESR C=CLK D=$abc$4874$n434 E=$abc$4874$n64 Q=UART.tx_bit_counter[2] R=$abc$4874$n11
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:28|uart.v:25|/usr/local/bin/../share/yosys/ice40/cells_map.v:7"
|
|
.gate SB_DFFNESS C=CLK D=$abc$4874$n436 E=$abc$4874$n64 Q=UART.tx_bit_counter[3] S=$abc$4874$n11
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:28|uart.v:25|/usr/local/bin/../share/yosys/ice40/cells_map.v:7"
|
|
.gate SB_DFFNE C=CLK D=UART_WR E=RESET Q=UART.TX_sig_last
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:28|uart.v:25|/usr/local/bin/../share/yosys/ice40/cells_map.v:7"
|
|
.gate SB_IO D_IN_0=KBD_RC_IN[0] D_OUT_0=$false OUTPUT_ENABLE=KBD_RC_EN[0] PACKAGE_PIN=KBD_RC[0]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:131"
|
|
.param PIN_TYPE 101001
|
|
.param PULLUP 1
|
|
.gate SB_IO D_IN_0=KBD_RC_IN[10] D_OUT_0=$false OUTPUT_ENABLE=KBD_RC_EN[10] PACKAGE_PIN=KBD_RC[10]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:131"
|
|
.param PIN_TYPE 101001
|
|
.param PULLUP 1
|
|
.gate SB_IO D_IN_0=KBD_RC_IN[11] D_OUT_0=$false OUTPUT_ENABLE=KBD_RC_EN[11] PACKAGE_PIN=KBD_RC[11]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:131"
|
|
.param PIN_TYPE 101001
|
|
.param PULLUP 1
|
|
.gate SB_IO D_IN_0=KBD_RC_IN[12] D_OUT_0=$false OUTPUT_ENABLE=KBD_RC_EN[12] PACKAGE_PIN=KBD_RC[12]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:131"
|
|
.param PIN_TYPE 101001
|
|
.param PULLUP 1
|
|
.gate SB_IO D_IN_0=KBD_RC_IN[13] D_OUT_0=$false OUTPUT_ENABLE=KBD_RC_EN[13] PACKAGE_PIN=KBD_RC[13]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:131"
|
|
.param PIN_TYPE 101001
|
|
.param PULLUP 1
|
|
.gate SB_IO D_IN_0=KBD_RC_IN[14] D_OUT_0=$false OUTPUT_ENABLE=KBD_RC_EN[14] PACKAGE_PIN=KBD_RC[14]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:131"
|
|
.param PIN_TYPE 101001
|
|
.param PULLUP 1
|
|
.gate SB_IO D_IN_0=KBD_RC_IN[15] D_OUT_0=$false OUTPUT_ENABLE=KBD_RC_EN[15] PACKAGE_PIN=KBD_RC[15]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:131"
|
|
.param PIN_TYPE 101001
|
|
.param PULLUP 1
|
|
.gate SB_IO D_IN_0=KBD_RC_IN[16] D_OUT_0=$false OUTPUT_ENABLE=KBD_RC_EN[16] PACKAGE_PIN=KBD_RC[16]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:131"
|
|
.param PIN_TYPE 101001
|
|
.param PULLUP 1
|
|
.gate SB_IO D_IN_0=KBD_RC_IN[17] D_OUT_0=$false OUTPUT_ENABLE=KBD_RC_EN[17] PACKAGE_PIN=KBD_RC[17]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:131"
|
|
.param PIN_TYPE 101001
|
|
.param PULLUP 1
|
|
.gate SB_IO D_IN_0=KBD_RC_IN[18] D_OUT_0=$false OUTPUT_ENABLE=KBD_RC_EN[18] PACKAGE_PIN=KBD_RC[18]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:131"
|
|
.param PIN_TYPE 101001
|
|
.param PULLUP 1
|
|
.gate SB_IO D_IN_0=KBD_RC_IN[19] D_OUT_0=$false OUTPUT_ENABLE=KBD_RC_EN[19] PACKAGE_PIN=KBD_RC[19]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:131"
|
|
.param PIN_TYPE 101001
|
|
.param PULLUP 1
|
|
.gate SB_IO D_IN_0=KBD_RC_IN[1] D_OUT_0=$false OUTPUT_ENABLE=KBD_RC_EN[1] PACKAGE_PIN=KBD_RC[1]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:131"
|
|
.param PIN_TYPE 101001
|
|
.param PULLUP 1
|
|
.gate SB_IO D_IN_0=KBD_RC_IN[20] D_OUT_0=$false OUTPUT_ENABLE=KBD_RC_EN[20] PACKAGE_PIN=KBD_RC[20]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:131"
|
|
.param PIN_TYPE 101001
|
|
.param PULLUP 1
|
|
.gate SB_IO D_IN_0=KBD_RC_IN[21] D_OUT_0=$false OUTPUT_ENABLE=KBD_RC_EN[21] PACKAGE_PIN=KBD_RC[21]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:131"
|
|
.param PIN_TYPE 101001
|
|
.param PULLUP 1
|
|
.gate SB_IO D_IN_0=KBD_RC_IN[22] D_OUT_0=$false OUTPUT_ENABLE=KBD_RC_EN[22] PACKAGE_PIN=KBD_RC[22]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:131"
|
|
.param PIN_TYPE 101001
|
|
.param PULLUP 1
|
|
.gate SB_IO D_IN_0=KBD_RC_IN[23] D_OUT_0=$false OUTPUT_ENABLE=KBD_RC_EN[23] PACKAGE_PIN=KBD_RC[23]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:131"
|
|
.param PIN_TYPE 101001
|
|
.param PULLUP 1
|
|
.gate SB_IO D_IN_0=KBD_RC_IN[24] D_OUT_0=$false OUTPUT_ENABLE=KBD_RC_EN[24] PACKAGE_PIN=KBD_RC[24]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:131"
|
|
.param PIN_TYPE 101001
|
|
.param PULLUP 1
|
|
.gate SB_IO D_IN_0=KBD_RC_IN[25] D_OUT_0=$false OUTPUT_ENABLE=KBD_RC_EN[25] PACKAGE_PIN=KBD_RC[25]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:131"
|
|
.param PIN_TYPE 101001
|
|
.param PULLUP 1
|
|
.gate SB_IO D_IN_0=KBD_RC_IN[26] D_OUT_0=$false OUTPUT_ENABLE=KBD_RC_EN[26] PACKAGE_PIN=KBD_RC[26]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:131"
|
|
.param PIN_TYPE 101001
|
|
.param PULLUP 1
|
|
.gate SB_IO D_IN_0=KBD_RC_IN[27] D_OUT_0=$false OUTPUT_ENABLE=KBD_RC_EN[27] PACKAGE_PIN=KBD_RC[27]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:131"
|
|
.param PIN_TYPE 101001
|
|
.param PULLUP 1
|
|
.gate SB_IO D_IN_0=KBD_RC_IN[28] D_OUT_0=$false OUTPUT_ENABLE=KBD_RC_EN[28] PACKAGE_PIN=KBD_RC[28]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:131"
|
|
.param PIN_TYPE 101001
|
|
.param PULLUP 1
|
|
.gate SB_IO D_IN_0=KBD_RC_IN[29] D_OUT_0=$false OUTPUT_ENABLE=KBD_RC_EN[29] PACKAGE_PIN=KBD_RC[29]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:131"
|
|
.param PIN_TYPE 101001
|
|
.param PULLUP 1
|
|
.gate SB_IO D_IN_0=KBD_RC_IN[2] D_OUT_0=$false OUTPUT_ENABLE=KBD_RC_EN[2] PACKAGE_PIN=KBD_RC[2]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:131"
|
|
.param PIN_TYPE 101001
|
|
.param PULLUP 1
|
|
.gate SB_IO D_IN_0=KBD_RC_IN[30] D_OUT_0=$false OUTPUT_ENABLE=KBD_RC_EN[30] PACKAGE_PIN=KBD_RC[30]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:131"
|
|
.param PIN_TYPE 101001
|
|
.param PULLUP 1
|
|
.gate SB_IO D_IN_0=KBD_RC_IN[31] D_OUT_0=$false OUTPUT_ENABLE=KBD_RC_EN[31] PACKAGE_PIN=KBD_RC[31]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:131"
|
|
.param PIN_TYPE 101001
|
|
.param PULLUP 1
|
|
.gate SB_IO D_IN_0=KBD_RC_IN[32] D_OUT_0=$false OUTPUT_ENABLE=KBD_RC_EN[32] PACKAGE_PIN=KBD_RC[32]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:131"
|
|
.param PIN_TYPE 101001
|
|
.param PULLUP 1
|
|
.gate SB_IO D_IN_0=KBD_RC_IN[33] D_OUT_0=$false OUTPUT_ENABLE=KBD_RC_EN[33] PACKAGE_PIN=KBD_RC[33]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:131"
|
|
.param PIN_TYPE 101001
|
|
.param PULLUP 1
|
|
.gate SB_IO D_IN_0=KBD_RC_IN[3] D_OUT_0=$false OUTPUT_ENABLE=KBD_RC_EN[3] PACKAGE_PIN=KBD_RC[3]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:131"
|
|
.param PIN_TYPE 101001
|
|
.param PULLUP 1
|
|
.gate SB_IO D_IN_0=KBD_RC_IN[4] D_OUT_0=$false OUTPUT_ENABLE=KBD_RC_EN[4] PACKAGE_PIN=KBD_RC[4]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:131"
|
|
.param PIN_TYPE 101001
|
|
.param PULLUP 1
|
|
.gate SB_IO D_IN_0=KBD_RC_IN[5] D_OUT_0=$false OUTPUT_ENABLE=KBD_RC_EN[5] PACKAGE_PIN=KBD_RC[5]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:131"
|
|
.param PIN_TYPE 101001
|
|
.param PULLUP 1
|
|
.gate SB_IO D_IN_0=KBD_RC_IN[6] D_OUT_0=$false OUTPUT_ENABLE=KBD_RC_EN[6] PACKAGE_PIN=KBD_RC[6]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:131"
|
|
.param PIN_TYPE 101001
|
|
.param PULLUP 1
|
|
.gate SB_IO D_IN_0=KBD_RC_IN[7] D_OUT_0=$false OUTPUT_ENABLE=KBD_RC_EN[7] PACKAGE_PIN=KBD_RC[7]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:131"
|
|
.param PIN_TYPE 101001
|
|
.param PULLUP 1
|
|
.gate SB_IO D_IN_0=KBD_RC_IN[8] D_OUT_0=$false OUTPUT_ENABLE=KBD_RC_EN[8] PACKAGE_PIN=KBD_RC[8]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:131"
|
|
.param PIN_TYPE 101001
|
|
.param PULLUP 1
|
|
.gate SB_IO D_IN_0=KBD_RC_IN[9] D_OUT_0=$false OUTPUT_ENABLE=KBD_RC_EN[9] PACKAGE_PIN=KBD_RC[9]
|
|
.attr module_not_derived 00000000000000000000000000000001
|
|
.attr src "top.v:131"
|
|
.param PIN_TYPE 101001
|
|
.param PULLUP 1
|
|
.names dbg_led[0] DBG_LED[0]
|
|
1 1
|
|
.names dbg_led[1] DBG_LED[1]
|
|
1 1
|
|
.names KBD_RC_IN[23] DBG_LED[2]
|
|
1 1
|
|
.names CLK UART.CLK
|
|
1 1
|
|
.names RESET UART.RESET
|
|
1 1
|
|
.names UART.tx_activity UART.TX_ACTIVITY
|
|
1 1
|
|
.names UART_TX_DATA[0] UART.TX_BYTE[0]
|
|
1 1
|
|
.names UART_TX_DATA[1] UART.TX_BYTE[1]
|
|
1 1
|
|
.names UART_TX_DATA[2] UART.TX_BYTE[2]
|
|
1 1
|
|
.names UART_TX_DATA[3] UART.TX_BYTE[3]
|
|
1 1
|
|
.names UART_TX_DATA[4] UART.TX_BYTE[4]
|
|
1 1
|
|
.names UART_TX_DATA[5] UART.TX_BYTE[5]
|
|
1 1
|
|
.names $undef UART.TX_BYTE[6]
|
|
1 1
|
|
.names $undef UART.TX_BYTE[7]
|
|
1 1
|
|
.names DBG_TX UART.TX_LINE
|
|
1 1
|
|
.names UART_WR UART.TX_SIGNAL
|
|
1 1
|
|
.names DBG_TX UART.tx_line
|
|
1 1
|
|
.names UART.tx_activity UART_ACTIVE
|
|
1 1
|
|
.names $undef UART_TX_DATA[6]
|
|
1 1
|
|
.names $undef UART_TX_DATA[7]
|
|
1 1
|
|
.names DBG_TX UART_TX_LINE
|
|
1 1
|
|
.names $undef com_msg[12]
|
|
1 1
|
|
.names $undef com_msg[13]
|
|
1 1
|
|
.names $undef com_msg[14]
|
|
1 1
|
|
.names $undef com_msg[15]
|
|
1 1
|
|
.names $undef com_msg[16]
|
|
1 1
|
|
.names $undef com_msg[17]
|
|
1 1
|
|
.names $undef com_msg[18]
|
|
1 1
|
|
.names $undef com_msg[19]
|
|
1 1
|
|
.names $undef com_msg[20]
|
|
1 1
|
|
.names $undef com_msg[21]
|
|
1 1
|
|
.names $undef com_msg[22]
|
|
1 1
|
|
.names $undef com_msg[23]
|
|
1 1
|
|
.names $undef com_msg[24]
|
|
1 1
|
|
.names $undef com_msg[25]
|
|
1 1
|
|
.names $undef com_msg[26]
|
|
1 1
|
|
.names $undef com_msg[27]
|
|
1 1
|
|
.names $undef com_msg[28]
|
|
1 1
|
|
.names $undef com_msg[29]
|
|
1 1
|
|
.names $undef com_msg[30]
|
|
1 1
|
|
.names $undef com_msg[31]
|
|
1 1
|
|
.names $undef com_msg[32]
|
|
1 1
|
|
.names $undef com_msg[33]
|
|
1 1
|
|
.names $undef com_msg[34]
|
|
1 1
|
|
.names $undef com_msg[35]
|
|
1 1
|
|
.names $undef com_msg[36]
|
|
1 1
|
|
.names $undef com_msg[37]
|
|
1 1
|
|
.names $undef com_msg[38]
|
|
1 1
|
|
.names $undef com_msg[39]
|
|
1 1
|
|
.names $undef com_msg[40]
|
|
1 1
|
|
.names $undef com_msg[41]
|
|
1 1
|
|
.names $undef com_msg[42]
|
|
1 1
|
|
.names $undef com_msg[43]
|
|
1 1
|
|
.names $undef com_msg[44]
|
|
1 1
|
|
.names $undef com_msg[45]
|
|
1 1
|
|
.names $undef com_msg[46]
|
|
1 1
|
|
.names $undef com_msg[47]
|
|
1 1
|
|
.names $undef dbg_led[2]
|
|
1 1
|
|
.end
|