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226 lines
8.0 KiB
226 lines
8.0 KiB
module matrix_kbd (input CLK, input RESET, input FREEZE, inout [15:0] ROWS, input [7:0] COLUMNS, output [7:0] kbd_r0, kbd_r2, kbd_r3, kbd_r4, kbd_r5, kbd_r6, kbd_r7, output INT);
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// * - ESC (29), 7 - F1 (3A), 4 - F2 (3B), 1 - NUM_LOCK (53)
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// 0 - CAPS LOCK (39), 8 - R (15), 5 - BACKSPACE (2A), 2 - ENTER (58)
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// # - LSHIFT (E1), 9 - C (06), 6 - V (19), 3 - DELETE (4C)
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// D - LCTRL (E0), C - LALT (E2), B - SPACE (2C), A - RGUI (E7)
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parameter ONE_ROW_TIME = 8000;
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parameter ROW_STT_PROCESS_TIME = 7000;
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parameter ONE_COLUMN_PROCESS_TIME = 50;
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parameter ONE_ROW_TIME_POW = 12; // 15 - 65536 tacts or 5.46 ms, 14 - 32768 tacts or 2.73 ms, 13 - 16384 tacts or 1.36 ms,
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// 12 - 8191 tacts or 683 mks, 11 - 4096 tacts or 341 mks, 10 - 2048 tacts or 171 ms, 9 - 1024 tacts or 85 mks, 8 - 512 tacts or 43 ms,
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// 7 - 256 tacts or 21 mks, other values have no guaranties
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parameter ONE_CALC_TIME_POW = 4; // 3 - 16 tacts or 1.3 mks, 4 - 32 tacts or 2.7 mks, 5 - 64 tacts or 5.3 mks, 6 - 128 tacts or 10.7 mks
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// ONE_ROW_TIME_POW > (ONE_CALC_TIME_POW - 3); ONE_CALC_TIME_POW > 2 (if 2 or smaller, top module overrun may occur)
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reg [12:0] row_time = 0;
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reg [3:0] row_counter;
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reg [7:0] temp;
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reg [7:0] i;
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reg [7:0] report [6:0]; // NO BYTE 2
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reg isr;
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reg [15:0] ROWS_EN = 0;
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reg [15:0] ROWS_OUT = 0;
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wire [15:0] ROWS_IN;
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reg [7:0] COLS_SHADOW;
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reg [7:0] kbd_code;
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wire [7:0] kbd_code_hid;
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reg is_pressed;
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reg ram_wr;
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reg [8:0] ram_adr;
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wire [7:0] ram_rd;
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reg [3:0] init_delay_cnt;
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reg [8:0] init_ram_cnt;
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/*always @ (negedge CLK) begin
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COLS_SHADOW <= COLUMNS;
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end*/
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ram RAM (CLK, ram_wr, ram_adr, temp, ram_adr, ram_rd);//module ram(input clk, wen, input [8:0] addr, input [7:0] wdata, output [7:0] rdata);
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always @ (posedge CLK) begin
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if (RESET == 0) begin
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for (i = 0; i < 6; i = i + 1)
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report[i] = 0;
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isr = 0;
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init_delay_cnt = 0;
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init_ram_cnt = 0;
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row_time = 0;
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end
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else begin
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if (FREEZE == 0) begin
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if (init_delay_cnt != 15)
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init_delay_cnt = init_delay_cnt + 1;
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else if (init_ram_cnt < 256) begin
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ram_wr = 1;
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ram_adr = init_ram_cnt;
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temp = 255;
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init_ram_cnt = init_ram_cnt + 1;
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end
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/*else if (init_ram_cnt == 256) begin
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ram_wr = 0;
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init_ram_cnt = init_ram_cnt + 1;
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end*/
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else begin
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row_time = row_time + 1;
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if (row_time == 0) begin//== ONE_ROW_TIME) begin
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ram_wr = 0;
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//row_time <= 0;
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row_counter = row_counter + 1;
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ROWS_EN = 1 << row_counter;
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ram_adr = row_counter;
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end
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// ROW 0 - D, 1 - A, 2 - C, 3 - B
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/*if (row_time == (ROW_STT_PROCESS_TIME - 1)) begin
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temp = ram_rd;
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COLS_SHADOW <= COLUMNS;
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end*/
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//if (row_time == 8191/*(ROW_STT_PROCESS_TIME + ONE_COLUMN_PROCESS_TIME * 7 + 1)*/)
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// ram_wr = 1;
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if ((row_time[12:8] == 31) && (row_time[4:0] == 0)) begin
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//temp = ram_rd;
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//COLS_SHADOW = COLUMNS;
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if (row_time[7:5] == 0) begin
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temp = ram_rd;
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COLS_SHADOW = COLUMNS;
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end
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check_column (row_time[7:5]);
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if (row_time[7:5] == 7)
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ram_wr = 1;
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end
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else
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kbd_code = 255;
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/*if (row_time == (ROW_STT_PROCESS_TIME + ONE_COLUMN_PROCESS_TIME * 0))
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check_column (0);
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else if (row_time == (ROW_STT_PROCESS_TIME + ONE_COLUMN_PROCESS_TIME * 2))
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check_column (2);
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else if (row_time == (ROW_STT_PROCESS_TIME + ONE_COLUMN_PROCESS_TIME * 1))
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check_column (1);
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else if (row_time == (ROW_STT_PROCESS_TIME + ONE_COLUMN_PROCESS_TIME * 3))
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check_column (3);
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else if (row_time == (ROW_STT_PROCESS_TIME + ONE_COLUMN_PROCESS_TIME * 4))
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check_column (4);
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else if (row_time == (ROW_STT_PROCESS_TIME + ONE_COLUMN_PROCESS_TIME * 5))
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check_column (5);
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else if (row_time == (ROW_STT_PROCESS_TIME + ONE_COLUMN_PROCESS_TIME * 6))
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check_column (6);
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else if (row_time == (ROW_STT_PROCESS_TIME + ONE_COLUMN_PROCESS_TIME * 7))
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check_column (7);
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else
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kbd_code = 255;*/
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// START PACK I2C_HID REPORT
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if (kbd_code_hid != 0) begin
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if (kbd_code_hid[7:3] == 5'b11100) begin
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//if ((kbd_code_hid > 8'hDF) && (kbd_code_hid < 8'hE8)) begin
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if (is_pressed)
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report [0] = report [0] | (1<<(kbd_code_hid & 8'h07));
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else
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report [0] <= report [0] & (~(1<<(kbd_code_hid & 8'h07)));
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isr = 1;
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end
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else begin
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if (is_pressed) begin
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isr = 1;
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if (report [ 1 ] == 0)
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report [ 1 ] <= kbd_code_hid;
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else if (report [ 2 ] == 0)
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report [ 2 ] <= kbd_code_hid;
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else if (report [ 3 ] == 0)
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report [ 3 ] <= kbd_code_hid;
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else if (report [ 4 ] == 0)
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report [ 4 ] <= kbd_code_hid;
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else if (report [ 5 ] == 0)
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report [ 5 ] <= kbd_code_hid;
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else if (report [ 6 ] == 0)
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report [ 6 ] <= kbd_code_hid;
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else
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isr = 0;
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end
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else begin
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for (i = 1; i < 7; i = i + 1) begin
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if (report [i] == kbd_code_hid/*kbd_code*/) begin
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report [i] = 0;
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isr = 1;
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end
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end
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end
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end
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end // END OF KBD CODE SEND ALG
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else
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isr <= 0;
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end
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end
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end
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end
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task check_column;
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input [2:0] column;
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begin
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if (COLS_SHADOW[column] != temp[column]) begin
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kbd_code = row_counter*8 + column;
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if ((COLS_SHADOW[column] == 0) && (temp[column] == 1)) is_pressed = 1;
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else is_pressed = 0;
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end
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else kbd_code = 255;
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temp[column] = COLS_SHADOW[column];
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end
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endtask
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assign kbd_r0 = report[0];
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assign kbd_r2 = report[1];
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assign kbd_r3 = report[2];
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assign kbd_r4 = report[3];
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assign kbd_r5 = report[4];
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assign kbd_r6 = report[5];
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assign kbd_r7 = report[6];
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assign INT = isr;
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SB_RAM40_4K #(
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.INIT_0(256'h0000_0001_0001_0001_00E7_0058_004C_0053__0001_0001_0001_0001_00E0_0039_00E1_0029), // ROW 0-1
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.INIT_1(256'h0001_0001_0001_0001_002C_002A_0019_003B__0001_0001_0001_0001_00E2_0015_0006_003A), // ROW 2-3
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.INIT_2(256'h0001_0001_0001_0001_002C_002A_0019_003B__0001_0001_0001_0001_00E2_0015_0006_003A), // ROW 4-5
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.INIT_3(256'h0001_0001_0001_0001_002C_002A_0019_003B__0001_0001_0001_0001_00E2_0015_0006_003A), // ROW 6-7
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.INIT_4(256'h0001_0001_0001_0001_002C_002A_0019_003B__0001_0001_0001_0001_00E2_0015_0006_003A), // ROW 8-9
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.INIT_5(256'h0001_0001_0001_0001_002C_002A_0019_003B__0001_0001_0001_0001_00E2_0015_0006_003A), // ROW 10-11
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.INIT_6(256'h0001_0001_0001_0001_002C_002A_0019_003B__0001_0001_0001_0001_00E2_0015_0006_003A), // ROW 12-13
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.INIT_7(256'h0001_0001_0001_0001_002C_002A_0019_003B__0001_0001_0001_0001_00E2_0015_0006_003A), // ROW 14-15
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.INIT_8(256'h0001_0001_0001_0001_002C_002A_0019_003B__0001_0001_0001_0001_00E2_0015_0006_003A), // ROW 16-17
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.INIT_9(256'h0001_0001_0001_0001_002C_002A_0019_003B__0001_0001_0001_0001_00E2_0015_0006_003A), // ROW 18-19
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.WRITE_MODE(1),
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.READ_MODE(1)
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) kbd_codes (
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.RDATA(kbd_code_hid),
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.RADDR(kbd_code),
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.RCLK(CLK),
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.RCLKE(1'b1),
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.RE(1'b1),
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.WADDR(8'b0),
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.WCLK(1'b0),
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.WCLKE(1'b0),
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.WDATA(8'b0),
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.WE(1'b0)
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);
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SB_IO #(
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.PIN_TYPE(6'b 1010_01),
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.PULLUP(1'b 0)
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) rows_io [15:0] (
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.PACKAGE_PIN(ROWS),
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.OUTPUT_ENABLE(ROWS_EN),
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.D_OUT_0(ROWS_OUT),
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.D_IN_0(ROWS_IN)
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);
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endmodule
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