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module test_counter;
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reg clk, SCL, SDA;
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wire SDA_OUT, I2C_ACTIVITY, I2C_READ, ACK, WR;
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wire [7:0] received_byte, byte_to_transmit;
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reg [7:0] to_tx = 8'hC5;
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wire [8:0] i2c_counter;
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reg [8:0] i, j;
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reg [8:0] data_to [4:0]/* = { 9'h98, 9'h00, 9'h23, 9'h10, 9'h98 }*/;
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//reg [8:0] data_to = 9'h98;
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//устанавливаем экземпляр тестируемого модуля
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i2c_slave i2c(clk, SCL, SDA, SDA_OUT, I2C_ACTIVITY, I2C_READ, ACK, WR, received_byte, byte_to_transmit, i2c_counter);
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//module i2c_slave (input CLK,
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// input SCL, /*inout SDA,*/SDA_IN, output SDA_OUT, // FOR TEST
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// output IS_TRANSMISSION, output IS_READ, output IS_ACK, output WR, //output ACK_MASTER_CTRL,
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// output reg [7:0] RECEIVED_BYTE, input [7:0] BYTE_TO_TRANSMIT,
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// output [(MAX_I2C_TRANSACTION_EXP2-1):0] COUNTER);
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//моделируем сигнал тактовой частоты
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always
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begin
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#1 clk = ~clk;
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data_to[0] = 9'hd0; // TX (ADRESS 34)
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data_to[1] = 9'h00;
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data_to[2] = 9'h46;
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data_to[3] = 9'h10;
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data_to[4] = 9'h98;
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/*data_to[0] = 9'hd2; // RX (ADRESS 34)
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data_to[1] = 9'h1FE;
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data_to[2] = 9'h1FE;
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data_to[3] = 9'h1FE;
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data_to[4] = 9'h1FF;*/
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end
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//от начала времени...
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parameter SDA_STT = 30;
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parameter SCL_H = 100;
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parameter SCL_L1 = 70;
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parameter SCL_L2 = 30;
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assign byte_to_transmit = to_tx;
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initial
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begin
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//byte_to_transmit = 8'hC5;
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clk = 0;
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SCL = 1;
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//SDA_CTRL = 1;
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to_tx = 8'hC5;
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SDA = 1;
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#500 SDA = 0;
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#SDA_STT SCL = 0;
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for (i = 0; i < 5; i++)
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begin
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#200 for (j = 0; j < 9; j++)
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begin
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#SCL_L1 SDA = data_to[i][8-j]; // first bit start
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#SCL_L2 SCL = 1; // CLOCK of first bit
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#SCL_H SCL = 0;
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end
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end
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#200 SDA = 0;
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#200 SCL = 1;
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#40 SDA = 1;
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/*
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#SCL_L1 SDA = 1; // first bit start
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#SCL_L2 SCL = 1; // CLOCK of first bit
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#SCL_H SCL = 0; // bit 7
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#SCL_L1 SDA = 0;
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#SCL_L2 SCL = 1;
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#SCL_H SCL = 0; // 6
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#SCL_L1 SDA = 1;
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#SCL_L2 SCL = 1;
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#SCL_H SCL = 0; // 5
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#SCL_L1 SDA = 0;
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#SCL_L2 SCL = 1;
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#SCL_H SCL = 0; // 4
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#SCL_L1 SDA = 0;
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#SCL_L2 SCL = 1;
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#SCL_H SCL = 0; // 4
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#SCL_L1 SDA = 0;
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#SCL_L2 SCL = 1;
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#SCL_H SCL = 0; // 3
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#SCL_L1 SDA = 0;
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#SCL_L2 SCL = 1;
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#SCL_H SCL = 0; // 2
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#SCL_L1 SDA = 0;
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#SCL_L2 SCL = 1;
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#SCL_H SCL = 0; // 1
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*/
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end
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/*
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//через временной интервал "50" подаем сигнал сброса
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#50 SCL = 1;
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//еще через время "4" снимаем сигнал сброса
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#4 SCL = 0;
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//пауза длительностью "50"
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#50;
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//ждем фронта тактовой частоты и сразу после нее подаем сигнал записи
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@(posedge clk)
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#0
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begin
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SDA = 0;
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//wr = 1'b1;
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end
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//по следующему фронту снимаем сигнал записи
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@(posedge clk)
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#0
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begin
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SDA = 1;
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//wr = 1'b0;
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end
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end
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*/
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//заканчиваем симуляцию в момент времени "400"
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initial
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begin
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#11500 $finish;
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end
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//создаем файл VCD для последующего анализа сигналов
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initial
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begin
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$dumpfile("out.vcd");
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$dumpvars(0,test_counter);
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end
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//наблюдаем на некоторыми сигналами системы
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initial
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$monitor($stime,, clk,,, SCL,, SDA,, I2C_ACTIVITY);
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endmodule
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